Dual-port memory module design for composable computing

This application is a continuation of International Application No. PCT/US2021/018839, filed on Feb. 19, 2021, entitled “DUAL-PORT MEMORY MODULE DESIGN FOR COMPOSABLE COMPUTING,” the benefit of priority of which is claimed herein, and which application is hereby incorporated herein by reference in its entirety.

The present disclosure is related to computing memory modules, and in particular, to methods and apparatus to provide redundant high-speed Serializer and Deserializer (SerDes) access ports for connection to multiple computing processors or compute nodes for memory capacity composability on-demand, expansion and sharing, and composable computing enablement.

In computing applications, random-access memory (RAM) typically provides higher speed access but less total storage capacity than primary storage (e.g., hard drive storage or solid-state drive (SSD) storage). One key difference between RAM and the primary storage including NAND memory for SSD is that RAM is a byte-addressable device and accessed with memory-semantic LOAD(READ) and STORE(WRITE) commands while storage is block-addressable device and accessed with block storage protocols such Small Computer System Interface (SCSI) and Non-Volatile Memory express (NVMe). Dynamic RAM (DRAM) is a type of RAM and often used in digital electronics to provide affordable, high-speed, and high-capacity memory. A dual-inline memory module (DIMM) form factor is typically used to attach a DRAM module to a motherboard. In some examples, DRAM DIMM devices use single-port single-ended high-speed signals for attachment to a memory controller or central processing unit (CPU) with an integrated DRAM controller. A typical DRAM DIMM includes a memory module that houses multiple DRAM devices. As processing speed continue to increase, the demand for larger and faster access to DRAM will continue to increase. As different applications may have different memory capacity requirements, it is desirable that the memory capacity of a compute node or server could be changed on-demand dynamically without changing the DIMMs, such as to provide composable computing.

It is an object of various embodiments to provide an efficient architecture and methodology for implementing a dual-port RAM module to provide improved memory capacity composability, expansion and sharing. In particular, this dual-port RAM module uses high-speed SerDes (e.g., 25G NRZ, 112G PAM4, etc.) based redundant access ports for connection to multiple CPUs or compute nodes, where each access port may access part or all of the module's memory capacity under software configuration. This provides improved memory capacity composability and expansion through memory sharing and provides improved memory access performance and reliability. The Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

According to a first aspect of the present disclosure, there is provided a dual-port memory module device operable to access computer memory, the device comprising: a plurality of memory media chips providing random access memory (RAM) capacity; and a dual-port memory controller application specific integrated circuit (ASIC) operable to allocate a first portion of the RAM capacity to a first computing host and a second portion of the RAM capacity to a second computing host, the dual-port memory controller ASIC including: a first interface port coupled to a first computing host; a second interface port coupled to a second computing host; and a plurality of memory interface channels operable to configure, read data from, and write data to the plurality of memory media chips.

In a second embodiment of the dual-port memory module device according to the first aspect as such, the device further includes a management port operable to receive module configuration and management data from a configuration management server, the allocation of the a first portion of the RAM capacity and the second portion of the RAM capacity is based on the received module configuration and management data.

In a third embodiment of the dual-port memory module device according to the first aspect as such, the plurality of memory media chips includes at least one of DRAM, SRAM, HBM, STT-MRAM, or PCM.

In a fourth embodiment of the dual-port memory module device according to the first aspect as such, the device further includes a protocol agnostic multi-lane connector operable to: couple the first interface port to the first computing host; couple the second interface port to the second computing host; and couple the management port to the configuration management server.

In a fifth embodiment of the dual-port memory module device according to the first aspect as such, the protocol agnostic multi-lane connector includes an SF-TA-1002 compliant PCB connector.

In a sixth embodiment of the dual-port memory module device according to the first aspect as such, the first computing host accesses the first portion of the RAM capacity and the second computing host accesses the second portion of the RAM capacity with memory-semantic LOAD(READ) and STORE(WRITE) commands.

In a seventh embodiment of the dual-port memory module device according to the first aspect as such, the first interface port and the second interface port each include a Serial and Deserializer (SerDes) port consisting of a plurality of differential lanes for memory access protocol communication.

In an eighth embodiment of the dual-port memory module device according to the first aspect as such, the first interface port and the second interface port each may include an optional differential clock input.

In a ninth embodiment of the dual-port memory module device according to the first aspect as such, the dual-port memory controller ASIC is further operable to configure the memory media chips for access by the first computing host and the second computing host.

In a tenth embodiment of the dual-port memory module device according to the first aspect as such, the device further includes a serial presence detect device, wherein: the dual-port memory controller ASIC reads a memory media configuration from the serial presence detect device; and the configuration of the memory media chips is based on the memory media configuration.

In an eleventh embodiment of the dual-port memory module device according to the first aspect as such, the memory media configuration includes at least one of a memory media type, a memory media capacity, a memory media speed, or a number of memory media chips.

In a twelfth embodiment of the dual-port memory module device according to the first aspect as such, the dual-port memory controller ASIC is further operable to: store memory usage allocation data that indicates the allocation of the first portion of the RAM capacity to the first computing host and the allocation of the second portion of the RAM capacity to the second computing host; and in response to a device power cycle or reset event: retrieve the memory usage allocation data; and restore the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host to provide a persistent configuration in response to the device power cycle or reset event.

According to a second aspect of the present disclosure, there is provided a dual-port memory module method operable to receiving a module configuration request at a management port of a dual-port memory controller application specific integrated circuit (ASIC) of a dual-port memory module coupled by a first port to a first computing host and coupled by a second port to a second computing host; and allocating, in response to receiving the module configuration request, a first portion of RAM capacity to the first computing host and a second portion of the RAM capacity to the second computing host.

In a second embodiment of the dual-port memory module method according to the second aspect as such, the method further includes receiving a module configuration and management data from a configuration management server via a management port at the dual-port memory controller ASIC, the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host is based on the received module configuration and management data.

In a third embodiment of the dual-port memory module method according to the second aspect as such, the plurality of memory media chips includes at least one of DRAM, SRAM, HBM, STT-MRAM, or PCM.

In a fourth embodiment of the dual-port memory module method according to the second aspect as such, the dual-port memory controller ASIC further includes a protocol agnostic multi-lane connector operable to: couple the first interface port to the first computing host; couple the second interface port to the second computing host; and couple the management port to the configuration management server.

In a fifth embodiment of the dual-port memory module method according to the second aspect as such, the protocol agnostic multi-lane connector includes an SF-TA-1002 compliant PCB connector.

In a sixth embodiment of the dual-port memory module method according to the second aspect as such, the first computing host accesses the first portion of the RAM capacity and the second computing host accesses the second portion of the RAM capacity with memory-semantics LOAD(READ) and STORE(WRITE) commands.

In a seventh embodiment of the dual-port memory module method according to the second aspect as such, the method further includes receiving data on a Serial and Deserializer (SerDes) port consisting of a plurality of differential memory lanes for access protocol communication.

In an eighth embodiment of the dual-port memory module method according to the second aspect as such, the method further includes receiving a differential clock input on the first interface port and the second interface port.

In a ninth embodiment of the dual-port memory module method according to the second aspect as such, the method further includes configuring, at the dual-port memory controller ASIC, the memory media chips for access by the first computing host and the second computing host.

In a tenth embodiment of the dual-port memory module method according to the second aspect as such, the method further includes reading, at the dual-port memory controller ASIC, a memory media configuration from a serial presence detect device, the configuration of the memory media chips is based on the memory media configuration.

In an eleventh embodiment of the dual-port memory module method according to the second aspect as such, the memory media configuration includes at least one of a memory media type, a memory media capacity, a memory media speed, or a number of memory media chips.

In a twelfth embodiment of the dual-port memory module method according to the second aspect as such, the method further includes storing memory usage allocation data that indicates the allocation of the first portion of the RAM capacity to the first computing host and the allocation of the second portion of the RAM capacity to the second computing host; and in response to a device power cycle or reset event: retrieving the memory usage allocation data; and restoring the allocation of the first portion of the RAM capacity to the first computing host and the second portion of the RAM capacity to the second computing host to provide a persistent configuration in response to the device power cycle or reset event.

Any one of the foregoing examples may be combined with any one or more of the other foregoing examples to create a new embodiment in accordance with the present disclosure.

In the following description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments, and it is to be understood that other embodiments may be utilized, and that structural, logical, mechanical, and electrical changes may be made. The following description of example embodiments is, therefore, not to be taken in a limited sense.

The functions or algorithms described herein may be implemented in software in an embodiment. The software may comprise computer-executable instructions stored on computer-readable media or computer-readable storage device such as one or more non-transitory memories or other type of hardware-based storage devices, either local or networked. Further, such functions correspond to modules, which may be software, hardware, firmware, or any combination thereof. Multiple functions may be performed in one or more modules as desired, and the embodiments described are merely examples. The software may be executed on a digital signal processor, application-specific integrated circuit (ASIC), a microprocessor, or other type of processor operating on a computer system, such as a personal computer, server or other computer system, turning such computer system into a specifically programmed machine.

Machine-readable non-transitory media, such as computer-readable non-transitory media, includes all types of computer readable media, including magnetic storage media, optical storage media, and solid state storage media and specifically excludes signals. The software can be installed in and sold with the devices that handle memory allocation as taught herein. Alternatively, the software can be obtained and loaded into such devices, including obtaining the software via a disc medium or from any manner of network or distribution system, including, for example, from a server owned by the software creator or from a server not owned but used by the software creator. The software can be stored on a server for distribution over the Internet, for example.

As used herein, the term “memory module” refers to a printed circuit board assembly (PCBA) with memory control integrated circuits and memory media chips are mounted on a printed circuit board (PCB). A dual in-line memory module (DIMM) has separate contacts on each side of the PCB. Memory modules may have a 32-bit data path, a 64-bit data path or use another data path size. Different memory modules may have different numbers of pins (e.g., 72 pins, 100 pins, 144 pins, 278 pins, or 288 pins) and operate at different voltages (e.g., 5.0 V, 3.3 V, 2.5 V, 1.8 V, 1.5 V, or 1.2 V).

A host computer reads data from a memory module by providing an address to read from and a read command signal on input pins of the memory module. The memory module responds by providing the read data on output pins of the memory module. The host computer writes data to a memory module by providing an address to write to and a data value on input pins of the memory module. In case of a differential DIMM with a SerDes interface to the host, the access command and data are encapsulated into a packet transferred over the

SerDes interface.

A dual-channel memory module operates as two independent channels for accessing memory. Each channel has its own set of input and output pins. Additionally, the memory chips on the dual-channel memory module are divided between the two channels physically. Thus, data written using one channel cannot be read using the other channel Nor can the distribution of the memory between the channels be altered after manufacturing.

As described herein, a dual-port memory module provides two sets of input and output pins, but the memory capacity of the dual-port memory module is divided between the ports by a dual-port memory controller ASIC. Accordingly, the allocation of the memory capacity of the memory module to each port can be changed after manufacturing. By comparison with dual-channel memory modules, dual-port memory modules provide greater flexibility, allowing more efficient use of computing resources and enabling composable memory for composable computing. The term “multi-port memory module” encompasses memory modules with more than one port (e.g., the two ports of a dual-port memory module, three ports of a tri-port memory module, four ports of a quad-port memory module, and so on).

As used herein, the term “memory media chip” refers to the byte-addressable memory integrated circuits of a memory module for data storage. Memory media chip includes DRAM, storage class memory (SCM), magnetic RAM (MRAM), spin-transfer torque MRAM (STT-MRAM), among others. DRAM includes single data rate (SDR) DRAM, double data rate (DDR) DRAM, and synchronous DRAM (SDRAM), among others.

Signaling to and from a memory module may be provided using differential signaling or single-ended signaling. With single-ended signaling, a single pin is used to transmit each signal. The voltage of each pin is compared to the ground voltage to determine if the signal is a zero or a one. For example, if the voltage on the pin is at least a threshold above the ground voltage, the signal is a logical one and if the voltage does not meet the threshold, the signal is a logical zero. With differential signaling, two pins are used to transmit each signal. The voltage of one pin is compared to the other to determine if the signal is a zero or a one. For example, if the two pins are within a threshold voltage of each other, the signal is a logical zero and if the difference exceeds the threshold, the signal is a logical one.

As used herein, the term “communication lane” refers to a pair of data transfer connections, one for input and one for output. With differential signaling, each communication lane of a memory module uses four pins, two for the input differential signal and two for the output differential signal.

One way to increase the data transfer rate of memory modules is to increase the number of communication lanes, allowing more data to be sent or received in parallel on each clock cycle. However, reducing the size of pins increases cross-talk and increasing the number of pins without reducing their size increases the size of the memory module, neither of which is desirable.

Another way to increase the data transfer rate of memory modules is to increase the operating clock frequency, allowing more data to be transferred per lane per second. The clock frequency for communication between the computing host and the memory module can be increased by a factor and the number of lanes divided by the same factor, keeping the data transfer rate the same while reducing the number of pins on the memory module. A SerDes is implemented on each side of the connection to convert data signals between wide data (e.g., 64 lanes) at a lower frequency (e.g., 1 GHz) and narrow data (e.g., 8 lanes) at a higher frequency (e.g., 8 GHz). Thus, the data from multiple lanes (eight, in this example) is “serialized” and output sequentially onto one lane. On the other side of the connection, sequentially received data is “deserialized” and output in parallel on multiple lanes (also eight, in this example). More complex coding schemes, such as 8B/10B, 64B/65B or 128B/129B than signal multiplexing, may be used in some embodiments.

illustrates an example of DRAM DIMM system. The systemincludes a DRAM DIMMwhich includes a register clock driver (RCD)and number of DRAM devices, such as eighteen or thirty-six DRAM devices for error correction code (ECC) DIMM. A DRAM DIMMmay be attached to a DIMM socket, such as to connect the DRAM DIMMto a host (a central processing unit (CPU) or a SoC or a DRAM controller). A DRAM DIMMuses single-port single-ended high-speed signals for attachment to a host. DRAM data rates have been evolving from 200 megatransfers per second (MT/s) in DDR1 in 1998 to 6400 MT/s DDR5 defined by JEDEC in 2020.

illustrate example DIMM configurations. The DIMM configurationsinclude unregistered DIMM (UDIMM), where the command, address, data, and clock signals of DRAM chipsare connected to a host directly without being registered or regenerated. The DIMM configurationsinclude a registered DIMM (RDIMM), where the command and address signals between the host and DRAM chipsare buffered with registers and the clock signal is regenerated with a phase locked loop (PLL), but the data signals are not buffered and connected to the host directly. The DIMM configurationsinclude a load-reduced DIMM (LRDIMM), where the command, address and data signals between the Host and DRAM chipsare buffered with registers, and the clock signal is regenerated with a PLL.

illustrate an example dual-channel DDR5 DIMMdefined by JEDEC DRAM standard committee. The dual-channel DIMMincludes a generalized dual-channel DIMM, which includes an independent communication channel Aand another independent communication channel B. The dual-channel DIMMincludes an RDIMM, which includes an independent RDIMM communication channel Aand another independent RDIMM communication channel B. The dual-channel DIMMincludes an LRDIMM, which includes an independent LRDIMM communication channel Aand another independent LRDIMM communication channel B.

illustrate an example double data rate (DDR) throughput comparison. The DDR throughput comparisonincludes a DDR comparison table, which compares features of various types of DDR memory. As shown in the table, a 288-pin DDR4 DIMM includes UDIMM, RDIMM, and LRDIMM, uses one 64+8 bits channel per DIMM for data rate up to 3200 MT/s. A 288-pin DDR5 DIMM includes RDIMM and LRDIMM, but splits into two independent 32+8 bits channels for data rate up to 6400 MT/s. The data transfer rate for these DDR4 and DDR5 SDRAM DIMMs with a host may be increased by using a differential Serializer and Deserializer (SerDes) communication interface. As shown in memory capacity improvement graph, memory density increases as memory progresses from DDR to DDR5. As shown in memory interface improvement graph, transfer rates increase as memory progresses from DDR to DDR5.

illustrates a differential DIMMsuch as the one specified and implemented by OpenPower. The differential DIMMincludes a differential DIMM controller ASICthat receives command, address, data, and clock signals from a host CPU via a SerDes interfaceon a host interface connectorto a host computer. The differential DIMM controllerreceives host memory access commands from the SerDes interface and provides memory access to DRAM chips. The differential DIMMmay use differential SerDes to provide increased speed between the CPU and DIMM. A DIMM form factor may include a 25G X8 differential open memory interface (OMI) DDIMM, which may include an 84-pin connector that uses 16 differential pairs for 8×25G SerDes and leaves 20 pins (e.g., 10 differential pairs) for other functions.

illustrate example connectorsfor differential DIMMs and related information. The connectoris based on Storage Networking Industry Association (SNIA) protocols, such the SNIA small form factor (SFF) technology affiliate (TA) 1002 protocol. A SNIA-SFF-TA-1002 tableshows the features of various connector configurations. The connectors may include various connector configurations, such as vertical connectors, right-angle connectors, or edge connectors. A SNIA-SFF-TA-1002 ecosystemshows the relationships between the SFF form factors, differential memory, and the Gen-Z form factors

illustrates an example DIMM evolution. The DIMM progressionincludes a Joint Electron Device Engineering Council (JEDEC) DDR4 DIMM, which provides a 64-bit channel with single-ended parallel signaling, providing throughput of up to 3200 MT/s. The JEDEC DDR4 DIMMis followed by a JEDEC DDR5 DIMM, which provides dual 32-bit channels with single-ended parallel signaling, providing up to 6400 MT/s. The JEDEC DDR5 DIMMmay be followed by a JEDEC-proposed DDR5 DIMM, which provides dual 32-bit channels with differential SerDes signaling, providing greater than 25 gigatransfers per second (GT/s). As used herein, “high-speed differential signaling” is used to refer to signaling providing 25 GT/s or greater