Methods and apparatus to encode and decode video using quantization matrices

This disclosure relates generally to video coding and, more particularly, to methods and apparatus to encode and decode video using quantization matrices.

In recent years, increased demand for media has increased the amount of video files shared over networks. Similarly, as camera and graphics technologies improve, video file sizes have increased. To support and facilitate the transfer of large video files over a network, video coding techniques to reduce the sizes of video files are used throughout industry. A video coding techniques typically includes both an encode and decode procedure. A source machine may execute an encode procedure to compress an input video into a smaller file, which may be shared over a network to a destination machine. The destination machine may execute a decode procedure to reconstruct the input video from the smaller file.

In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not to scale.

Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly that might, for example, otherwise share a same name.

As used herein, “approximately” and “about” refer to dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections. As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+/−1 second.

As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.

As used herein, “processor circuitry” is defined to include (i) one or more special purpose electrical circuits structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmed with instructions to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmed microprocessors, Field Programmable Gate Arrays (FPGAs) that may instantiate instructions, Central Processor Units (CPUs), Graphics Processor Units (GPUs), Digital Signal Processors (DSPs), XPUs, or microcontrollers and integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and/or a combination thereof) and application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of the processing circuitry is/are best suited to execute the computing task(s).

In recent years, many video coding techniques have supported video file transfer with direct cosine transform (DCT) matrices. A DCT matrix divides an input video frame into segments and describes the frequency components of each segment. In examples disclosed herein, frequency may refer to the rate at which pixel values change within the input video frame. In general, the human visual system is more sensitive to low frequencies, where pixel values change relatively slowly, than high frequencies, where pixel values change relatively quickly.

Video coding techniques that utilize a DCT matrix may additionally use a quantization matrix (QM) to leverage the sensitivity of the human visual system. A QM is a matrix of coefficients that describes the relative importance of frequency components within an associated DCT matrix. A video coding technique may specify that a DCT matrix is divided element wise by its associated QM to produce an output matrix. In some examples, an output matrix may be referred to as a transform block. In some examples, producing an output matrix may be referred to as quantizing the transform coefficients of the DCT matrix.

Generally, QMs are designed so that high frequency components in the DCT matrix are reduced or eliminated in the resulting output matrix. By encoding the output matrix rather than the original DCT matrix, video coding techniques can remove data that the human visual system is less perceptive of and reduce file size. In some examples, the amount of data saved in the reduced file size may be referred to as a compression range.

Some prior video coding techniques may support user-defined QMs, which in turn may be used to achieve larger compression ranges than are available using default QMs. However, such prior video coding techniques explicitly encode a QM for each frame, which reduces the flexibility of the video coding technique in some encoding conditions.

Other prior video coding techniques may not explicitly encode a QM for each frame. Rather, such prior video coding techniques may define a number of default QMs and encode a matrix index for each frame, where the matrix index describes which default QM should be used when decoding the frame. Those prior video coding techniques may exhibit increased flexibility in some encoding conditions but do not support user-defined QMs.

Furthermore, some prior video coding techniques assign a single QM to an entire frame. As a result, some segments of the decoded frame may retain a higher quality relative to the original frame than other segments. For example, if a frame consists of sharp texts and a complex background, it may be difficult to use a single QM to avoid text blurring and achieve a high quality background.

Examples disclosed herein may be used to form a video coding technique that supports user-defined QMs, does not explicitly encode a QM for each frame, and supports the use of multiple QMs within a single frame. For example, on the encoding side, example video encoder circuitry, which is disclosed in detail below, includes example QM syntax encoder circuitry, which is disclosed in detail below, to encode a set of user-defined QMs into a sequence header associated with an input video frame. Example adaptive QM selector circuitry, which is disclosed in detail below, selects a subset of QMs used for the input video frame. The subset of QMs come from a larger set of both default QMs and user-defined QMs. Example adaptive segment selector circuitry, which is disclosed in detail below, assigns a QM from the subset for each segment within the input video frame. Example encoder circuitry, which is disclosed in detail below, quantizes the DCT coefficients of each segment using the assigned QMs.

On the decoding side, example video decoder circuitry, which is disclosed in detail below, includes example sequence decoder circuitry, which is disclosed in detail below, to determine syntax information for a sequence within the compressed video. In the beginning of decoding each frame, example frame decoder circuitry, which is disclosed in detail below, derives the QMs for the current frame. Example segment decoder circuitry, which is disclosed in detail below, then assigns one QM to each segment. Example dequantizer circuitry, which is disclosed in detail below, the dequantizes transform blocks within each segment using the assigned QMs.

is an example systemto encode and decode video using quantization matrices. The example systemincludes example input video, example QM trainer circuitry, example user-defined QMs, example video encoder circuitry, example compressed video, example video decoder circuitry, and example recovered video.

The input videoofis a video to be compressed. The input videomay be of any length and describe any content. Furthermore, the input videomay be compressed for any reason. In some examples, the input videois compressed before transmission over a network. The input videoincludes a first frameA and a second frameB. While FIG.illustrates two frames for simplicity, the input videomay include any number of frames.

The QM trainer circuitryofimplements a training algorithm to derive a set of user-defined QMs. The training algorithm may be of any type, including one or more of a rules-based heuristic, Artificial Intelligence, Machine Learning, Deep Learning algorithm, etc. In some examples, the example QM trainer circuitryderives a set of user-defined QMscorresponding to different video characteristics. For example, the training algorithm may derive the set of user-defined QMsto include both a first frame optimized to compress an image with low complexity (such as, for example, a loading screen), and a second frame optimized to compress an image with high complexity (such as, for example, a computer generated action scene).

A user may provide training data and/or other training parameters to specify the contents of the derived user-defined QMs. A QM contains coefficients that describe how various frequency components of frames in the input videoare compressed. A user may specify contents of the user-defined QMsfor any reason. In some examples, the user-defined QMsare used to achieve higher compression range than are possible with default QMs. The user-defined QMsmay include QMs for various conditions within an input video.

In some examples, the QM trainer circuitryimplements the training algorithm to create user-defined QMseach time an instance of input videois to be compressed. However, in some examples, the QM trainer circuitrymay not implement the training algorithm to create user-defined QMseach time an instance of the input videoneeds compression. Instead, in such examples, the example QM trainer circuitrymay implement the training algorithm before any input videoinstance is compressed so that the same set of user-defined QMsis utilized across compressions. In some examples, the example QM trainer circuitrymay rerun the training algorithm to add, remove, or generally edit the user-defined QMs. The example QM trainer circuitrymay edit the user-defined QMsbased on input from a user. Additionally or alternatively, the user may manually edit the user-defined QMs.

The example video encoder circuitryofcompresses the input videoto produce a compressed video. The compressed videodescribes the input videobut has a smaller file size. The example video encoder circuitrysupports user-defined QMs, does not explicitly encode a QM for each frame, and supports the use of multiple QMs within a single frame. An example implementation of the video encoder circuitryis illustrated in, which is described in detail below.

The example video decoder circuitryofdecompresses the compressed videoto produce a recovered video. The recovered videois a replication of the input video. In some examples, data from the recovered videois an exact replica of data from the input videorather than an approximation of data from the input video. In some such examples, the type of compression performed by the example video encoder circuitrymay be referred to as lossless data compression. In other examples, the data from the recovered the videois an approximation of data from the input videorather than an exact replica. In some such examples, the type of compression performed by the example video encoder circuitrymay be referred to as lossy data compression. An example implementation of the video decoder circuitryis illustrated in, which is described in detail below.

The example systemcompresses a video to a smaller size for storage and/or transfer over a network and decompresses the video for use after storage and/or transmission. Because the example video encoder circuitrysupports user-defined QMs, does not explicitly encode a QM for each frame, and supports the use of multiple QMs within a single frame, the example systemcan offer improved granularity, flexibility, and efficiency over prior video coding techniques.

is a block diagram of an example implementation of the video encoder circuitryof. The example video encoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by processor circuitry such as a central processing unit executing instructions. Additionally or alternatively, the example video encoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by an ASIC or an FPGA structured to perform operations corresponding to the instructions. It should be understood that some or all of the circuitry ofmay, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently on hardware and/or in series on hardware. Moreover, in some examples, some or all of the circuitry ofmay be implemented by one or more virtual machines and/or containers executing on the microprocessor.

The example video encoder circuitryincludes example QM syntax encoder circuitry, example picture analyzer circuitry, example adaptive QM selector circuitry, example adaptive segment selector circuitry, and example encoder circuitry. The example QM syntax encoder circuitryofaccepts the user-defined QMsselected by a user and encodes the user-defined QMsinto a sequence header. In some examples, a sequence header is a data structure that contains encoding and display parameters for one or more Groups Of Pictures (GOPs). A GOP is a data structure that contains a collection of sequential pictures within the video. In some examples, a picture may also be referred to as a frameA.

The example picture analyzer circuitryofanalyzes spatial features of a frameA. A spatial feature is data that describes characteristics of various portions of the frameA and/or objects within the frameA. For example, spatial features may identify vectors, lines, polygons, regions, etc. within the frameA. The example picture analyzer circuitrymay use any technique to analyze spatial features. These techniques include but are not limited to one or more of a rules based heuristic, Artificial Intelligence, Machine Learning, Deep Learning algorithm, etc.

The example picture analyzerdetermines bitrate and quality control information for a frameA. The bitrate and quality control information of a given frameA influences how the frameA is compressed to achieve a desired quality. In some examples, the example picture analyzeruses spatial analysis to determine bitrate and quality control information. The example picture analyzer circuitrymay use any technique to determine bitrate and quality control information, including but not limited to the one or more techniques to analyze spatial features of the frameA.

In some examples, the example picture analyzer circuitrydetermines the number and location of segments within the frame. A segment refers to a collection of pixels within the frame. Any collection of pixels within a frame may collectively form a segment. In such examples, the example picture analyzer circuitrydetermines the segments based on spatial analysis. For example, the example picture analyzer circuitrymay determine segments to differentiate between characters within a frame, differentiate a foreground and a background of the frame, etc. In some examples, the example picture analyzer circuitrydetermines the number and/or locations of segments within the frame based on a rule set stored in memory. For example, the rule set may divide a frameA into segments based on a grid pattern, where each grid contains a specified number of pixels. In some examples, the rule set may additionally or alternatively determine the number and location of segments using one or more different techniques.

The example adaptive QM selector circuitryselects a subset of QMs from a set of default QMs and the set of user-defined QMs. The default QMs are QMs that are pre-defined or otherwise initialized within the memory resources of the video encoder circuitryand remain constant between the compression of multiple videos. In some examples, one or more default QMs stored in the example video encoder circuitrymay match one or more default QMs used in a prior video coding technique.

The subset of QMs selected by the example adaptive QM selector circuitryare the QMs used to encode the current frameA. The example adaptive QM selector circuitryuses the spatial analysis of the current frameA provided by the example picture analyzer circuitryto select the subset of QMs. In some examples where the current frameB is not the first frame within the input video, the example adaptive QM selector circuitryadditionally uses feedback from the previously encoded frameA to select the subset of QMs. The feedback provided by the example encoder circuitrymay describe an error rate and/or quality parameter associated with an entropy coding technique. In some examples where user-defined QMs are not provided, the example adaptive QM selector circuitry implicitly selects QMs. Further details concerning implicit selection and the example adaptive QM selector circuitryare provided in the context of, which is described below.

The example adaptive segment selector circuitryassigns a QM from the subset of QMs for each segment within the current frameA. The example adaptive segment selector circuitrymay assign QMs based on the number of QMs within the subset of the QMs and the pixel values of the segments. Further details concerning the example adaptive segment selector circuitryare provided in the context of, which is described below.

The example encoder circuitryofquantizes transform coefficients using the assigned QMs. Each segment within the current frameA has one or more associated DCT matrices which describe the pixel values and frequency components within the segment. To quantize the transform coefficients of an associated DCT matrix, the example encoder circuitrymay perform elementwise division on the DCT matrix with the assigned QM as described previously. The example encoder circuitryencodes the quantized transform coefficients of the segments within the frames of the input videointo the compressed video. In some examples, the example encoder circuitryuses an entropy coding technique to encode the quantized transform coefficients. An entropy coding technique is a form of lossless data compression that is independent of any specific video coding standard. Example entropy coding techniques include but are not limited to Huffman coding, arithmetic coding, Elias gamma coding, Fibonacci coding, etc.

The example video encoder circuitryproduces a compressed videothat has a smaller file size than the input video. In doing so, the example video encoder circuitrysupports user-defined QMs, does not explicitly encode a QM for each frame, and supports the use of multiple QMs within a single frame.

In some examples, the example video encoder circuitryincludes means for accessing an input frame. For example, the means for accessing may be implemented by example QM syntax encoder circuitry. In some examples, the example QM syntax encoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example QM syntax encoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocksof. In some examples, the example QM syntax encoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example QM syntax encoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example QM syntax encoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video encoder circuitryincludes means for encoding a set of user-defined quantization matrices into a sequence header associated with a sequence of video frames including an input frame. For example, the means for encoding may be implemented by example QM syntax encoder circuitry. In some examples, the example QM syntax encoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example QM syntax encoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocks,—of. In some examples, the example QM syntax encoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example QM syntax encoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example QM syntax encoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video encoder circuitryincludes means for analyzing spatial features of an input frame. For example, the means for analyzing may be implemented by picture analyzer circuitry. In some examples, the example picture analyzer circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example picture analyzer circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocksof. In some examples, the example picture analyzer circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example picture analyzer circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example picture analyzer circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video encoder circuitryincludes means for selecting a subset of quantization matrices from a combination of a set of default quantization matrices and a set of user-defined quantization matrices. For example, the means for selecting a subset of quantization matrices may be implemented by example adaptive QM selector circuitry. In some examples, the example adaptive QM selector circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example adaptive QM selector circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocks,-of. In some examples, the example adaptive QM selector circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example adaptive QM selector circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example adaptive QM selector circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video encoder circuitryincludes means for selecting a first one of a subset of quantization matrices for a first segment of an input frame, the input frame to be divided into a plurality of segments including the first segment. For example, the means for selecting a first one of a subset of quantization matrices may be implemented by adaptive segment selector circuitry. In some examples, the example adaptive segment selector circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example adaptive segment selector circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocks-,-of. In some examples, the example adaptive segment selector circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example adaptive segment selector circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example adaptive segment selector circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video encoder circuitryincludes means for quantizing transform coefficients of the first segment of the input frame based on the first one of the subset of quantization matrices. For example, the means for quantizing may be implemented by example encoder circuitry. In some examples, the example encoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example encoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocksof. In some examples, the example encoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example encoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example encoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

is a block diagram of an example implementation of the video decoder circuitryof. The example video encoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by processor circuitry such as a central processing unit executing instructions. Additionally or alternatively, the example video decoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by an ASIC or an FPGA structured to perform operations corresponding to the instructions. It should be understood that some or all of the circuitry ofmay, thus, be instantiated at the same or different times. Some or all of the circuitry may be instantiated, for example, in one or more threads executing concurrently on hardware and/or in series on hardware. Moreover, in some examples, some or all of the circuitry ofmay be implemented by one or more virtual machines and/or containers executing on the microprocessor.

The example video decoder circuitryincludes example sequence decoder circuitry, example frame decoder circuitry, example segment decoder circuitry, and example dequantizer circuitry. The example sequence decoder circuitryofdecodes a sequence header within the compressed video. By decoding the sequence header, the example sequence decoder circuitryobtains QM syntax information. QM syntax information includes but is not limited to whether user-defined QMs were used in the compressed video, the total number of user-defined QMs in the compressed video, QM, and whether implicit QP adaptive QM selection was used in the compressed video. Implicit QP adaptive QM selection is described in further detail below.

The example frame decoder circuitryofderives which QMs were used to compress a given frame. The frame decoder circuitryuses one or more matrix indices encoded within the example compressed video to determine which QMs were used to encode a given frame. The matrix indices point to one or more QMs from a set of both default QMs and user-defined QMs.

The example segment decoder circuitryofassigns QMs used to encode a given frame to segments within the current frame. The example segment decoder circuitryassign one QM to each segment based on sequencing information encoded in a slice header associated with the segment. A slice header is a data structure that describes encoding and display information for a slice. In some examples, a slice is referred to as a segment.

The example dequantizer circuitryofdequantizes transform blocks. A transform block is the output of a quantization process in which the example encoder circuitrydivides a DCT matrix elementwise by a QM of the associated segment (e.g., transform block=DCT matrix/QM). To dequantize a transform block, the example dequantizer circuitrymultiplies the transform block with the assigned QM for the segment, which results in a recovered DCT matrix (e.g., DCT matrix=transform block*QM). The recovered DCT matrices may be used to determine the frequency components of pixel values within the segment. The dequantizer circuitrydequantizes transform blocks of the segments within the current frame, resulting in a recovered frame.

The example video decoder circuitrydecompresses video that has been compressed by the example video encoder circuitry. The example video decoder circuitryproduces recovered frames that collectively compose a recovered video, which is a replication of the input video.

In some examples, the example video decoder circuitryincludes means for determining syntax information for a sequence within compressed video. For example, the means for determining syntax information may be implemented by example sequence decoder circuitry. In some examples, the example sequence decoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example sequence decoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocksof. In some examples, the example sequence decoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example sequence decoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example sequence decoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video decoder circuitryincludes means for deriving quantization matrices used to compress a frame within the sequence, the derived quantization matrices based on the syntax information and a frame header associated with the frame. For example, the means for deriving may be implemented by example frame decoder circuitry. In some examples, the example frame decoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example frame decoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocks,of. In some examples, the example frame decoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example frame decoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example frame decoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video decoder circuitryincludes means for assigning the derived quantization matrices to segments within the frame based on a slice header associated with the segment. For example, the means for assigning may be implemented by example segment decoder circuitry. In some examples, the example segment decoder circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example segment decoder circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocks,of. In some examples, the example segment decoder circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example segment decoder circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example segment decoder circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

In some examples, the example video decoder circuitryincludes means for dequantizing transform blocks within the segments based on the assigned quantization matrices, the dequantized transform blocks to form a recovered frame. For example, the means for dequantizing may be implemented by example dequantizer circuitry. In some examples, the example dequantizer circuitrymay be instantiated by processor circuitry such as the example processor circuitryof. For instance, the example dequantizer circuitrymay be instantiated by the example general purpose processor circuitryofexecuting machine executable instructions such as that implemented by at least blocksof. In some examples, the example dequantizer circuitrymay be instantiated by hardware logic circuitry, which may be implemented by an ASIC or the FPGA circuitryofstructured to perform operations corresponding to the machine readable instructions. Additionally or alternatively, the example dequantizer circuitrymay be instantiated by any other combination of hardware, software, and/or firmware. For example, the example dequantizer circuitrymay be implemented by at least one or more hardware circuits (e.g., processor circuitry, discrete and/or integrated analog and/or digital circuitry, an FPGA, an Application Specific Integrated Circuit (ASIC), a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to execute some or all of the machine readable instructions and/or to perform some or all of the operations corresponding to the machine readable instructions without executing software or firmware, but other structures are likewise appropriate.

illustrates an example output of the example system of.includes a first example imageand a second example image. The first imageofis an example output resulting from encoding an example input image with the example video encoder circuitryand decoding that encoded image with the example video decoder circuitry. For example, the first imagecan correspond to a portion of a video frame that has been compressed using the example video encoder circuitryand decompressed by the example video decoder circuitry. The first imageincludes example textA, an example close buttonB, and an example backgroundC.