Semiconductor device and method of fabricating a semiconductor device

Common transistor devices for power electronic applications include Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). Power transistors devices may be used in circuits for power control. For example, two power transistor devices may be coupled to form a half bridge circuit and driven by gate control circuitry to switch a load current.

WO 01/72092 A1 discloses a multichip module in which various components of a circuit are included within a single package. The circuit includes a first power MOSFET providing the high side switch of a half bridge circuit, a second power MOSFET providing the low side switch of the half bridge circuit and a gate driver for controlling switching of the high side switch and low side switch. The first power MOSFET, second power MOSFET and the gate driver are each provided as separate packaged components that are mounted within the module. It is, however, desirable to reduce the size of circuits for power control.

According to the present disclosure, a semiconductor device is provided which comprises a vertical power FET (Field Effect Transistor), a first lateral FET and a second lateral FET. The vertical power FET (Field Effect Transistor) is configured to switch a load current. The first lateral FET and the second lateral FET provide an output stage of gate driver circuitry that is configured to drive the vertical power FET. The vertical power FET is configured to provide a channel region of a first conductivity type. The first lateral FET is configured to provide a channel region of the first conductivity type and the second lateral FET is configured to provide a channel region of a second conductivity type, that opposes the first conductivity type. The vertical power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the vertical power FET.

According to the present disclosure, a semiconductor device is provided which comprises a vertical power FET (Field Effect Transistor), a first lateral FET and a second lateral FET. The vertical power FET comprises a channel region of a first conductivity type. The first lateral FET comprises a channel region of the first conductivity type and the second lateral FET comprises a channel region of a second conductivity type, that opposes the first conductivity type. The vertical power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the vertical power FET.

The first conductivity type may be n-type and the second conductivity type p-type, or vice versa. For example, the first lateral FET may be a n-channel device and the second lateral FET be a p-channel device.

The vertical power FET has a vertical drift path that extends substantially perpendicularly to the first surface of the semiconductor substrate. In contrast, the lateral FETs have a drift path that extends substantially parallel to the first surface of the semiconductor substrate.

The vertical power FET may be a vertical MOSFET or MISFET with a charge compensation structure. The lateral FETs may be a lateral MOSFET or a lateral MISFET, for example a shallow trench recessed channel CMOS device or LDMOS device.

The first and second lateral FETs provide an output stage of the gate driver circuitry since the drain of the first lateral FET and the source of the second lateral FET are electrically coupled to the gate of the vertical power FET. The two lateral FETs are monolithically integrated in the semiconductor substrate along with the power vertical power FET which they are to control. This arrangement enables the physical size of the circuit to be reduced and the length of the electrical connections between the lateral FETs and the vertical power FET to be reduced, thus reducing losses and improve efficiency. The semiconductor device may also be useful for high current, e.g. 90A applications.

In some embodiments, a well of the second conductivity type is arranged in a first surface of the semiconductor substrate. The well is a portion of the semiconductor substrate that has dopants of the second conductivity type and that has a base and side walls which form a pn junction with the semiconductor substrate that includes dopants of the first conductivity type. The first lateral FET is formed in the well and comprises a gate electrode that is arranged in a first gate trench formed in the first surface. The gate electrode is electrically insulated from the well by a first insulating layer. The first insulating layer may line sidewalls and base of the first gate trench. The first gate trench may be referred to as a shallow trench. The first lateral FET also comprises a source region of the first conductivity type and a drain region of the first conductivity type that are arranged on opposing sides of the gate electrode and are arranged in the well. The source region and the drain region are, therefore, arranged on opposing sides of the first gate trench.

In some embodiments, opposing sidewalls of the first gate trench are formed by the source region and drain region, respectively.

In some embodiments, the first lateral FET further comprises a lightly doped drift region of the first conductivity type, the lightly doped drift region extending from the drain region under the first gate trench. In some embodiments, the lightly doped drift region further extends from the source region under the first gate trench. In some embodiments, the lightly doped drift region extends substantially horizontally and a more highly doped drain region and a more highly doped source region extend from the first surface into the well and have a depth from the first surface which is about the same as or at least the depth of the base of the first trench from the first surface. The lightly doped drift region can be considered to have two portions which extend towards one another, one from the drain region, the other from the source region, whereby the two portions are spaced apart from one another by a portion of the well.

In some embodiments, the lightly doped drift region for the drain region extends from the first surface of the substrate and adjoins the drain region and then extends under the drain region and the drain sided peripheral edge of the first gate trench.

In some embodiments, the lightly doped drift region is more lightly doped that the drain region. In some embodiments, the doping level of the drift region may be similar or the same as the drain region.

In some embodiments the first insulating layer, which lines the first gate trench and electrically insulates the gate electrode from the well, has a thickness on the base of the first gate trench that provides the gate insulation layer for the gate electrode. The first insulating layer has a thickness between the sidewall of the first gate trench on the drain side that is greater than its thickness on the base. In some embodiments, the sidewall of the first gate trench is formed by the drain region. The electrically insulating layer arranged between the first gate electrode and the drain-sided side wall provides a spacer and the thickness or width of this region of the electrically insulating layer may be adjusted to define the length of the drift region of the first lateral FET. The electrically insulating layer that is arranged between the first gate electrode and the drain-sided side wall and provides the spacer may also have two or more sublayers that may have differing compositions.

In some embodiments, the second lateral FET is formed in the semiconductor substrate and comprises a gate electrode arranged in a second gate trench that is formed in the first surface of the semiconductor substrate. The second gate trench may be referred to as a shallow trench. The second gate electrode is electrically insulated from the semiconductor substrate by a second insulating layer. The second insulating layer may line the sidewalls and base of the second gate trench. The second lateral FET further comprises a source region of the second conductivity type and a drain region of the second conductivity type that are arranged on opposing sides of the gate electrode. The source region and the drain region are positioned on opposing sides of the second gate trench and in the semiconductor substrate.

In some embodiments, opposing sidewalls of the second gate trench of formed by the source region and drain region, respectively.

In some embodiments, the second lateral FET further comprises a lightly doped drift region of the second conductivity type. The lightly doped drift region of the second lateral FET may extend from the drain region under the second trench. In some embodiments, the lightly doped drift region of the second conductivity type further extends from the source region under the second trench. The lightly doped drift region can be considered to have to portions which extend towards one another, one from the drain region and the other from the source region, whereby the two portions are spaced apart from one another by a portion of the semiconductor substrate.

In some embodiments, the lightly doped drift region for the drain region extends from the first surface of the substrate and adjoins the drain region and then extends under the drain region and the drain sided peripheral edge of the second gate trench.

In some embodiments, the lightly doped drift region is more lightly doped that the drain region. In some embodiments, the doping level of the drift region may be similar or the same as the drain region.

In some embodiments, the second insulating layer has a thickness on the base of the second trench that provides the gate insulation layer for the gate electrode. The second insulating layer has a thickness between the sidewall of the second trench on the drain side of the second trench that is greater than the thickness of the second insulating layer on the base.

The electrically insulating layer arranged between the second gate electrode and the drain-sided side wall provides a spacer and the thickness or width of this region of the electrically insulating layer may be adjusted to define the length of the drift region of the second lateral FET. The electrically insulating layer that is arranged between the second gate electrode and the drain-sided side wall and provides the spacer may also have two or more sublayers that may have differing compositions.

In some embodiments, the first gate trench of the first lateral FET has a base and sidewalls, whereby the sidewalls extend substantially perpendicular to the first surface. In other embodiments, the side walls extend at an inclined angle to the first surface to form a tapered trench, in which the base of the trench has a smaller area than the open end of the trench at the first surface. In some embodiments, an edge formed between the base and the sidewalls of the trench is rounded. The sidewalls may be inclined to the first surface or substantially perpendicular to the first surface.

In some embodiments, the second gate trench of the second lateral FET has a base and sidewalls, whereby the sidewalls extend substantially perpendicular to the first surface. In other embodiments, the sidewalls extend as an inclined angle to the first surface to form a tapered trench, in which the base of the trench has a smaller area than the open end of the trench at the first surface. In some embodiments, and edge formed between the base and the sidewalls of the trench is rounded. The sidewalls may be inclined to the first surface or substantially perpendicular to the first surface.

In some embodiments, the vertical power FET comprises a plurality of third trenches extending into the semiconductor substrate from the first surface. The distance of the base of the third trenches of the vertical power FET from the first surface is greater than the distance of the base of the first and second gate trenches of the first and second lateral FETS. Mesas are formed between the third trenches. The semiconductor substrate provides the drift region of the vertical FET. Each third trench comprises a field plate that is electrically insulated from the semiconductor substrate. The vertical power FET further comprises a drain region arranged at a second surface of the semiconductor substrate that opposes the first surface, a body region of the second conductivity type that is arranged on the drift region and a source region of the first conductivity type that is arranged on the body region. The mesas include the drift region, body region and source region.

In some embodiments, each of the plurality of third trenches further comprises a gate electrode that is arranged above and that is electrically insulated from the field plate positioned in that trench. In some embodiments, the vertical power FET has a different arrangement of the gate electrode and further comprises a plurality of gate trenches, each comprising a gate electrode. One gate trench is arranged between adjacent ones of the plurality of third trenches which include only a field plate. The gate trenches are arranged in the mesas and have a depth that is less than the depth of the third trenches with the field plates.

In some embodiments, the third trenches are columnar or needle shape. In these embodiments the individual field plates also have a columnar or needle shape. The columnar trenches and, therefore, the field plates, may be arranged in a regular array, for example of rows and columns or in staggered rows. In some embodiments, the third trenches are columnar and the gate trenches are elongate and strip-like. In some embodiments, the third trenches are elongate and have a stripe-like structure. The filed plates and the gate electrodes also have an elongate strip-like structure.

According to the present disclosure, a method for forming a vertical power FET for switching a load current, a first lateral FET and a second lateral FET in a common semiconductor substrate is provided. The method comprises providing a semiconductor substrate of the first conductivity type. The semiconductor substrate comprises a first surface, a plurality of trenches for a vertical power FET formed in the first surface, each trench comprising a field plate that is electrically insulated from the semiconductor substrate. The semiconductor substrate further comprises a first predefined area region for a first lateral FET having a channel region of the first conductivity type and a second predefined region for lateral second lateral FET having a channel region of the second conductivity type that opposes the first conductivity type.

The method comprises forming a well of the second conductivity type in the first surface of the semiconductor substrate in the first predefined region. A well of the second conductivity type is not formed in the second predefined region or in the third predefined region of the semiconductor substrate comprising the trenches for the vertical power FET.

The method continues by forming a first gate trench in the first surface of the semiconductor substrate for a first gate electrode in the first predetermined region and a second gate trench in the first surface of the semiconductor substrate for a second gate electrode in the second predefined region. The first gate trench and second gate trench may be formed in the first and second predefined regions, respectively, using the same process steps. A gate insulating layer is formed which covers the sidewalls and base of the first and second gate trenches, the first surface of the semiconductor substrate and the upper portion of the plurality of trenches for the vertical power FET. Conductive material is inserted into the first and second gate trenches and also into the plurality of trenches for the vertical power FET and a third gate electrode is formed in each of the plurality of trenches.

Conductive material is removed from the first and second gate trenches in regions adjacent the sidewalls and also from peripheral regions of the base of each of the first and second gate trenches. The gate insulating layer positioned on the sidewalls and in peripheral regions of the base is exposed. The remaining portion of the conductive material in the first gate trench forms the first gate electrode having a predetermined length. Similarly, a second gate electrode having a predetermined length is formed from the conductive material remaining and the second gate trench. In the second predefined area, dopants of the second conductivity type are implanted into the sidewalls and peripheral regions of the base of the second gate trench. In the first predefined area, dopants of the first conductivity type are implanted into the sidewalls and into peripheral regions of the base of the first gate trench. Insulating material is then formed in the first and second gate trenches and may fill the first and second gate trenches covering the first and second gate electrodes and is also formed on the third gate electrodes arranged in the plurality of trenches.

In this method, the same process steps may be used to form the gate electrode of the vertical power FET as well as for the two lateral FETs and also the insulating material in the respective gate trenches of the vertical power FET as well as for the two lateral FETs.

In some embodiments, the method further comprises implanting dopants of the second conductivity type into the first surface of the semiconductor substrate to form a body region of the power FET, implanting dopants of the first conductivity type into the first surface of the semiconductor substrate and into the well of the second conductivity type in the first predefined region to form source and drain regions of the first lateral FET and a source region on the body region for the vertical power FET and implanting dopants of the second conductivity type into the first surface of the semiconductor substrate in the second predefined region to form source and drain regions of the second lateral FET.

In some embodiments, a third insulating layer is formed on the first surface and openings are formed in the third insulating layer which expose the underlying structure to which a contact is to be made by inserting conductive material into the opening.

An opening to the first gate electrode is formed in the first gate trench, an opening is formed to the source region and an opening is formed to drain region of the first lateral FET. An opening is formed to the second gate electrode in the second gate trench, an opening is formed to the source region and an opening is formed to drain region of the second lateral FET. An opening is also formed to the third gate electrodes in the plurality of trenches and an opening is formed to the source region of the vertical power FET. Conductive material is inserted into these openings to form the contact to the underlying structure and a planarising process carried out, for example by chemical mechanical polishing, to form a planarized surface comprising contacts formed of the conductive material arranged in the openings and the third insulating layer. A metallization structure may be formed on the planarized surface.

The metallization structure may include a plurality of electrically insulating and electrically conductive layers. The metallization structure can be patterned so as to provide electrical connections between the drain contacts of the first and second lateral FETS and the gate of the vertical power FET.

Typically, the first and second lateral FET each comprise a plurality of transistor cells, each including a source region, a drain region and a gate trench with the gate electrode and each having substantially the same structure. Each of the source region, drain region, gate trench and gate electrode may have an elongate stripe-like form and extend substantially parallel to one another, whereby the source and drain region can be common to two adjoining cells so that an order of source region, gate electrode, drain region, gate electrode source region and so on is formed. The first lateral FET according to any one of the embodiments described herein may also represent one of the transistor cells of the plurality of transistor cells of the first lateral FET. Similarly, the second lateral FET according to any one of the embodiments described herein may also represent one of the transistor cells of a plurality of the transistor cells of the second lateral FET.

The vertical power FET typically also comprises a plurality of transistor cells, each including a mesa with a source region, body region, drift region and a drain region and a third trench with a field plate and a gate electrode and each having substantially the same structure.

The metallization structure may also provide busses for electrically connecting transistor cells of the first and second lateral FETS and of the vertical power FET. For example, a first source bus electrically connects the source regions of the first lateral FET, a first drain bus electrically connects the drain regions of the first lateral FET and a first gate bus electrically connects the first gate electrodes of the first lateral FET to one another. A second source bus electrically connects the source regions of the second lateral FET, a second drain bus electrically connects the drain regions of the second lateral FET and a second gate bus electrically connects the gate electrodes of the second lateral FET to one another. A third source bus electrically connects the source regions and field plates of the vertical power FET and a third gate bus electrically connects the gate electrodes of the vertical power FET to one another. The vertical power FET includes a single drain region arranged at the second surface of the semiconductor substrate which provides a common drain region for all of the transistor cells. A drain pad may be directly arranged on the drain region at the second surface.

In some embodiments, the removing the conductive material from the first and second gate trenches comprises applying a mask onto the first surface that covers the third gate electrodes in the plurality of trenches and that covers designated source and drain regions on opposing sides of the first and second gate trenches and a designated gate electrode region of the conductive material in the first and second gate trenches. The regions of the conductive material exposed by the mask are removed from the first and second gate trenches, for example by etching such as wet chemical etching.

In some embodiments, the etching process is carried out such that the first gate electrode has inclined side walls, wherein a base of the first gate electrode that is formed on the gate insulating layer has a larger area than a top of the first gate electrode and the second gate electrode has inclined side walls, wherein a base of the second gate electrode that is formed on the gate insulating layer has a larger area than a top of the second gate electrode.

After removal of the conductive material and forming the first and second gate electrodes, the first and second gate trenches may be filled with insulating material which may also cover the first and second gate electrodes.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the figure(s) being described. Because components of the embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, thereof, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference symbols in the figures. In the context of the present description, “lateral” or “lateral direction” should be understood to mean a direction or extent that runs generally parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction thus extends generally parallel to these surfaces or sides. In contrast thereto, the term “vertical” or “vertical direction” is understood to mean a direction that runs generally perpendicular to these surfaces or sides and thus to the lateral direction. The vertical direction therefore runs in the thickness direction of the semiconductor material or semiconductor carrier.

As employed in this specification, when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present.

As employed in this specification, when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

As used herein, various device types and/or doped semiconductor regions may be identified as being of n type or p type, but this is merely for convenience of description and not intended to be limiting, and such identification may be replaced by the more general description of being of a “first conductivity type” or a “second, opposite conductivity type” where the first type may be either n or p type and the second type then is either p or n type.

The figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n” means a doping concentration which is lower than the doping concentration of an “n”-doping region while an “n”-doping region has a higher doping concentration than an “n”-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”-doping regions may have the same or different absolute doping concentrations.

According to the present disclosure, a semiconductor device is provided that includes a vertical power FET and two lateral FETs monolithically integrated into a semiconductor substrate. The lateral FETs are electrically coupled to the vertical power FET so that the lateral FETs can form part of a gate driver circuit for driving the vertical power FET. The lateral FETs may provide part of the output stage of the gate driver circuit.

The semiconductor device may be used in DCDC applications, where integrating driver devices in a power MOSFET can result in better performance and higher frequency. Bringing drivers into the die of the power switch can add on efficiency gains from power MOSFET Figure-of-Merit (FOM) improvement. The semiconductor device may be used to provide a high side switch or a low side switch of a half-bridge of full-bridge circuit which has an integrated output stage of a gate driver circuit provided by the two lateral FETs.