Layout structure, semiconductor structure and memory

This is a continuation of International Patent Application No. PCT/CN2022/126213 filed on Oct. 19, 2022, which claims priority to Chinese Patent Application No. 202211073818.7 filed on Sep. 2, 2022. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety.

Standard cell is the basis of integrated circuit design, which may include logic devices commonly used in integrated circuits, such as an inverter, a logic gate circuit, a register, a buffer. When designing an integrated circuit, a standard cell layout in a standard cell library may be called to complete the layout design of the integrated circuit according to the design requirements, which can improve the design efficiency of the circuit. With the high integration and high performance of the semiconductor devices, it is a feasible way to optimize the standard cells, so as to improve the design efficiency as well as the integration and performance of the semiconductor devices.

The disclosure relates to the technical field of semiconductors, in particular to a layout structure, a semiconductor structure and a memory.

According to a first aspect of the disclosure, a semiconductor structure is provided. The semiconductor structure includes a logic device and a switch driving device.

The logic device includes a first power line and a second power line. The first power line and the second power line are located on a same wiring layer, each of the first power line and the second power line extends along a first direction, and the first power line and the second power line are arranged in parallel along a second direction. The first direction and the second direction intersect with each other and are both parallel to a plane where the wiring layer is located.

The switch driving device and the logic device are arranged in parallel along the first direction. The switch driving device includes a first input line and a first output line. The first input line, the first output line and the first power line are located on the same wiring layer, each of the first input line and the first output line extends along the first direction, and the first input line and the first output line are arranged in parallel along the second direction. The first output line is connected with the first power line or the second power line.

According to a second aspect of the disclosure, a memory is provided. The memory includes the semiconductor structure. The semiconductor structure includes a logic device and a switch driving device.

The logic device includes a first power line and a second power line. The first power line and the second power line are located on a same wiring layer, each of the first power line and the second power line extends along a first direction, and the first power line and the second power line are arranged in parallel along a second direction. The first direction and the second direction intersect with each other and are both parallel to a plane where the wiring layer is located.

The switch driving device and the logic device are arranged in parallel along the first direction. The switch driving device includes a first input line and a first output line. The first input line, the first output line and the first power line are located on the same wiring layer, each of the first input line and the first output line extends along the first direction, and the first input line and the first output line are arranged in parallel along the second direction. The first output line is connected with the first power line or the second power line.

According to a third aspect of the disclosure, a layout structure is provided. The layout structure includes a logic device layout and a switch driving device layout.

The logic device layout includes a first power line pattern and a second power line pattern. The first power line pattern and the second power line pattern are located on a same layout wiring layer. Each of the first power line pattern and the second power line pattern extends along a first direction, and the first power line pattern and the second power line pattern are arranged in parallel along a second direction. The first direction intersects with the second direction. The logic device layout is configured to define a logic device, the first power line pattern is configured to define a first power line, and the second power line pattern is configured to define a second power line.

The switch driving device layout and the logic device layout are arranged in parallel along the first direction. The switch driving device layout includes a first input line pattern and a first output line pattern. The first input line pattern, the first output line pattern and the first power line pattern are located on the same layout wiring layer. Each of the first input line pattern and the first output line pattern extends along the first direction, and the first input line pattern and the first output line pattern are arranged in parallel along the second direction. The first output line pattern extends along the first direction and is connected with the first power line pattern or the second power line pattern. The switch driving device layout is configured to define a switch driving device, the first input line pattern is configured to define a first input line, and the first output line pattern is configured to define a first output line.

The technical solution in the disclosure is described in detail below with reference to the accompanying drawings and specific embodiments in the specification.

In the description of the disclosure, it should be understood that terms “length”, “width”, “depth”, “upper”, “lower”, “outer” and the like that indicate an orientation or positional relationship are based on the orientation or a positional relationship shown in the drawings, which are merely intended to facilitate the description of the disclosure and to simplify the description, rather than to indicate or imply that the referred device or element is limited to the specific orientation or to be operated or configured in the specific orientation. Therefore, the above-mentioned terms shall not be interpreted as confine to the disclosure.

is a schematic diagram of a layout of a semiconductor structure according to an embodiment of the disclosure. The semiconductor structure includes a standard cell array. The standard cell arrayincludes a plurality of standard cells. For example, as shown in, the standard cell array includes 4×12 standard cells.

The standard cell may include different types of logic devices. The logic device may be a buffer (abbreviated as buf), a register, an inverter (abbreviated as inv), a logic gate circuit and the like. The logic gate circuit includes, but is not limited to a NOR gate circuit (nor), a NAND gate circuit (nand) and the like. It should be noted that there are expressions, such as nand3PF×2, shown in the figures, which will be defined uniformly herein, in which “nand” represents any logic gate circuit; “3” represents the number of the input terminals of the logic gate circuit; “PF” represents that the power supply terminal is not limited, and the grounding terminal is defined as the main grounding terminal Vss; “GF” represents that the grounding terminal is not limited, and the power supply terminal is defined as the main power supply terminal Vcc; and “×2” represents the width-to-length ratio of the MOS transistor in the logic gate circuit.

The semiconductor structure further includes two switch driving device arrays. The two switch driving device arraysare respectively arranged on either side of the standard cell arrayalong a Y direction. The switch driving device arrayincludes a plurality of switch driving devices (Switch CMOS Driver Cell, abbreviated as Scmos Dry cell). For example, as shown in, the switch driving device array may include 10×1 switch driving devices, in which “10” represents the number of the switch driving devices, and “×1” represents the width-to-length ratio of the MOS transistor in the switch driving device.

The semiconductor structure further includes a plurality of local power buses, each local power busextending along the Y direction. The local power buselectrically connects the switch driving device with the logic device. The switch driving device is configured to control the turning on and turning off of the power supply of the logic device (i.e., the standard cell array). For example, the switch driving device includes a PMOS transistor (P-channel enhancement mode field effect transistor), an NMOS transistor (N-channel enhancement mode field effect transistor), or a CMOS circuit composed of a PMOS transistor and an NMOS transistor.

There are two connection modes of the switch driving device with the logic device. One is to turn off the logic device by turning off the power signal of the logic device, and the other is to turn off the logic device by turning off the grounding signal of the logic device.

andshow two connection modes of the switch driving device with the logic device. As shown in, the switch driving device is a PMOS transistor MPa. The drain of the PMOS transistor MPa is connected to the power supply Vcc, the source of the PMOS transistor MPa is connected to the power supply terminal of the logic device, and the grounding terminal of the logic device is connected to the common grounding Vss. When the PMOS transistor MPa is turned on, the switch driving device supplies power to the logic device. For example, the power supply provided by the switch driving device is referred to as the local power supply (Local Vcc). When the PMOS transistor MPa is turned off, the power supply of the logic device can be turned off.

As shown in, the switch driving device is an NMOS transistor MNa. The drain of the NMOS transistor MNa is connected to the common grounding Vss, the source of the NMOS transistor MNa is connected to the grounding terminal of the logic device, and the power supply terminal of the logic device is connected to the power supply Vcc. When the NMOS transistor MNa is turned on, the switch driving device is configured to provide a grounding signal to the logic device. For example, the grounding signal provided by the switch driving device is referred to as the local grounding signal (Local Vss). When the NMOS transistor MNa is turned off, the power supply of the logic device can be turned off.

Combined with the above analysis, it should be noted that there are three modes to provide power to the logic devices. The first mode is that the power supply terminal is connected to the power supply Vcc, and the grounding terminal is connected to the common grounding Vss. The second mode is that the power supply terminal is connected to the switch driving device to receive the local power supply (Local Vcc), and the grounding terminal is connected to the common grounding Vss. The third mode is that the power supply terminal is connected to the power supply Vcc, and the grounding terminal is connected to the switch driving device to receive the local grounding signal (Local Vss).

is an enlarged schematic diagram of the logic device and the switch driving device in the semiconductor structure shown in, that is, an enlarged schematic diagram showing an area indicated by the dashed line box in. Herein, the logic deviceis the invPF×4. In this embodiment, the layout and connection mode of the logic deviceand the switch driving deviceare explained by taking the logic device being the invPF×4 as an example.

is a circuit diagram of the logic device and the switch driving device shown in. As shown in, the switch driving deviceincludes a plurality of PMOS transistors MPa which are connected in parallel with each other. For example, in this embodiment, the switch driving deviceincludes five PMOS transistors MPa which are connected in parallel with each other. Thus, the switch driving device arrayinprovides the local power supply (Local Vcc) to the standard cell arraythrough a plurality of local power buses. It should be understood that in some other embodiments, the switch driving device array may also provide the local grounding signal (Local Vss) to the standard cell array through a plurality of local power buses.

With reference to, the logic deviceincludes a first load transistor MP, a first driving transistor MN, a second load transistor MPand a second driving transistor MN. The first load transistor MPand the second load transistor MPare PMOS transistors, and the first driving transistor MNand the second driving transistor MNare NMOS transistors.

The source of the first load transistor MPis connected to the output terminal of the switch driving device, for receiving the local power supply (Local Vcc), the drain of the first load transistor MPand the drain of the first driving transistor MNare both connected to the node b, the source of the first driving transistor MNis connected to the common grounding Vss, and the gate of the first load transistor MPand the gate of the first driving transistor MNare both connected to the node a. The source of the second load transistor MPis also connected to the output terminal of the switch driving device, for receiving the local power supply (Local Vcc), the drain of the second load transistor MPand the drain of the second driving transistor MNare both connected to the node b, the source of the second driving transistor MNis connected to the common grounding Vss, and the gate of the second load transistor MPand the gate of the second driving transistor MNare both connected to the node a. The node ais connected with the node a, and the node bis connected with the node b.

The logic deviceincludes two inverters connected in parallel with each other. The first load transistor MPand the first driving transistor MNconstitute a first inverter, the node ais an input terminal of the first inverter, and the node bis an output terminal of the first inverter. The second load transistor MPand the second driving transistor MNconstitute a second inverter, the node ais an input terminal of the second inverter, and the node bis an output terminal of the second inverter. The node ais connected to the node a, and the node bis connected to the node b, that is, the input terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the first inverter is connected to the output terminal of the second inverter, and the first inverter and the second inverter are connected in parallel with each other.

is an enlarged schematic diagram of the logic device in.is a cross-sectional diagram of the logic device taken along a line A-A in. With reference toto, an n-type well region and a p-type well region are formed in a substrate. The first load transistor MPand the second load transistor MPare formed in the n-type well region, the first load transistor MPand the second load transistor MPare arranged in parallel along the X direction. The first driving transistor MNand the second driving transistor MNare formed in the p-type well region, the first driving transistor MNand the second driving transistor MNare arranged in parallel along the X direction. The first load transistor MPand the first driving transistor MNare arranged in parallel along the Y direction, and the second load transistor MPand the second driving transistor MNare arranged in parallel along the Y direction.

As shown in, each of the first load transistor MPand the second load transistor MPincludes a source regionand a drain regionwhich are located in the n-type well region. Each of the source regionand the drain regionis a p-type doped region. The source regionand the drain regionare arrayed along the X direction and isolated from each other, and a channel is formed between the source regionand the drain region. In this embodiment, the first load transistor and the second load transistor share the drain region.

Each of the two load transistors (i.e., the first load transistor MPand the second load transistor MP) also includes a gate structure covering the channel. The gate structure includes a gateextending in the Y direction and a gate dielectric layer located between the gateand the channel. The gatesof the two load transistors are arranged in parallel along the X direction and are electrically connected with each other through a sub-connecting lineextending in the X direction. The sub-connecting lineand the gateare located on the same wiring layer.

Similarly, each of the first driving transistor MNand the second driving transistor MNincludes a source region (not shown in the figure), a channel and a drain region (not shown in the figure) which are located in the p-type well region, as well as a gate structure covering the channel. The source region, the channel and the drain region are arranged in parallel along the X direction. Each of the source region and the drain region is an n-type doped region. The first driving transistor MNand the second driving transistor MNshare a drain region. As shown in, the gate structure includes a gateextending in the Y direction and a gate dielectric layer located between the gateand the channel. The gatesof the two driving transistors (i.e., the first driving transistor MNand the second driving transistor MN) are arranged in parallel along the X direction and are electrically connected with each other through a sub-connecting lineextending in the X direction. The sub-connecting lineand the gateare located on the same wiring layer.

Herein, the gatesof the two load transistors and the gatesof the two driving transistors are located on the same wiring layer, but are isolated from each other, that is, the gatesand the gatesare not electrically connected with each other on this wiring layer.

With reference toand, the logic devicefurther includes source linesand drain lineof the two load transistors. Each of the source linesand the drain lineof the two load transistors extends in the Y direction, each source lineis electrically connected to its source region through the contact plug CT, and each drain lineis electrically connected to its drain region through the contact plug CT. Herein, the source linesand the drain lineof the two load transistors are defined to be located on a first wiring layer M. The first wiring layer Mis located above the wiring layer where the gate is located. The contact plug CT is located between the first wiring layer Mand the substrate, or the contact plug CT is located between the first wiring layer Mand the source region.

For example, the source lineof each load transistor may be electrically connected to its source regionthrough a respective contact plug CT, and the drain lineof each load transistor may be electrically connected to its drain regionthrough a respective contact plug CT.

Similarly, the logic device further includes source linesand drain lineof the two driving transistors. Each of the source linesand the drain lineof the two driving transistors extends in the Y direction. Each source lineis electrically connected to its source region through the contact plug CT, and each drain lineis electrically connected to its drain region through the contact plug CT. Herein, the source linesand the drain lineof the two driving transistors are located on the first wiring layer M.

Herein, in the first wiring layer M, the drain lineshared by two load transistors is connected to the drain lineshared by two driving transistors. In other words, the drain lineand the drain lineconstitute a single conductive line. The drain lineis connected to the drain line, and the node band the node bin the corresponding circuit are connected to each other.

The first wiring layer Mfurther includes a main connecting lineextending in the Y direction. The main connecting lineis electrically connected to the sub-connecting lineand the sub-connecting linethrough the contact plug CT, and the node aand the node ain the corresponding circuit are connected to each other.

With reference toand, the logic device further includes a first local lineand second main line. Herein, the first local lineis configured to provide the local power supply (Local Vcc) to the logic device, and the second main lineis configured to provide the common grounding signal Vss to the logic device. The first local lineand the second main lineboth extend in the X direction and are arranged in parallel along the Y direction. The first local lineis electrically connected to the source linesof the two load transistors through an interconnection via V, and the second main lineis electrically connected to the source linesof the two driving transistors through the interconnection via V. Herein, the first local lineand the second main lineare located on a second wiring layer M. The second wiring layer Mis located above the first wiring layer M. The interconnection via Vis located between the second wiring layer Mand the first wiring layer M.

For example, the first local lineis electrically connected to the source linesof the two load transistors through a plurality of interconnection vias V, and the second main lineis electrically connected to the source linesof the two driving transistors through a plurality of interconnection vias V.

With reference toand, the local power busis located on a third wiring layer M. The third wiring layer Mis located above the second wiring layer M. The local power busis electrically connected to the first local lineof the logic device through an interconnection via V. The interconnection via Vis located between the third wiring layer Mand the second wiring layer M.

The logic device further includes an interconnection via Vand an interconnection via V. The interconnection via Vis located on the drain lineand/or the drain line, for serving as the output terminal of the logic device, and the interconnection via Vis located on the main connecting line, for serving as the input terminal of the logic device.

With reference to, the switch driving deviceincludes a plurality of PMOS transistors MPa connected in parallel with each other. The structure and layout of the PMOS transistor MPa are substantially the same as the structure and layout of the first load transistor MPand the second load transistor MPin the logic device. The PMOS transistor MPa includes: the first source region, the first channel, and the first drain region (not shown in the figure) which are located in the first well region of the substrate, as well as the first gate, the first source line, the first drain line, the first input line, and the first output line. The first well region is an n-type well region. The first source region, the first channel and the first drain region are arranged in parallel along the X direction. The first source region and the first drain region are p-type doped regions.

The first gatecovers the first channel and extends in the Y direction. The first source lineand the first drain lineare located on the first wiring layer M, and the first source lineand the first drain lineextend along the Y direction and are arranged in parallel along the X direction. The first source lineis electrically connected to the first source region through the contact plug CT, and the first drain lineis electrically connected to the first drain region through the contact plug CT.

The first input lineand the first output lineare located on the second wiring layer M. The first input lineand the first output lineextend along the X direction and are arranged in parallel along the Y direction. The first input lineis electrically connected to the first source linethrough the interconnection via V, and the first output lineis electrically connected to the first drain linethrough the interconnection via V.

The local power busis electrically connected to the first output linethrough the interconnection via V, such that the switch driving device provides the local power supply (Local Vcc) to the first local lineof the logic device.

When the semiconductor structure shown inis applied to the circuit of Low Power Double Data Rate SDRAM (LPDDR), part of the logic devices (for example, the invPF×4, nor3PF×2, nand3PF×2, nor2PF×2, nand2PF×2 included in the solid line box in) may be composed of multiple high-speed transistors (abbreviated as Lvt transistor, Low V). The high-speed transistor has a low threshold voltage (V), a short delay time and a fast opening speed. However, the transistor noise of the high-speed transistor is easily superimposed, which leads to a poor stability of the delay time of the high-speed transistor. One feasible method is to improve the power supply stability of the high-speed transistors, that is, to improve the stability of the local power supply.

In some embodiments, the resistance value of the local power supply network may be reduced by increasing the number of the local power buses, or by increasing the line width of the local power bus, thereby improving the stability of the local power supply.

However, the above method has two disadvantages. The first disadvantage is that when the requirements for local power supply are extremely strict (such as double-edge handshake signal), even if the power is supplied to the standard cell array through all the local power buses, the resistance value of the local power supply network cannot be guaranteed to meet the requirements. The reason is that when the switch driving device provides the local power supply to the logic device, the flow path of the current is: the first drain lineof the switch driving device→the interconnection via V→the first output lineof the switch driving device→the interconnection via V→the local power bus→the interconnection via V→the first local lineof the logic device→the interconnection via V→the source lineof the logic device, that is, current sequentially flows through: M→V→M→V→M→M→V→M. Each of the interconnection via Vand the interconnection via Vis passed through twice in the transmission process. Due to the large resistance value of the interconnection via, the resistance value of the local power supply network is relatively large, the loss in the transmission process is relatively large, and the stability of the local signal is relatively poor.

The second disadvantage is that, even if the resistance value of the power supply network is reduced to the desired value by increasing the number of the local power busesand increasing the line width of the local power bus, a large number of tracks of the third wiring layer Mare occupied, resulting in insufficient tracks for subsequent layout arrangement.

In view of this, an embodiment of the disclosure provides a semiconductor structure.is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure.is an enlarged schematic diagram of a standard cell in the semiconductor structure shown in. With reference toand, the semiconductor structure includes a new standard cell array′ including a plurality of standard cells. At least some of the standard cells include a logic deviceand a switch driving device. In other words, in the embodiment of the disclosure, the switch driving deviceand the logic deviceare disposed in one standard cell, so as to form a logic device standard cell provided with a switch driving device.