Bank configurable power modes

The present Application for Patent is a continuation of U.S. patent application Ser. No. 16/551,581 by Mirichigni et al., entitled “BANK CONFIGURABLE POWER MODES,” filed Aug. 26, 2019, which is assigned to the assignee hereof and is expressly incorporated by reference herein.

The following relates generally to a system that includes at least one memory device and more specifically to bank-configurable power modes.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices most often store one of two states, often denoted by a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read, or sense, at least one stored state in the memory device. To store information, a component of the device may write, or program, the state in the memory device.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others. Memory devices may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source. FeRAM may be able to achieve densities similar to volatile memory but may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device.

Improving memory devices, generally, may include increasing memory cell density, increase read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or improving manufacturing processes, among other metrics. Solutions for improving power consumption at a memory device may be desired.

Some memory devices may operate in one or more low power modes where the memory device may disable or change operation of circuitry supporting the memory cells to reduce power consumption. For example, a FeRAM device may transition from an idle state to a low power state that has lower power consumption than the idle state based on deactivating some amount of circuitry. In the low power state, the memory device may not be able to perform access operations (e.g., read operations, write operations, etc.) on memory cells of the memory device or able to transition directly to an active state in which such operations may be performed (e.g., when in the lower power state, the memory device may have to first transition to the idle state, then to the active state). In some cases, a FeRAM device may support different low power states associated with different decreased levels of current consumption (e.g., associated with different amounts of deactivated circuitry).

Similarly, a DRAM device may also transition its memory banks from an idle state to a low power state, which may include powering down one or more circuitry components to decrease the current consumption at the DRAM device. In some cases, a DRAM may maintain a self-refresh mode while powering down other components that are used to perform access operations (e.g., read operations, write operations, etc.).

Transitioning a memory device from a low power mode to an active mode (e.g., to an idle mode and then to an active mode) may take a period of time. For example, the memory device may need to perform one or more procedures to activate circuitry that was deactivated while in the low power state in order to access memory cells. In some cases, low power modes having lower current consumption (i.e., using less energy, having more circuitry deactivated) may take longer to transition to an idle or active mode.

Some memory devices (e.g., some FeRAM and DRAM devices) may control low power modes at a device or die level. That is, when entering a low power mode, circuitry for the entire device or die may change operating modes to use less power. Accordingly, if a memory device receives a command to perform an operation at the memory array, there may be a latency associated with transitioning the memory device or die from a low power mode to an idle mode and then transitioning at least a portion of the memory array (e.g., a bank of the memory array) to an active mode. Further, although the entire memory device may switch in or out of a low power mode, the access operations (e.g., read, write, etc.) may only be performed on the active portion of the memory array. As a result, the memory die may only switch to a low power mode if it will stay in that low power mode for a minimum duration, such as a long enough duration to achieve an overall reduction in power consumption (e.g., the reduced power use from operating in the low power mode is greater than power loss associated with transitioning the die into and out of the low power mode). Accordingly, a memory die may achieve less power savings than desired due to losses associated with switching the entire device or die into and out of a lower power mode. Further, a memory device or die may operate in a low power mode less frequently due to the latency required to wake up the entire device or die, further increasing power consumption.

A memory device may achieve greater power savings (e.g., less current consumption) by operating different portions of the memory device or a die therein (e.g., different portions of a single memory array) in different power modes. For example, a first portion of the memory device or die may be operated in a first power mode and a second portion of the memory device or die may be operated in a second power mode. The first power mode could be an active mode or a low power mode that can be accessed with a shorter latency (e.g., a quicker wake up time) than other low power modes. Such a low power mode with a relatively shorter latency may be referred to as a power down (PD) mode. The memory device may operate the second portion of the memory in a second low power mode as compared to the PD mode, where the second low power mode may be accessed with a longer latency. The low power mode with a relatively longer latency may be referred to as a deep sleep (DS) mode. In some case, a memory device may support multiple DS modes, which may respectively correspond to different amounts of power consumption (e.g., different amounts of deactivated circuitry for a portion of the memory device in the DS mode), and different portions of the memory device may concurrently be in different DS modes. In some cases, the memory device may switch the first portion of the memory from the PD mode to an idle or active mode while maintaining the second portion of memory in the DS mode (or vice versa). In this regard, the memory device may achieve increased power saving by operating different portions of the device in different power modes and in some cases only transitioning a portion of the memory cells to an active mode to perform access operations. Accordingly, the memory device may reduce losses from transitioning into and out of low power modes and operate in one or more low power modes more often and for a greater amount of time.

Aspects of the teachings herein include using a power mode bitmap to indicate the portions (e.g., memory banks) that are to be operated in various low power modes (e.g., PD and DS power modes). The power mode bitmap may be written to one or more registers (e.g., mode registers) or other storage within the memory device. Additionally or alternatively, the memory device may be configured via one or more commands for switching different portions (e.g., different memory banks) to one or more low power modes. In some cases, when the memory device receives a command to enter a low power mode, the memory device may access the power mode bitmap to determine which portions of the memory device should be operated in which low power mode. Further, while operating in one or more low power modes, the memory device may switch one or more portions from a low power mode to an active or idle mode, while maintaining other portions of the memory device in the low power mode. In some cases, the memory device may control low power modes at the bank level. Accordingly, the memory device may switch different banks between an active mode, an idle mode and one or more different low power modes.

Operation of the different portions of the memory device in different low power modes may result in an overall decreased current consumption. For example, the memory device may be able to operate some portions of the memory in a low power mode such as a DS mode more often and for longer periods of time as compared to a memory device which switches the entire memory device into and out of a low power mode. Further, the memory device may decrease latency operating a portion of the memory device in a PD mode that it can more quickly switching to an idle or active mode to address command received by the memory device.

In some cases, a memory device may benefit from operating some memory banks in a PD mode and other memory banks in one or more DS modes, including when the same or a limited number of banks are repeatedly accessed. For example, these frequently accessed banks may be operated in a PD mode, which may support more quickly switching them to idle/active modes for performing one or more access operations. Accordingly, these banks may achieve slightly increased power savings by switching between the PD mode and idle/active modes. Further, the memory device may achieve greater decreases in power use by operating other memory banks in one or more DS modes and may not need to switch theses DS banks into an idle/active mode because access operations are concentrated at the PD banks. Accordingly, the overall current use (e.g., due to both PD and DS modes) for a memory device may decrease as compared to systems that switch the entire memory device or die between active and low power modes. In some cases, operating additional memory banks in DS modes to increase power savings may decrease bandwidth for access operations due to the greater access times associated with portions of the memory device operating in the DS mode. The quantity of memory banks operating in each of the PD and DS modes may be varied to balance power savings and bandwidth. Further, in some cases a memory controller (internal or external to the memory device) may allocate data for one or more applications across one or more memory banks based on power consumption considerations (e.g., by concentrating associated data within a relatively small number of memory banks, to support increased use of DS modes for other memory banks). These and other benefits may be appreciated by one of ordinary skill in the art.

Features of the disclosure are initially described in the context of a memory system and memory die as described with reference to. Features of the disclosure are described in the context memory device state diagrams, process flows, power mode bitmaps, and power level consumption diagrams as described with reference to. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to bank-configurable power modes as described with references to.

illustrates an example of a systemthat utilizes one or more memory devices in accordance with examples as disclosed herein. The systemmay include an external memory controller, a memory device, and a plurality of channelscoupling the external memory controllerwith the memory device. The systemmay include one or more memory devices, but for ease of description the one or more memory devices may be described as a single memory device.

The systemmay include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. The systemmay be an example of a portable electronic device. The systemmay be an example of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, or the like. The memory devicemay be component of the system configured to store data for one or more other components of the system. In some examples, the systemis capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

At least portions of the systemmay be examples of a host device. Such a host device may be an example of a device that uses memory to execute processes such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, some other stationary or portable electronic device, or the like. In some cases, the host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller. In some cases, the external memory controllermay be referred to as a host or host device. In some examples, systemis a graphics card.

In some cases, a memory devicemay be an independent device or component that is configured to be in communication with other components of the systemand provide physical memory addresses/space to potentially be used or referenced by the system. In some examples, a memory devicemay be configurable to work with at least one or a plurality of different types of systems. Signaling between the components of the systemand the memory devicemay be operable to support modulation schemes to modulate the signals, different pin designs for communicating the signals, distinct packaging of the systemand the memory device, clock signaling and synchronization between the systemand the memory device, timing conventions, and/or other factors.

The memory devicemay be configured to store data for the components of the system. In some cases, the memory devicemay act as a slave-type device to the system(e.g., responding to and executing commands provided by the systemthrough the external memory controller). Such commands may include an access command for an access operation, such as a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands. The memory devicemay include two or more memory dice(e.g., memory chips) to support a desired or specified capacity for data storage. The memory deviceincluding two or more memory dice may be referred to as a multi-die memory or package (also referred to as multi-chip memory or package).

The systemmay further include a processor, a basic input/output system (BIOS) component, one or more peripheral components, and an input/output (I/O) controller. The components of systemmay be in electronic communication with one another using a bus.

The processormay be configured to control at least portions of the system. The processormay be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, the processormay be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphic processing unit (GPGPU), or a system on a chip (SoC), among other examples.

The BIOS componentmay be a software component that includes a BIOS operated as firmware, which may initialize and run various hardware components of the system. The BIOS componentmay also manage data flow between the processorand the various components of the system, e.g., the peripheral components, the I/O controller, etc. The BIOS componentmay include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

The peripheral component(s)may be any input device or output device, or an interface for such devices, that may be integrated into or with the system. Examples may include disk controllers, sound controller, graphics controller, Ethernet controller, modem, universal serial bus (USB) controller, a serial or parallel port, or peripheral card slots, such as peripheral component interconnect (PCI) or specialized graphics ports. The peripheral component(s)may be other components understood by those skilled in the art as peripherals.

The I/O controllermay manage data communication between the processorand the peripheral component(s), input devices, or output devices. The I/O controllermay manage peripherals that are not integrated into or with the system. In some cases, the I/O controllermay represent a physical connection or port to external peripheral components.

The inputmay represent a device or signal external to the systemthat provides information, signals, or data to the systemor its components. This may include a user interface or interface with or between other devices. In some cases, the inputmay be a peripheral that interfaces with systemvia one or more peripheral componentsor may be managed by the I/O controller.

The outputmay represent a device or signal external to the systemconfigured to receive an output from the systemor any of its components. Examples of the outputmay include a display, audio speakers, a printing device, or another processor on printed circuit board, and so forth. In some cases, the outputmay be a peripheral that interfaces with the systemvia one or more peripheral componentsor may be managed by the I/O controller.

The memory devicemay include a device memory controllerand one or more memory dice. Each memory diemay include a local memory controller(e.g., local memory controller-, local memory controller-, and/or local memory controller-N) and a memory array(e.g., memory array-, memory array-, and/or memory array-N). A memory arraymay be a collection (e.g., a grid) of memory cells, with each memory cell being configured to store at least one bit of digital data. Features of memory arraysand/or memory cells are described in more detail with reference to.

The memory devicemay be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die. A 3D memory device may include two or more memory dice(e.g., memory die-, memory die-, and/or any quantity of memory dice-N). In a 3D memory device, a plurality of memory dice-N may be stacked on top of one another or next to one another. In some cases, memory dice-N in a 3D memory device may be referred to as decks, levels, layers, or dies. A 3D memory device may include any quantity of stacked memory dice-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This may increase the quantity of memory cells that may be positioned on a substrate as compared with a single 2D memory device, which in turn may reduce production costs or increase the performance of the memory array, or both. In some 3D memory device, different decks may share at least one common access line such that some decks may share at least one of a word line, a digit line, and/or a plate line.

The device memory controllermay include circuits or components configured to control operation of the memory device. As such, the device memory controllermay include the hardware, firmware, and software that enables the memory deviceto perform commands and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device. The device memory controllermay be configured to communicate with the external memory controller, the one or more memory dice, or the processor. In some cases, the memory devicemay receive data and/or commands from the external memory controller. For example, the memory devicemay receive a write command indicating that the memory deviceis to store certain data on behalf of a component of the system(e.g., the processor) or a read command indicating that the memory deviceis to provide certain data stored in a memory dieto a component of the system(e.g., the processor). In some cases, the device memory controllermay control operation of the memory devicedescribed herein in conjunction with the local memory controllerof the memory die. Examples of the components included in the device memory controllerand/or the local memory controllersmay include receivers for demodulating signals received from the external memory controller, decoders for modulating and transmitting signals to the external memory controller, logic, decoders, amplifiers, filters, or the like.

The local memory controller(e.g., local to a memory die) may be configured to control operations of the memory die. Also, the local memory controllermay be configured to communicate (e.g., receive and transmit data and/or commands) with the device memory controller. The local memory controllermay support the device memory controllerto control operation of the memory deviceas described herein. In some cases, the memory devicedoes not include the device memory controller, and the local memory controlleror the external memory controllermay perform the various functions described herein. As such, the local memory controllermay be configured to communicate with the device memory controller, with other local memory controllers, or directly with the external memory controlleror the processor.

The external memory controllermay be configured to enable communication of information, data, and/or commands between components of the system(e.g., the processor) and the memory device. The external memory controllermay act as a liaison between the components of the systemand the memory deviceso that the components of the systemmay not need to know the details of the memory device's operation. The components of the systemmay present requests to the external memory controller(e.g., read commands or write commands) that the external memory controllersatisfies. The external memory controllermay convert or translate communications exchanged between the components of the systemand the memory device. In some cases, the external memory controllermay include a system clock that generates a common (source) system clock signal. In some cases, the external memory controllermay include a common data clock that generates a common (source) data clock signal.

In some cases, the external memory controlleror other component of the system, or its functions described herein, may be implemented by the processor. For example, the external memory controllermay be hardware, firmware, or software, or some combination thereof implemented by the processoror other component of the system. While the external memory controlleris depicted as being external to the memory device, in some cases, the external memory controller, or its functions described herein, may be implemented by a memory device. For example, the external memory controllermay be hardware, firmware, or software, or some combination thereof implemented by the device memory controlleror one or more local memory controllers. In some cases, the external memory controllermay be distributed across the processorand the memory devicesuch that portions of the external memory controllerare implemented by the processorand other portions are implemented by a device memory controlleror a local memory controller. Likewise, in some cases, one or more functions ascribed herein to the device memory controlleror local memory controllermay in some cases be performed by the external memory controller(either separate from or as included in the processor).

The components of the systemmay exchange information with the memory deviceusing a plurality of channels. In some examples, the channelsmay enable communications between the external memory controllerand the memory device. Each channelmay include one or more signal paths or transmission mediums (e.g., conductors) between terminals associated with the components of system. For example, a channelmay include a first terminal including one or more pins or pads at external memory controllerand one or more pins or pads at the memory device. A pin may be an example of a conductive input or output point of a device of the system, and a pin may be configured to act as part of a channel. In some cases, a pin or pad of a terminal may be part of to a signal path of the channel. Additional signal paths may be coupled with a terminal of a channel for routing signals within a component of the system. For example, the memory devicemay include signal paths (e.g., signal paths internal to the memory deviceor its components, such as internal to a memory die) that route a signal from a terminal of a channelto the various components of the memory device(e.g., a device memory controller, memory dice, local memory controllers, memory arrays).

Channels(and associated signal paths and terminals) may be dedicated to communicating specific types of information. In some cases, a channelmay be an aggregated channel and thus may include multiple individual channels. For example, a data channelmay be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (e.g., including sixteen signal paths), and so forth. Signals communicated over the channels may use a double data rate (DDR) timing scheme. For example, some symbols of a signal may be registered on a rising edge of a clock signal and other symbols of the signal may be registered on a falling edge of the clock signal. Signals communicated over channels may use single data rate (SDR) signaling. For example, one symbol of the signal may be registered for each clock cycle.

In some cases, the channelsmay include one or more command and address (CA) channels. The CA channelsmay be configured to communicate commands between the external memory controllerand the memory deviceincluding control information associated with the commands (e.g., address information). For example, the CA channelmay include a read command with an address of the desired data. In some cases, the CA channelsmay be registered on a rising clock signal edge and/or a falling clock signal edge. In some cases, a CA channelmay include any quantity of signal paths to decode address and command data (e.g., eight or nine signal paths).

In some cases, the channelsmay include one or more clock signal (CK) channels. The CK channelsmay be configured to communicate one or more common clock signals between the external memory controllerand the memory device. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controllerand the memory device. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal paths of the CK channelsmay be configured accordingly. In some cases, the clock signal may be single ended. A CK channelmay include any quantity of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations for the memory device, or other system-wide operations for the memory device. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, or the like).

In some cases, the channelsmay include one or more data (DQ) channels. The data channelsmay be configured to communicate data and/or control information between the external memory controllerand the memory device. For example, the data channelsmay communicate information (e.g., bi-directional) to be written to the memory deviceor information read from the memory device.

In some cases, the channelsmay include one or more other channelsthat may be dedicated to other purposes. These other channelsmay include any quantity of signal paths.

The channelsmay couple the external memory controllerwith the memory deviceusing a variety of different architectures. Examples of the various architectures may include a bus, a point-to-point connection, a crossbar, a high-density interposer such as a silicon interposer, or channels formed in an organic substrate or some combination thereof. For example, in some cases, the signal paths may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

Signals communicated over the channelsmay be modulated using a variety of different modulation schemes. In some cases, a binary-symbol (or binary-level) modulation scheme may be used to modulate signals communicated between the external memory controllerand the memory device. A binary-symbol modulation scheme may be an example of a M-ary modulation scheme where M is equal to two. Each symbol of a binary-symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary-symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) having two symbols (e.g., PAM2), and/or others.

The memory devicemay receive one or more commands to operate one or more portions of the memory devicein a low power mode. For example, the memory devicemay receive a command to write power bitmap data (e.g., via a CA channel) to one or more mode registers of the memory device. The power bitmap data may indicate a first portion of the memory device(e.g., one or more memory banks) to be operated in a first low power mode such as a PD mode. The power bitmap data may also indicate a second portion of the memory deviceto be operated in a second low power mode that is associated with a lower power consumption level than the first mode such as a DS mode. The memory devicemay receive the power bitmap data and write it to one or more mode registers.

The memory devicereceive a command to enter a low power mode and access the power bitmap data stored on the mode registers. Additionally or alternatively, the memory devicemay receive one or more commands specifying information that may be otherwise written to mode registers. The memory devicemay switch the first portion of the memory deviceto the PD mode and switch the second portion of the memory deviceto the DS mode. While operating in the first and second portions in their respective low power modes, the memory devicemay receive a command to switch the first portion from the PD mode, for example, to an idle or active mode (e.g., the memory devicemay receive a command to selectively switch only portions in the PD mode to an idle or active mode, leaving portions in a DS mode in the DS mode). The memory devicemay cause the first portion of the memory deviceto exit from the PD mode while continuing to operate the second portion in the DS mode. The memory devicemay perform one or more operations at the first portion of the memory device. For example, the memory devicemay perform read or write operations on banks associated with the first portion of the memory device. In some cases, the memory devicemay receive a command to switch the first portion back to the low power mode and cause the first portion to enter the PD mode.

illustrates an example of a memory diein accordance with examples as disclosed herein. The memory diemay be an example of the memory dicedescribed with reference to. In some cases, the memory diemay be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory diemay include one or more memory cellsthat are programmable to store different logic states. Each memory cellmay be programmable to store two or more states. For example, the memory cellmay be configured to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some cases, a single memory cell(e.g., a multi-level memory cell) may be configured to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, or a logic 11).

A memory cellmay store a state (e.g., polarization state or dielectric charge) that represents digital data. In FeRAM architectures, the memory cellmay include a capacitor that includes a ferroelectric material to store a charge and/or a polarization representative of the programmable state. In DRAM architectures, the memory cellmay include a capacitor that includes a dielectric material to store a charge representative of the programmable state.

Operations such as reading and writing may be performed on memory cellsby activating or selecting access lines such as a word line, a digit line, and/or a plate line. In some cases, digit linesmay also be referred to as bit lines. References to access lines, word lines, digit lines, plate lines or their analogues, are interchangeable without loss of understanding or operation. Activating or selecting a word line, a digit line, or a plate linemay include applying a voltage to the respective line.

The memory diemay include the access lines (e.g., the word lines, the digit lines, and the plate lines) arranged in a grid-like pattern. Memory cellsmay be positioned at intersections of the word lines, the digit lines, and/or the plate lines. By biasing a word line, a digit line, and a plate line(e.g., applying a voltage to the word line, digit line, or plate line), a single memory cellmay be accessed at their intersection.

Accessing the memory cellsmay be controlled through a row decoder, a column decoder, and a plate driver. For example, a row decodermay receive a row address from the local memory controllerand activate a word linebased on the received row address. A column decoderreceives a column address from the local memory controllerand activates a digit linebased on the received column address. A plate drivermay receive a plate address from the local memory controllerand activates a plate linebased on the received plate address. For example, the memory diemay include multiple word lines, labeled WL_1 through WL_M, multiple digit lines, labeled DL_1 through DL_N, and multiple plate lines, labeled PL_1 through PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating a word line, a digit line, and a plate line, e.g., WL_1, DL_3, and PL_1, the memory cellat their intersection may be accessed. The intersection of a word lineand a digit line, in either a two-dimensional or three-dimensional configuration, may be referred to as an address of a memory cell. In some cases, the intersection of a word line, a digit line, and a plate linemay be referred to as an address of the memory cell.

The memory cellmay include a logic storage component, such as capacitor, and a switching component. The capacitormay be an example of a ferroelectric capacitor. A first node of the capacitormay be coupled with the switching componentand a second node of the capacitormay be coupled with a plate line. The switching componentmay be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

Selecting or deselecting the memory cellmay be accomplished by activating or deactivating the switching component. The capacitormay be in electronic communication with the digit lineusing the switching component. For example, the capacitormay be isolated from digit linewhen the switching componentis deactivated, and the capacitormay be coupled with digit linewhen the switching componentis activated. In some cases, the switching componentis a transistor and its operation is controlled by applying a voltage to a transistor gate, where the voltage differential between the transistor gate and transistor source is greater or less than a threshold voltage of the transistor. In some cases, the switching componentmay be a p-type transistor or an n-type transistor. The word linemay be in electronic communication with the gate of the switching componentand may activate/deactivate the switching componentbased on a voltage being applied to word line.

A word linemay be a conductive line in electronic communication with a memory cellthat is used to perform access operations on the memory cell. In some architectures, the word linemay be in electronic communication with a gate of a switching componentof a memory celland may be configured to control the switching componentof the memory cell. In some architectures, the word linemay be in electronic communication with a node of the capacitor of the memory celland the memory cellmay not include a switching component.