Voltage converter with regulated switching frequency and minimum on time override

This application is based upon and claims the benefit of priority under 35 U.S.C. 119 (e) to U.S. Patent Application No. 63/488,346 filed on Mar. 3, 2023, and titled “VOLTAGE CONVERTER WITH REGULATED SWITCHING FREQUENCY AND MINIMUM ON TIMEOVERRIDE,” the entire disclosure of which is incorporated herein by reference in its entirety.

The present disclosure relates to methods and systems for voltage regulators. Particularly, a hysteretic current mode buck regulator with regulated switching frequencies and minimum on time override is described.

Voltage regulators or voltage converters, such as buck converters and boost converters, can be used for converting an input voltage to an output voltage having a different voltage level. A buck converter, or step-down converter, can convert the input voltage into a lower voltage. A boost converter, or step-up converter, can convert the input voltage into a higher voltage. A buck-boost converter can step up or step down the input voltage. A voltage converter can include multiple switches that can be turned on and off by a pulse width modulated (PWM) control signal. A duty ratio of the PWM control signal can determine an output voltage of the voltage converter.

In one embodiment, a method that can implement a voltage converter with regulated switching frequency and minimum on time override is generally described. The method can include determining a pulse width modulation (PWM) on time duration being used for operating a voltage regulator. The method can further include determining a switching frequency being used for operating the voltage regulator. The method can further include determining whether the PWM on time duration is greater than or less than an on time reference. The method can further include, in response to determining that the PWM on time duration is less than the on time reference, increasing a voltage window for a PWM signal being used to operate the voltage regulator. The method can further include, in response to determining that the PWM on time duration is greater than the on time reference, performing a frequency locked loop (FLL) to regulate the switching frequency.

In one embodiment, a semiconductor device that can implement a voltage converter with regulated switching frequency and minimum on time override is generally described. The semiconductor device can include a controller configured to determine a pulse width modulation (PWM) on time duration being used for operating a voltage regulator. The controller can further be configured to determine a switching frequency being used for operating the voltage regulator. The controller can further be configured to determine whether the PWM on time duration is greater than or less than an on time reference. The controller can further be configured to, in response to the determination that the PWM on time duration is less than the on time reference, increase a voltage window for a PWM signal being used to operate the voltage regulator. The controller can further be configured to in response to the determination that the PWM on time duration is greater than the on time reference, perform a frequency locked loop (FLL) to regulate the switching frequency.

In one embodiment, a system that can implement a voltage converter with regulated switching frequency and minimum on time override is generally described. The system can include a power stage configured to convert an input voltage into an output voltage. The system can further include a driver circuit configured to drive the power stage. The system can further include a controller configured to generate a control signal for operating the driver circuit. The controller can further be configured to determine a pulse width modulation (PWM) on time duration being used for driving the power stage. The controller can further be configured to determine a switching frequency being used for driving the power stage. The controller can further be configured to determine whether the PWM on time duration is greater than or less than an on time reference. The controller can further be configured to in response to the determination that the PWM on time duration is less than the on time reference, increase a voltage window of the control signal. The controller can further be configured to in response to the determination that the PWM on time duration is greater than the on time reference, perform a frequency locked loop (FLL) to regulate the switching frequency.

Further features as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.

is a diagram showing a system that can implement a switching frequency regulator and a minimum on time override function in one embodiment. A systemshown incan be implemented by a voltage regulation system or voltage converter. Systemcan include a controller, driver integrated circuit (IC), power stage, inductor, and load.

Controllercan include, for example, a processor, microcontroller, central processing unit (CPU), field-programmable gate array (FPGA) or any other circuitry that is configured to control and operate system. While described as a CPU in illustrative embodiments, controlleris not limited to a CPU in these embodiments and may comprise any other circuitry that is configured to control and operate driver IC. Controllercan be configured to generate control signals, such as pulse width modulation (PWM) or pulse frequency modulation (PFM) signals (labeled as PWM in the figures herewith) for controlling a driver ICto selectively turn switches HS and LS in power stageon and off. Controllercan control characteristics of the control signals such as the duty ratio or the switching frequency based on various conditions such as feedback from voltage Vramp to be described in more detail below.

Driver ICcan be configured to receive PWM signals from controller. Driver ICcan generate drive signalsusing the received PWM signals. Driver ICcan drive the switches in power stagevia drive signals. Drive signalscan be a voltage signal having a gate voltage that can turn on or off the high-side (HS) and low-side (LS) switches of power stage. In one embodiment, HS and LS switches can be field-effect transistors (FETs) such as metal oxide semiconductor field effect transistors (MOSFETs). In other embodiments, HS and LS switches can be diodes or insulated-gate bipolar transistors (IGBTs). Driver ICcan include a driver configured to drive HS switch and another driver configured to drive LS switch in power stage. Driver ICcan be configured to provide the gate voltages or drive signalsto drive HS and LS switches. HS switch can be switched on while LS switch is switched off, and vice versa. When HS switch is switched on and LS switch is switched off, a voltage at a switch node Vsw between HS switch and LS switch can be pulled up to Vin such that the voltage at the switch node Vsw is equivalent to Vin. When HS is switched off and LS is switched on, the voltage at the switch node can be pulled down to ground, hence Vsw is equivalent to zero.

Power stagecan be configured to receive drive signalsfrom driver IC. The HS and LS switches can be switched on and off to generate output voltage Vout. Output voltage Vout can be outputted to, for example, a loadthrough an inductor. Vout can be fed back to controlleras a feedback signalto provide controllerwith feedback information.

In switching voltage converters, such as system, frequency control can impact predictable dynamics, component selection, efficiency, and stability. Control of power stageminimum switch on and off time can also impact various functions such as current sense detection, stable steady state operation, overcurrent detection, etc. A voltage mode or current mode power converter may utilize a fixed switching frequency, while a hysteretic mode power converter may change a switching frequency to adjust an output voltage. In addition, in conventional systems, frequency control and minimum on and off time control can be performed by different circuits and different control loops. For example, frequency control can be performed by using a frequency locked loop (FLL) to regulate the switching frequency while PWM signals alternate between high and low voltages. However, at a low output voltage Vout and with an FLL in place, the minimum on-time of the PWM signal can significantly drop. Having an on-time below the minimum requirements can cause problems such as difficulty in sensing fault conditions.

In a situation where both the switching frequency needs to be regulated and minimum on-time needs to be increased, the two operations can clash with each other, e.g., minimum on-time needs to be increased while switching frequency is being regulated for a low output voltage Vout. To be described in more detail below, the controllercan be configured to receive the feedback signalto regulate the switching frequency and minimum on-time. More specifically, the controllercan use the FLL block under specific conditions to prioritize regulation of the minimum on time rather than the switching frequency to improve efficiency, and having controllerregulate both minimum on time and switching frequency can reduce bill-of-material costs.

. is a diagram showing an example voltage regulator system that can implement a switching frequency regulator and a minimum on time override function in one embodiment. Descriptions ofmay reference components shown in. In another example embodiment, controllercan include at least an error amplifier, voltage sources,, comparators,, an S-R latch, an FLL circuit, and amplifier. Error amplifiercan be configured to receive a feedback signalfrom the systemoutput Vout. Error amplifiercan also receive a predefined reference voltage Vref. Error amplifiercan compare the feedback signalwith Vref to generate an error difference and can generate a control voltage Vc based on the error difference. Voltage sourcesandcan be configured to increase and decrease a voltage window Vw for the presently active PWM cycle. The voltage window can bound control voltage Vc within a voltage range defined by an upper voltage boundary Vw+ and a lower voltage boundary Vw−, and control voltage Vc can be a voltage centered between Vw+ and Vw− (e.g., median of Vw+ and Vw−). Changes to the voltage window, or changes to Vw+ and Vw−, can change the switching frequency and/or the PWM on time of the PWM signals being outputted by the S-R latch.

In the embodiment shown in, the first voltage supplycan control upper voltage boundary Vw+ of the voltage window Vw and the second voltage supplycan control a lower voltage boundary Vw− of the voltage window Vw. Comparatorsandcan be configured to receive outputs from the voltage window Vw boundaries Vw+ and Vw− as well as voltage feedback information Vramp. Amplifiercan generate Vramp by sensing a voltage across inductorand amplifying the sensed voltage based on a gain gm. Comparatorcan receive the upper boundary voltage Vw+ at the inverting input (−) and can receive Vramp at the non-inverting input (+). Comparatorcan receive the lower boundary voltage Vw− at the non-inverting input (+) and can receive Vramp at the inverting input (−).

The PWM signal can be in a high state (e.g., “T” or “true” state) or a low state (e.g., “F” or “false” state). Based on the PWM signal, driver ICcan enforce the state of the HS and LS switches. For example, while the PWM signal is in the high state, the driver ICenforces HS on, and LS off. While PWM is in the low state, the driver ICenforces HS off, and LS on. The voltage feedback information Vramp can emulate the current flowing through inductorwhich is subject to the logic states of the PWM signal. For example, when switch HS is on and switch LS is off, Vramp is increasing which is indicative of current flowing through the inductorincreasing. When switch HS is off and switch LS is on, Vramp is decreasing which is indicative of current flowing through inductordecreasing.

Comparatorsandcan produce logical outputs that are indicative of the relative voltage of their (+) and (−) inputs. Whenever the voltage of the (+) input of the comparator (comparatoror comparator) is higher than the voltage of the (−) input, the comparator can output logic state “T” or “true” . . . . If the voltage of the (−) input is higher than the voltage of the (+) input, the comparator can output logic state “F” or “false”.

S-R latchcan receive the output of comparatorsandas inputs. The output of comparatorcan be provided to the reset pin R of S-R latch, and the output of comparatorcan be provided to the set pin S of S-R latch. The S-R latchcan be configured to generate the PWM signal based on the input voltages at the set and reset pins of S-R latch. The PWM signals can be outputted to driver ICand driver ICcan generate drive signalsto drive the power stage.

When S-R-latchoutputs a PWM signal in a high or “T” state, the driver ICcan turn on HS switch and turn off LS switch, and Vramp can increase. When Vramp rises above the top of the voltage window Vw+ (i.e., Vc+ voltage source) comparatorcan output logic state T, which when applied to the R pin input of S-R-latchwill RESET the S-R latch. The reset of S-R latchreleases the PWM, i.e., outputs the PWM signal in a “F” state. The PWM signal in an “F” state turns off HS switch and turns on LS switch, via driver IC, causing Vramp to decrease. When Vramp descends below Vw− (i.e., Vc− voltage source), the R input is released, but the S-R latchretains the PWM “F” state.

When SR-latchoutputs a PWM signal in a low or “F” state, the driver ICcan turn off HS switch and turn on LS switch, and Vramp will decrease. When Vramp descends below the bottom of the voltage window Vw− (i.e., Vc− supply voltage), comparatorcan output logic state “T”, which when applied to the S pin input of SR-latchwill SET S-R latch. The setting of S-R Latchoutputs the PWM signal in a “T” state, which, via driver, turns on HS switch and turns off LS switch, causing Vramp to now increase. When Vramp ascends above Vw−, the S input is released, but the S-R latchretains the PWM “T” state.

The duration of rising Vramp in any complete cycle is designated as the on-time Ton. The duration of descending Vramp in any complete cycle is designated as the off-time Toff. The total cycle time Ton+Toff is designated as the switching period Tsw. The switching frequency is the reciprocal of Tsw, that is, Fsw=1/Tsw. The ratio of on time to total cycle time is designated the duty ratio D; D=Ton/(Ton+Toff)=Ton/Tsw. The duty ratio D is the parameter that the controllermodifies to regulate the output voltage Vout. Ton can be expressed as Ton=D*Tsw, or Ton=D/Fsw.

In an embodiment, Ton and Toff can be determined by the size of the voltage window Vw. For example, a larger voltage window Vw produces a larger Ton and Toff which in turn produces a larger Tsw. A smaller voltage window Vw produces a smaller Ton and Toff which in turn produces a smaller Tsw. By varying the size of voltage window Vw, a desired switching frequency Fsw can be obtained. Changing Ton by changing Vw can also change Tsw by the same proportion. Thus changing the voltage window Vw may not directly change duty ratio D.

Controllercan include an FLL circuit. FLL circuitcan receive the PWM signal output by the S-R latch, a clock signal CLK, and a predetermined or programmable reference switching frequency (Fsw Ref). The FLL circuitcan monitor the PWM signal in real time and determine the switching frequency Fsw using the PWM signal. By way of example, the FLL circuitcan be configured to measure Tsw by measuring the Ton and Toff times in the received PWM signal and summing the measured Ton and Toff. FLL circuitcan determine a reciprocal of Tsw to determine switching frequency Fsw of the received PWM signal. Thus, FLL circuitcan monitor the switching frequency Fsw using the received PWM signal. FLL circuitcan compare the switching frequency Fsw of the received PWM signal with the reference Fsw Ref. Based on the comparison, FLL circuitcan determine whether to increase the voltage window Vw to reduce Fsw or to decrease the voltage window Vw to increase Fsw. In one embodiment, FLL circuitcan also compare Tsw of the received PWM signal with a cycle time reference and based on this comparison, determine whether to increase the voltage window Vw or to decrease the voltage window Vw. The determination of whether to increase or decrease the voltage window Vw can be made by FLL circuitat the end of each cycle because the measurement of Tsw requires that the full cycle time Tsw to be observed. In one example embodiment, the clock signal CLK being received by FLL circuitcan be used for measuring the switching frequency Fsw.

In response to determining whether to increase or decrease the voltage window Vw, FLL circuitcan adjust (e.g., increment or decrement) the voltage window Vw as indicated by a result of the determination. The adjustment of the voltage window Vw can be in effect for the current switching cycle, or switching cycle n. The voltage window size decision (e.g., amount to increment or decrement) and any adjustment to the size of the voltage window, can be instantaneous, thus the decision from current cycle can be in effect for next cycle, or cycle n+1, as well. In one embodiment, the FLL circuitcan output a voltage signalthat can be used by controllerto adjust the voltage window Vw boundaries Vw+ and Vw−. If the Fsw Ref is less than the measured switching frequency from the PWM signal, then the voltage window can be decreased to increase the switching frequency Fsw. The FLL circuitcan decrease the voltage window by decreasing the voltage sourceto reduce the upper boundary Vw+ and decreasing the voltage sourceto the raise boundary Vw−, thus creating a narrower (e.g., decreased) voltage window Vw. If the Fsw Ref is greater than the measured switching frequency from the PWM signal, then the voltage window can be increased to reduce the switching frequency Fsw. The FLL circuitcan increase the voltage window by increasing the voltage sourceto raise the upper boundary Vw+ and increasing the voltage sourceto increase the difference between Vc and Vw−, thus, lowering the lower boundary Vw− and creating a wider (e.g., increased) voltage window Vw. The amount of adjustments made to voltage sources,for adjusting voltage window Vw can be equal or can be different from one another depending on a desired implementation of system. In one embodiment, if a desired implementation requires voltage window Vw to be symmetric with Vc at the center, then the amount of adjustments made to voltage sources,can be equivalent to maintain symmetry of the voltage window centered at Vc. In another embodiment, if a desired implementation does not require voltage window Vw to be symmetric, then the amount of adjustments made to voltage sources,can be different. By way of example, to adjust voltage window without adjusting voltage sources,with equal adjustments, FLLcan apply voltage signalon either one of voltage sources,, instead of both, to adjust the voltage window.

FLL circuitcan also be configured to adjust the voltage window Vw to increase the on-time duration of the PWM signal. FLL circuitcan be configured to determine whether the minimum on time duration of the PWM signal crosses a predefined threshold. The predefined threshold can be a programmable minimum on-time (Ton Ref) that represents the minimum time a switch needs to be on for controllerto function correctly, a limitation due to limitations on the rate of switch transition time, or other operational constraints. If the on time is lower than a Ton Ref, then controllercan increase the voltage window Vw+, i.e., increasing the voltage sourceto raise the upper boundary Vw+ and increasing the voltage sourceto lower the lower boundary Vw−. If the on time is greater than a pre-determined reference on-time duration, then FLL circuitcan continue to regulate the switching frequency of system. By this decision precedence, the constraint of minimum on-time supersedes the regulation of Fsw; Fsw is controlled, subject to the higher priority constraint that minimum on-time is not violated.

The switching frequency Fsw, as determined by the window size Vw, can deviate from the expected value due to various nonidealities in system. These nonidealities can vary with operating conditions such as desired output voltage, the Vin supply voltage, regulator load current, dissipation of power in lossy components, the number of active phases in a multi-phase controller, and temperature, and/or other conditions that can alter switching frequency. The FLL circuitprovides a frequency regulation mechanism that overcomes the uncertainties that impact switching frequency Fsw accuracy.

The duty ratio D, which determines the output voltage, must be adjusted for its own set of nonidealities that contribute to output voltage accuracy, which includes power loss elements and load variations along with other practical deviations from ideal performance. But the duty ratio D of controlleris primarily determined by the ratio of the desired output voltage to the input supply voltage, by the approximation D=Vout/Vin. Recall that Ton=Tsw*D=D/Fsw. So for a given Fsw, Ton=(Vout/Vin)/Fsw. For the condition of Vin sufficiently larger than Vout, and if Fsw is sufficiently high, Ton can be very small, potentially violating the minTon constraint. In another embodiment, Ton can be estimated instead of being measured. An estimation can be made based on various parametric values such as the measure of Vin and Vout. The voltage regulation of the Vout depends on both Vin and the desired Vout level. When the minimum on-time (minTon) needs to be met, but is limited by Vin and the desired Vout level, the switching frequency Fsw needs to be decreased. This adjustment is made by increasing the voltage window Vw. This compromise is necessary to ensure the proper functioning of the voltage regulator. Thus, the regulation of the switching frequency Fsw is determined by the need to meet the minimum on-time constraint.

The embodiments shown herein can allow a controller to perform both regulation of PWM on-time and switching frequency, where the PWM on time regulation can be prioritized over switching frequency regulation. The priority given to the PWM on-time regulation can avoid issues caused by low PWM on-time in low duty ratio operating conditions.

is a flow diagram illustrating a process to implement a switching frequency regulator and a minimum on time override function in one embodiment. Descriptions ofmay reference components shown in. The processcan include one or more operations, actions, or functions as illustrated by one or more of blocks,,,,,,, and. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, performed in different order, or performed in parallel, depending on the desired implementation.

Processcan be implemented by a voltage regulator system. For example, controllerof systemcan perform process. Processcan begin at block. At block, controllercan determine whether a new PWM cycle has occurred. By way of example, controllercan detect a rising edge of the PWM signal and the rising edge is an indication of a new PWM cycle. If controllerdoes not detect a new PWM cycle (: NO), processcan loop around blockuntil a new PWM cycle begins.

If controllerdetermines a new PWM cycle has begun at block(: YES), then processcan continue from blockto block. At block, controllercan determine an on time PWMTon and a switching frequency Fsw of the previously completed PWM cycle, or PWM cycle n−1. The on time PWMTon can be a duration in time of a PWM signal in the PWM cycle n−1 being in the “on” state and the switching frequency Fsw can be the rate at which the HS and LS switches switch on and off to generate the PWM signal in PWM cycle n−1. Controllercan latch the determined on time PWMTon and the latched switching frequency Fsw. Processcan continue from blockto block. At block, controllercan determine whether the latched PWMTon is less than Ton Ref (see). The comparison being made by controlleris to check whether the minimum on-time operation needs to override the frequency regulation operation. If the latched PWMTon is less than the Ton Ref (: YES), then the minimum on-time function needs to be in operation, and processcan continue from blockto block

At block, controllercan increase the voltage window Vw. By increasing the voltage window Vw, the PWM Ton can be increased, (and also Toff, and so also Tsw, in the same proportion as the increase in Ton, thus preserving D). This decision precedes, and if taken, supersedes the regulation of Fsw, ensuring that the minimum on-time function has higher priority that Fsw regulation. Therefore, the regulation of PWM on time is prioritized over regulation of switching frequency.

If in blockthe PWMTon is greater than the Ton Ref (: NO), then processcan continue from blockto block. The determination that PWMTon is greater than the Ton Ref means that the minimum on-time function does not need to be in operation and the FLL can continue regulating the switching frequency. At block, controlleris configured to determine whether the latched PWM switching frequency is less than a low reference switching frequency FswLowRef. In an example embodiment, there can be two reference switching frequencies. A low reference switching frequency FswLowRef and high reference switching frequency FswHighRef that is greater than FswLowRef. If the latched PWM switching frequency is less than the FswLowRef (: YES), then processcan continue from blockto. Note that the comparisons being made to the two switching frequency references can regulate Fsw within a defined range such that dithering between the switching frequency boundaries can be reduced. The range between FswLowRef and FswHighRef can vary depending on various conditions. In one or more embodiments, there can be a predefined nominal switching frequency, and a range of frequencies around the nominal frequency can be assigned as a threshold range of frequencies where the switching frequency can impact the mechanisms and operational parameters of system. The range of frequencies can be used for setting the references FswLowRef and FswHighRef.

At block, controllercan decrease the voltage window. Decreasing the voltage window can increase the switching frequency to obtain a regulated switching frequency level between FswLowRef and FswHighRef. If the latched PWM switching frequency is greater than the FswLowRef (: NO), then processcan continue from blockto. At block, controlleris configured to determine whether the PWM switching frequency is greater than FswHighRef. If the PWM switching frequency is greater than the FswHighRef (: YES), then the processcan continue from blockto. At block, controlleris configured to increase the voltage window Vw. Increasing the voltage window would decrease the switching frequency to obtain a regulated switching frequency level between FswLowRef and FswHighRef. If the PWM switching frequency is less than the FswHighRef (: NO), then controllerdoes not need to adjust the voltage window and can return back to blockto wait for the next PWM cycle to begin.

is a flow diagram illustrating another process to implement a switching frequency regulator and a minimum on time override function in another embodiment. Descriptions ofmay reference components shown in. The processcan include one or more operations, actions, or functions as illustrated by one or more of blocks,,,,,,,, and, Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, performed in different order, or performed in parallel, depending on the desired implementation.

Processcan be implemented by a voltage regulator system. For example, controllerof systemcan perform process. Processcan begin at block. At block, controllercan determine whether a new PWM cycle has occurred. By way of example, controllercan detect a rising edge of the PWM signal and the rising edge is an indication of a new PWM cycle. If controllerdoes not detect a new PWM cycle (: NO), processcan loop around blockuntil a new PWM cycle begins.

If controllerdetermines a new PWM cycle has begun at block(: YES), then processcan continue from blockto block. At block, controllercan determine an on time PWMTon and a switching frequency Fsw of the previously completed PWM cycle, or PWM cycle n−1. The on time PWMTon can be a duration in time of a PWM signal in the PWM cycle n−1 being in the “on” state and the switching frequency Fsw can be the rate at which the HS and LS switches switch on and off to generate the PWM signal in the PWM cycle n−1. Controllercan latch the determined on time PWMTon and the latched switching frequency Fsw.

At block, controllercan determine whether the latched PWMTon is less than a first reference on time (Ton Ref). Ton Refis a first predefined threshold that can be programmable and represents the minimum time a switch needs to be on for controllerto operate correctly. If the latched PWMTon is less than the Ton Ref(: YES), then processcan continue from blockto block.

At block, controlleris configured to increase the voltage window Vw. By increasing the voltage window Vw, the PWM Ton can be increased. If the PWMTon is greater than the Ton Ref(: NO), then processcan continue from blockto block.

At block, controllercan return to regulating switching frequency since controllerhas determined that the minimum on-time constraint has been satisfied, so the override operation is no longer necessary. Controllercan determine whether the PWM switching frequency is less than the FswLowRef. If the PWM switching frequency is less than the FswLowRef (: YES), then processcan continue from blockto block.

At block, controllercan determine whether the PWMTon is less than a second reference on time (Ton Ref). Ton Refis a second predefined threshold that can be programmable and represents a second reference on-time that is greater than the first reference on-time TonRef. The two reference on-times Ton Ref, Ton Ref, can create a window boundary that allows controllerto continue monitoring minimum on-time while the on-time is within the on-time window. For example, when the measured minimum on-time is hovering around the threshold level e.g., Ton Ref. Note that the comparisons being made to the two PWM on time references can regulate PWMTon within a defined range such that jittering at the on time boundaries can be reduced.

If the latched PWMTon is less than the Ton Ref(: YES), then processcan continue from blockto blockto wait for a new PWM cycle (cycle n+2).

If the latched PWMTon is greater than the Ton Ref(: NO), then processcan continue from blockto block. At block, controllercan decrease the voltage window. Returning to decision block, if the PWM switching frequency is greater than the FswLowRef (: NO), then processcan continue from blockto. At block, controllercan determine whether the PWM switching frequency is greater than the FswHighRef. If the PWM switching frequency is greater than the FswHighRef (: YES), then the processcan continue from blockto. At block, controlleris configured to increase the voltage window Vw. If the PWM switching is less than the FswHighRef (: NO), then controllerdoes not need to adjust the voltage window and can return back to blockto wait for the next PWM cycle (PWM cycle n+1) to begin. As shown in, after latching PWM Ton and Fsw in block, instead of performing a FLL, controllerchecks whether the PWM on time (PWM Ton) is within a desired range (e.g., between Ton Refand Ton Ref). Therefore, the regulation of PWM on time is prioritized over regulation of switching frequency. Note that the comparisons being made to the two switching frequency references can regulate Fsw within a defined range such that dithering at the switching frequency boundaries can be reduced.

Note that in process, the switching frequency test in blockis performed prior to the Ton_reftest (e.g., block) to prevent a condition where Ton is between Ton_refand Ton_refand the voltage window needs to be increased to reduce the switching frequency. Further, the switching frequency test being performed prior to the Ton_reftest can allow the voltage window to be reduced (e.g., block) when the switching frequency is too low (e.g.,: YES). If the switching frequency is too high (: YES), then the voltage window will increase regardless of the result of the Ton_reftest

is a diagram illustrating an implementation of a switching frequency regulator and a minimum on time override function in another embodiment. Descriptions ofmay reference components shown in. In an example embodiment, lineillustrates the minimum on-time with switching frequency regulator and a minimum on time override function implemented. Lineillustrates the minimum on-time without switching frequency regulator and a minimum on time override function implemented. Linerepresents the predefined Ton Ref. Lineillustrates the switching frequency without switching frequency regulator and a minimum on time override function implemented. Lineillustrates the switching frequency with switching frequency regulator and a minimum on time override function implemented. Lineillustrates the voltage output Vout.

In an example embodiment, the starting condition begins with a programmed switching frequency of 1 MHz with an output voltage Vout of 1.0 V depicted by linefor 200 microseconds. While Vout is at 1.0 V, the measured PWM Ton depicted by lineandcan be at 120 nanoseconds. During time 200 microseconds to 300 microseconds, Vout changes from 1.0 V to 0.3 V. When systemutilizes an FLL to regulate the switching frequency, linesanddepict how the PWM Ton and switching frequency may react to the utilization of the FLL without Min_Ton override control. When Vout reaches 0.3V, the PWM Ton for linedrops to less than 40 nanoseconds which can cause switching operation issues and regulation issues, including current sense problems and difficulty in sensing fault conditions. As shown in, the predetermined Ton Ref was defined as 60 nanoseconds shown by line. Ton Ref can be used to determine when to switch operations from using a switching frequency regulation function to a minimum on time override function. Thus, when the PWM Ton drops below 60 nanoseconds, as illustrated by line, controllercan switch operations to prioritize increasing the on time to be above the 60 nanosecond threshold. As shown by line, the minimum on time override function takes over and corrects the PWM Ton to be at, at least, equal to Ton Ref. Without the minimum on time override, the on-time continues at under 40 nanoseconds as shown by line. As illustrated by line, the switching frequency decreases to almost 0.6 MHz because controlleris regulating the on time instead of the switching frequency. When Vout increases back up to 1.0 V, controllercan switch operations from the minimum on time override function back to the switching frequency regulation function. This can be seen by lineincreasing back to 1 MHz and lineincreasing to a 120 nanosecond on time duration.

is a flow diagram illustrating another process to implement a switching frequency regulator and a minimum on time override function in another embodiment. Descriptions ofmay reference components shown in. The processcan include one or more operations, actions, or functions as illustrated by one or more of blocks,,,, and. Although illustrated as discrete blocks, various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, performed in different order, or performed in parallel, depending on the desired implementation.

Processcan be implemented by a voltage regulator system. For example, controllerof voltage regulator systemcan perform process. Processcan begin at block. At block, the controller can determine a pulse width modulation (PWM) on time duration being used for operating a voltage regulator. In one embodiment, the voltage regulator can be a hysteretic current mode buck regulator.

Processcan continue from blockto. At block, the controller can further determine a switching frequency being used for operating the voltage regulator. In one embodiment, the controller can determine the switching frequency by determining a PWM off time duration being used for operating the voltage regulator, summing the PWM on time and the PWM off time to determine a cycle time, and determining a reciprocal of the cycle time to determine the switching frequency.