Semiconductor device and a method of fabricating the same with increased effective width of the channel without increasing the width of the gate active region

The present disclosure relates to an integrated circuit and a method of fabricating the same, and particularly to a semiconductor device and a method of fabricating the same.

In recent years, with the development of semiconductor technology, the size of an electronic device has become smaller, and the size of a gate structure has become smaller. However, as the size of gate structure has become smaller, less current passeses through the channel below the gate structure, and thus the performance of the device is decreased. In order to maintain or improve the performance of the device, the size of the device cannot be effectively reduced, so a larger chip area must be occupied.

The disclosure provides a semiconductor device and a method of fabricating the same, in which the effective width of the channel between the source and the drain can be increased without increasing the width of the gate active region.

According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. The gate structure covers the plurality of recesses and the substrate surface between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers the bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is disposed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

According to an embodiment of the present disclosure, a method of fabricating a semiconductor device includes the following steps. A plurality of recesses are formed in the substrate. A gate structure is formed on the substrate, wherein the gate structure covers the plurality of recesses and the surface of the substrate between the plurality of recesses and the surface. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers the bottom surfaces and the sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. A gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. A first doped region and a second doped region are formed at two sides of the gate structure.

The arrangement of multiple recesses in the embodiment of the present disclosure can increase the formation of sidewall channels, so the effective width of the channel can be increased without increasing the width of the gate active region, and the current I-Iof the device can be increased. Therefore, the present disclosure can save the chip area.

andare top views of semiconductor devices according to some embodiments of the present disclosure.andare cross-sectional views of semiconductor devices of some embodiments taken along the lines I-I′ of.andare cross-sectional views of semiconductor devices of some embodiments taken along the line I-I′ of.

Referring toand, semiconductor devicesA andB of the present disclosure respectively include a substrate, an isolation structure, a gate structure, a first doped regionand a second doped region.

The isolation structureis formed in the substrateto define an active region AA. The gate structureis located in the active region AA of the substrateand extends onto the isolation structure. The first doped regionand the second doped regionare located in the active region AA of the substrateat two sides of the gate structure. The gate structure, the first dope regionand the second doped regionform a single transistor. A transistor channelis below the gate structureand between the first doped regionand the second doped region. In other words, the channelextends in a first direction D, and the gate structureextends in a second direction Ddifferent from the first direction D. For example, the first direction Dand the second direction Dare perpendicular to each other. The direction in which the recessesextend is parallel to the direction of the channel, and the direction in which the recessesare arranged is parallel to the extending direction of the gate structure. In some embodiments, the semiconductor deviceA of the present disclosure further includes first contactsand second contacts, which are respectively landed on the first doped regionand the second doped region, and are respectively electrically connected to the first doped regionand the second doped region.

The single transistor of some embodiments of the present disclosure has multiple recessesin the substrate. The recessesextend along the first direction Dand are arranged along the second direction D. The recessesare located between the first doped regionand the second doped region. The recessesand the surface of the substratebetween the recessesare partially covered by the gate structure. In other words, the extending direction of each recessis parallel to the extending direction of the channel. The length Lof the recessesin the first direction Dis greater than the length Lof the gate structurein the first direction D, so that two ends Eand Eof each recessare not covered by (or exposed by) the gate conductive layerof the gate structure.

Referring to, in some embodiments, the recessesof the semiconductor deviceA are formed in the active region AA. Referring to, in other embodiments, the inner recessesof the semiconductor deviceB are formed in the active region AA, and the outermost recessare formed in both the active region AA and the isolation structure.

Referring toand, the substrateof the present disclosure can be a bulk substrate (e.g., a bulk silicon substrate), a semiconductor-on-insulator substrate (e.g., a silicon-on-insulator substrate), or an advanced material that can provide compressive stress to the channel, or another III-V material such as GaAs. The substrateof the present disclosure may be a bulk substrate, such as the substrateof each of the semiconductor devicesA andA, as shown inand. The bulk substrate is a bulk semiconductor substrate, for example. The substrateof the present disclosure may also be a bulk substrate including a well region, a doped region, and a doped region, as shown in the substrateof each of the semiconductor devicesB andB, as shown inand. The doped regionis located between the well regionand the doped region. The doped regionmay serve as a threshold voltage adjustment layer for the channelclose to the gate structure. The doped regionmay serve as a threshold voltage adjustment layer for the channelof a bottom parasitic device. The doped regionand the doped regionmay have dopants of the same conductivity type. The conductivity type of the dopants in the well regionmay be the same as or different from the conductivity type of the dopants in the doped regionand the doped region. In other embodiments, the substrate may also be a semiconductor-on-insulator substrate.

Referring toand, in the first direction D, the recessesand the surface of the substratebetween the recessesform a concave-convex structure, as shown in the concave-convex structureof each of the semiconductor devicesA,B,A,B in,,and. In other words, there is a non-zero distance between the bottom surfaceL of each recessand the surfaceH of the substrate. That is, each recesshas a non-zero depth. In some embodiments, the distance between the bottom surfaceL of the recessand the surfaceH of the substratemay range from about 15 nm to 100 nm, for example. Inand, the bottom surfaceL of the recessextends to the top surface of the doped region. In other words, the depth of the recessis approximately the same as the thickness of the doped region. In some embodiments, the recesshas approximately the same width from the upper portion to the lower portion thereof. In other embodiments, the recesshas inclined sidewalls, so that the width of the upper portion is greater than the width of the lower portion of the recess. The inclined sidewall of the recessmay have single, double or multiple slopes. The cross section of the recesscan be, for example, U-shaped, U-shaped with a wide top and a narrow bottom, V-shaped, or bowl-shaped.

Referring to,,,,and, when the transistor of the embodiment of the present disclosure is operated, the current between the first doped regionand the second doped regioncan flow along the surface channel-of the surfaceH of the substratebetween two adjacent recesses, along the bottom surface channels-of the bottom surfacesL of the recesses, and along the sidewall channels-of the sidewalls of the recesses. In this embodiment, the surface channels-of the substrate, the bottom surface channels-of the recesses, and the sidewall channels-of the recessesare collectively referred to as a channel. Therefore, as more recessesare covered by the gate structureof each transistor, more sidewall channels-are provided. For example, in, the gate structureof each transistor covers four recesses, and two sidewalls of each recessare within the active region AA, so eight sidewall channels-are additionally provided for the gate structure of each transistor. In, the gate structureof each transistor covers five recesses, each of the three inner recesseshas two sidewalls within the active region AA, and each of the two outer recessesonly has one sidewall within the active region AA, so eight sidewall channels-are additionally provided for each transistor. Therefore, the arrangement of multiple recessesin the embodiment of the present disclosure can increase the formation of sidewall channels, and thus, the effective width of the channelcan be increased without increasing the width of the gate active region AA.

Referring to,and, the gate structureincludes a gate dielectric layerand a gate conductive layerstacked in a third direction D. The third direction Dis perpendicular to the first direction Dand the second direction D. The gate dielectric layercovers the bottom surfaces and sidewalls of the recessesand the surfaceH of the substratebetween the recesses. The gate dielectric layerdoes not completely fill the recesses. The gate dielectric layermay conformally cover the bottom surface and sidewall of each of the recessesand the surfaceH of the substratebetween two adjacent recesses. The gate conductive layeris formed on the gate dielectric layer, completely fills in (or fills up) the recessesand covers the surface of the substratebetween the recesses. The gate dielectric layerincludes silicon oxide, silicon nitride, a high dielectric constant (high-k) material or a combination thereof. The material of the gate conductive layer includes polysilicon or metal. The metal gate conductive layercan be applied to a transistor having a high-k material as the gate dielectric layer. The metal includes tantalum or titanium nitride, but the disclosure is not limited thereto.

Referring toand, in an embodiment, the recessesare formed in the active region AA, the surfaceH of the substrateat the edge of the active region AA may be flushed with the surface of the adjacent isolation structure, and higher than the bottom surfacesL of the recesses.

Referring toand, in an embodiment, the recessesare formed in the active region AA and the isolation structure, the bottom surfaceL of the recessat the edge of the active region AA may be flushed with the surface of the adjacent isolation structure, and lower than the surfaceH of the substrate.

toandtoare cross-sectional views of the semiconductor devices of some embodiments along the line II-II′ ofor.

Referring to,,and, in some embodiments, the gate structureof each of the semiconductor devicesA,B,A,B,A, andB is formed across the recesseswithout covering two ends Eand Eof each recesses. Referring to,,and, in some embodiments, each of the semiconductor devicesA,B,A,B,A andB further includes spacers. The spacersare formed on the sidewalls of the gate structure. Inand, the spacersare formed over the recessand cover the sidewalls of two ends Eand Eof each recess. Inand, the spacersare formed over the recess, and cover the sidewalls of two ends Eand Eof each recessand the surfaceH of the substrate.

toare cross-sectional views of semiconductor devices of some embodiments taken along line III-III′ ofor.

Referring toto, in some embodiments, in each of the semiconductor devicesA andB, the surfaceH of the substratebetween the recessescovered by the gate structureand the spacersis flushed with the surfaceH of the substratenot covered by the gate structure.

Referring toto,toandto, in some embodiments, in each of the semiconductor devicesA,B,A,B,A, andB, parts of the first doped regionand the second doped regionoutside of the recessesare raised from (or protrude from) the bottom surfaces of the recesses, and therefore, the parts of the first doped regionand the second doped regionoutside of the recessesare referred to as raised parts (or protrusions) of the first doped regionand the second doped region. In other words, the first doped regionand the second doped regioncan also be referred to as the first raised doped regionand the second raised doped region. In addition, channel stress materials can be embedded in the first doped regionand the second doped regionto increase the saturation current Iof the device. For example, for an NMOS transistor, silicon carbide (SiC) can be embedded in the first doped regionand the second doped region. For a PMOS transistor, silicon germanium (SiGe) can be embedded in the first doped regionand the second doped region.

Referring toto,to, andto, in some embodiments, each of the semiconductor devicesA,B,A,B,A, andB may further include lightly doped drain regionsand, respectively between the first doped regionand the gate structureand between the second doped regionand the gate structure. The lightly doped drain regionsandare referred to as lightly doped regions in some examples.

toare cross-sectional views of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Referring to, a substrateis provided. The substratemay be a semiconductor substrate, such as a silicon substrate. Next, an isolation structureis formed in the substrate. The isolation structureis a shallow trench isolation structure, for example. The material of the isolation structureincludes silicon oxide, silicon nitride or a combination thereof. The isolation structurehas sidewalls perpendicular to the surface of the substrate, or has inclined sidewalls.

After that, multiple ion implantation processes are performed, so as to form a well region′, a doped region′ and a doped region′ in the substrate. A sacrificial layer (not shown) may be formed on the substratebefore performing the ion implantation processes, and the sacrificial layer is removed after the formation of the well region′, the doped region′ and the doped region′. The sacrificial layer includes screen oxide, for example.

Referring to, a mask layeris formed over the substrate. The mask layeris patterned through a lithography process to form multiple openings OP. The mask layerincludes a photoresist layer. Next, an etching process is performed to form multiple recessesin the substrate. The etching process for forming the recessesmay be a single etching process or multiple etching processes. The etching process includes an anisotropic etching process, an isotropic etching process or a combination thereof. Each recesshas sidewalls perpendicular to the surface of the substrate, e.g., having approximately the same width from the upper portion to the lower portion of the recess. Alternatively, the recesshas inclined sidewalls. For example, the width of the upper portion is greater than the width of the lower portion of the recess. The inclined sidewalls of the recessmay have single, double or multiple slopes. The cross section of the recesscan be, for example, U-shaped, U-shaped with a wide top and a narrow bottom, V-shaped, or bowl-shaped.

Referring to, the mask layeris removed to expose the surfaceH of the substrateand the bottom surfacesL of the recesses. The mask layercan be stripped by a dry process such as oxygen plasma, or removed by a wet process.

Referring to,,and, a gate structureis formed on the substrate. The gate structureincludes a gate dielectric layerand a gate conductive layer. The method of forming the gate dielectric layerand the gate conductive layerincludes forming a gate dielectric material and a gate conductive material on the substrate, and then performing lithography etching processes to pattern the gate dielectric material and the gate conductive material. The material of the gate dielectric layerincludes silicon oxide, silicon nitride and a high-k material formed by, for example, a thermal oxidation process. The high-k material includes metal oxide, such as ZrO, GdO, HfO, BaTiO, AlO, LaO, TiO, TaO, YOor a combination thereof. The gate conductive layerincludes polysilicon, doped polysilicon, tantalum, titanium nitride or a combination thereof.

Referring to,,and, an ion implantation process is performed to form lightly doped drain regionsandin the substrateat two sides of the gate structure. Thereafter, spacersare formed on sidewalls of the gate structure. Then, an ion implantation process and a thermal annealing process are performed to form a first doped regionand a second doped regionin the substrate. One of the first doped regionand the second doped regionis a source region. The other of the first doped regionand the second doped regionis a drain region. During the thermal oxidation process of forming the gate dielectric layer, the dopants in the well region′ and the doped regions′ and′ may be activated to form the well regionand the doped regionsand. In some embodiments, after the lightly doped drain regionsandare formed, an annealing process may be performed. During the annealing process, the dopants in the well region′ and the doped regions′ and′ may be activated to form the well regionand the doped regionsand

In the above embodiments, the isolation structureis formed before the gate structureis formed. However, in other embodiments, the isolation structuremay be formed after the gate dielectric material and the gate conductive material are formed, as shown into.

toare cross-sectional views of the manufacturing process of semiconductor devices according to other embodiments of the present disclosure.

Referring to, a well region′, a doped region′, and a doped region′ are formed in a substrateaccording to the method described above. It should be noted that in this embodiment, the isolation structureis not formed before the formation of the well region′, the doped region′ and the doped region′, but is formed later.

Referring to, before forming a mask layer, a hard mask layeris formed on the substrate. The hard mask layerincludes silicon nitride, silicon oxide or a combination thereof. After that, the mask layeris formed on the hard mask layer. The mask layeris patterned through a lithography process to form multiple openings OP.

Referring to, an etching process is performed to transfer patterns of the openings OPof the mask layerto the hard mask layerand then to the substrate, so as to form multiple recesses. The etching process is an anisotropic etching process, for example.

Referring to, the mask layerand the hard mask layerare removed, so as to expose the surfaceH of the substrateand the bottom surfacesL of the recesses.

Referring to, after forming the gate dielectric material and the gate conductive material, an isolation structureis formed in the substrate. Afterwards, the lithography and etching processes are performed to pattern the gate dielectric material and the gate conductive material to form a gate dielectric layerand a gate conductive layerof the gate structure, as shown in,and.

Afterwards, lightly doped drain regionsand, spacers, a first doped regionand a second doped regionare formed according to the method described in the above embodiments, and the dopants in the well region′ and the doped regions′ and′ are activated to form the well regionand the doped regionsand, as shown in,,,,and.

The semiconductor device of the present disclosure can be applied to not only a high-voltage device, but also a low-voltage device. The transistor of the present disclosure may be an N-type MOS transistor, or a P-type MOS transistor.

The arrangement of multiple recesses in the embodiment of the present disclosure can increase the formation of sidewall channels, so the effective width of the channel can be increased without increasing the width of the gate active region, and the current I-Iof the device can be increased. Therefore, the present disclosure can save the chip area.

Although the disclosure has been disclosed as above with embodiments, they are not intended to limit the disclosure. People with ordinary skills in the art can make some changes and modifications without departing from the spirit of the disclosure, so the scope of the disclosure shall be defined by the following claims.