Circuitry arrangement in a floorplan of a memory device

The present technology relates to memory devices and, more particularly, to a circuitry arrangement in the floorplan of a memory device.

Semiconductor memory is widely used in various electronic devices, such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power, e.g., a battery.

In such semiconductor memory devices, a chip includes a complimentary metal-oxide-semiconductor (CMOS) layer with circuitry that operates the chip. Such circuitry includes sense amplifiers, page buffers, charge pumps, etc. for both programming and reading a plurality of memory cells that are arranged in an array. In some chips, the circuitry is arranged in such a way that certain circuitry components that must communicate with one another are separated from one another by obstacles, thereby necessitating peripheral metal routing around these obstacles to establish electrical communication between such components. In addition to increasing cost, this peripheral metal routing also increases chip size, which reduces memory density.

One aspect of the present disclosure is related to a memory device that includes a die with a plurality of planes including a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

According to another aspect of the present disclosure, the first set of planes includes two planes and the second set of planes includes two planes.

According to yet another aspect of the present disclosure, the planes of the first set of planes are centrally located within the CMOS layer of the die in the first direction.

According to still another aspect of the present disclosure, the planes of the second set of planes are located on opposite sides of the first set of planes in the first direction.

According to a further aspect of the present disclosure, the at least one common peripheral circuitry area includes two common peripheral circuitry areas that are located on opposite sides of the planes of the first set of planes in the second direction.

According to yet a further aspect of the present disclosure, the two common peripheral circuitry areas have different sizes from one another.

According to still a further aspect of the present disclosure, each plane further includes a sense amplifier area in the CMOS layer of the die.

According to another aspect of the present disclosure, the planes of the first set of planes are oriented relative to one another such that the sense amplifier areas of the planes of the first set of planes are immediately adjacent one another and the non-common peripheral circuitry areas of the planes of the first set of planes are immediately adjacent the two common peripheral circuitry areas.

According to yet another aspect of the present disclosure, each plane further includes at least two sets of word line hook-up areas. The word line hook-up areas of the planes of the first set of planes are spaced from opposite ends of the planes of the first set of planes in the first direction such that the non-common peripheral circuitry areas of the planes of the first set of planes are immediately adjacent the non-common peripheral circuitry areas of the planes of the second set of planes.

According to still another aspect of the present disclosure, the planes of the first set of planes are differently sized than the planes of the second set of planes.

According to a further aspect of the present disclosure, the CMOS layer is located either vertically above or vertically below an array of memory cells of the plurality of planes.

Another aspect of the present disclosure is related to an apparatus that includes a memory device. The memory device includes a plurality of planes, each of which includes a plurality of memory blocks with memory cells. The memory device includes a CMOS layer that underlies or overlies the memory blocks. In the CMOS layer, each of the planes has a sense amplifier area and a non-common peripheral circuitry area. The CMOS layer further includes at least two common peripheral circuitry areas. The planes are oriented such that in the CMOS layer, each non-common peripheral circuitry areas is immediately adjacent the at least one of the common peripheral circuitry areas.

According to another aspect of the present disclosure, the plurality of planes includes a first set of planes and a second set of planes. The planes of the first set of planes are oriented in a first direction and the planes of the second set of planes are oriented in second direction that is transverse to the first direction.

According to yet another aspect of the present disclosure, the planes of the second set of planes are located on opposite sides of the planes of the first set of planes in the first direction.

According to still another aspect of the present disclosure, the common peripheral circuitry areas are located on opposite sides of the planes of the first set of planes in the second direction.

According to a further aspect of the present disclosure, each of the planes further includes a sense amplifier area in the CMOS layer of the memory device. The planes of the first set of planes are oriented such that the sense amplifiers of the planes of the first set of planes are immediately adjacent one another.

According to yet a further aspect of the present disclosure, the planes of the first set of planes are differently sized than the planes of the second set of planes.

Yet another aspect of the present disclosure is related to a memory device that includes a plurality of planes. Each plane including a plurality of memory blocks with memory cells. The memory device further includes a CMOS layer that underlies or overlies the memory blocks. In the CMOS layer, the memory device includes a common input/output means for communicating with a controller. Each of the planes has a peripheral circuitry area and a sense amplifier area. The planes are arranged such that in the CMOS layer, the peripheral circuitry areas of the plurality of planes are electrically connected with one another and with the input/output means without contacts that run above or below the sense amplifier areas.

According to another aspect of the present disclosure, the plurality of planes includes a first set of planes that have major dimensions that extend in a first direction and a second set of planes that include major dimensions that extend in a second direction that is transverse to the first direction.

According to yet another aspect of the present disclosure, the planes of the first set of planes are larger than the planes of the second set of planes.

According to the present disclosure, the peripheral circuitry and sense amplifiers in a plurality of planes are arranged in a CMOS layer of a chip according to a floor plan such that there is less wiring blockage between components that communicate with one another during operation of the memory device. This unique arrangement reduces a number of metal layers in the chip and manufacturing costs as compared to other known chip designs and also allows for chip size optimization. More specifically, in certain arrangements of the exemplary embodiments of the present disclosure, the planes of a die are rotated relative to one another such that their major dimensions extend in different directions. Within the die, this arrangement allows for more direct communication between the components of common peripheral circuitry areas of the die and the components of non-common peripheral circuitry areas of each of the planes. This more direct communication not only improves performance of the die but reduces cost and improves manufacturability of the die by eliminating certain metal contacts that extend around obstacles in other known chip designs. This floor plan is discussed in further detail below.

is a block diagram of an example memory device that includes a die with a CMOS constructed with the floor plan summarized above and discussed in further detail below. The memory devicemay include one or more memory die. The memory dieincludes a memory structureof memory cells, such as an array of memory cells, control circuitry, and read/write circuits. The memory structureis addressable by word lines via a row decoderand by bit lines via a column decoder. The read/write circuitsinclude multiple sense blocks SB, SB, . . . SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically, a controlleris included in the same memory device(e.g., a removable storage card) as the one or more memory die. Commands and data are transferred between the hostand controllervia a data bus, and between the controller and the one or more memory dievia lines.

The memory structurecan be two-dimensional or three-dimensional. The memory structuremay comprise one or more array of memory cells including a three-dimensional array. The memory structuremay comprise a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structuremay comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structuremay be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

The control circuitrycooperates with the read/write circuitsto perform memory operations on the memory structure, and includes a state machine, an on-chip address decoder, and a power control module. The state machineprovides chip-level control of memory operations.

A storage regionmay, for example, be provided for programming parameters. The programming parameters may include a program voltage, a program voltage bias, position parameters indicating positions of memory cells, contact line connector thickness parameters, a verify voltage, and/or the like. The position parameters may indicate a position of a memory cell within the entire array of NAND strings, a position of a memory cell as being within a particular NAND string group, a position of a memory cell on a particular plane, and/or the like. The contact line connector thickness parameters may indicate a thickness of a contact line connector, a substrate or material that the contact line connector is comprised of, and/or the like.

The on-chip address decoderprovides an address interface between that used by the host or a memory controller to the hardware address used by the decodersand. The power control modulecontrols the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. The sense blocks can include bit line drivers, in one approach. An SGS transistor is a select gate transistor at a source end of a NAND string, and an SGD transistor is a select gate transistor at a drain end of a NAND string.

In some embodiments, some of the components can be combined. In various designs, one or more of the components (alone or in combination), other than memory structure, can be thought of as at least one control circuit which is configured to perform the actions described herein. For example, a control circuit may include any one of, or a combination of, control circuitry, state machine, decoders/, power control module, sense blocks SB, SB, . . . , SBp, read/write circuits, controller, and so forth.

The control circuits can include a programming circuit configured to perform a program and verify operation for one set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state among a plurality of data states and memory cells assigned to represent another data state among the plurality of data states; the program and verify operation comprising a plurality of program and verify iterations; and in each program and verify iteration, the programming circuit performs programming for the one selected word line after which the programming circuit applies a verification signal to the selected word line. The control circuits can also include a counting circuit configured to obtain a count of memory cells which pass a verify test for the one data state. The control circuits can also include a determination circuit configured to determine, based on an amount by which the count exceeds a threshold, if a programming operation is completed.

For example,is a block diagram of an example control circuitwhich comprises a programming circuit, a counting circuit, and a determination circuit.

The off-chip controllermay comprise a processor, storage devices (memory) such as ROMand RAMand an error-correction code (ECC) engine.

The storage device(s),comprise, code such as a set of instructions, and the processoris operable to execute the set of instructions to provide the functionality described herein. Alternately or additionally, the processorcan access code from a storage deviceof the memory structure, such as a reserved area of memory cells in one or more word lines. For example, code can be used by the controllerto access the memory structuresuch as for programming, read and erase operations. The code can include boot code and control code (e.g., set of instructions). The boot code is software that initializes the controllerduring a booting or startup process and enables the controllerto access the memory structure. The code can be used by the controllerto control one or more memory structures. Upon being powered up, the processorfetches the boot code from the ROMor storage devicefor execution, and the boot code initializes the system components and loads the control code into the RAM. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

Generally, the control code can include instructions to perform the functions described herein including the steps of the flowcharts discussed further below and provide the voltage waveforms including those discussed further below.

In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor readable storage devices (RAM, ROM, flash memory, hard disk drive, solid state memory) that store processor readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input/output interfaces and/or one or more input/output devices in communication with the one or more processors.

Other types of non-volatile memory in addition to NAND flash memory can also be used.

Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse or phase change material, and optionally a steering element, such as a diode or transistor. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors comprising memory cells and SG transistors.

A NAND memory array may be configured so that the array is composed of multiple memory strings in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are examples, and memory elements may be otherwise configured. The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-y direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate may be a wafer over or in which the layer of the memory elements is formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

A three-dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z-direction is substantially perpendicular and the x- and y-directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

By way of non-limiting example, in a three-dimensional array of NAND strings, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-y) memory device level. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three-dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between memory device levels.

Then again, two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.

illustrates blocks,of memory cells in an example two-dimensional configuration of the memory arrayof. The memory arraycan include many such blocks,. Each example block,includes a number of NAND strings and respective bit lines, e.g., BL, BL, . . . which are shared among the blocks. Each NAND string is connected at one end to a drain-side select gate (SGD), and the control gates of the drain select gates are connected via a common SGD line. The NAND strings are connected at their other end to a source-side select gate (SGS) which, in turn, is connected to a common source line. One hundred and twelve word lines, for example, WL-WL, extend between the SGSs and the SGDs. In some embodiments, the memory block may include more or fewer than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines, which contain no user data, can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can shield the edge data word line from certain edge effects.

One type of non-volatile memory which may be provided in the memory array is a floating gate memory, such as of the type shown in. However, other types of non-volatile memory can also be used. As discussed in further detail below, in another example shown in, a charge-trapping memory cell uses a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.