Interpolation amplifier and source driver comprising the same

This application claims priority to Korean Patent Application No. 10-2023-0122887 (filed on Sep. 15, 2023), which is hereby incorporated by reference in its entirety.

The present disclosure generally relates to an interpolation amplifier and a source driver including the same.

In display devices, a source driver that drives a display panel provides a pixel voltage to a panel load connected to a source line, and a scan signal is provided to a gate driver to display an image on the display panel. The source driver provides pixel voltages, which correspond to digital image data provided by a timing controller, to pixels included in the display panel through lines to form an image on the display panel.

As display technology advances, resolution continues to increase. Furthermore, pixel voltages provided to pixels are becoming increasingly denser to form better quality images. In order to generate and provide these voltages to pixels, an amplifier interpolates and generates the voltages. However, since conventional interpolation amplifiers had nonlinear characteristics, an interpolation amplifier and a source driver capable of resolving the nonlinear characteristics were required.

The present disclosure is directed to providing an interpolation amplifier capable of alleviating the nonlinear characteristics, and a source driver including the interpolation amplifier.

According to an aspect of the present disclosure, there is provided an interpolation amplifier including an input stage, a load stage, and an output stage, wherein the input stage includes a plurality of connection source modules to which an input signal with a plurality of bits is provided, the connection source modules each include a first differential pair and a second differential pair to which an input voltage is input and an output voltage of the interpolation amplifier is fed back and input, a first current source connected to the first differential pair to provide a bias current, and a second current source connected to the second differential pair to provide a bias current, sources of the first differential pairs included in two or more of the connection source modules are connected to each other, and sources of the second differential pairs included in two or more of the connection source modules are connected to each other.

According to another aspect of the present invention, there is provided an interpolation amplifier for outputting a voltage corresponding to an input signal with a plurality of bits, the interpolation amplifier including an input stage including a plurality of unit modules configured to receive one bit of the plurality of bits of the input signal and generate a current corresponding to the bit, a load stage configured to generate a voltage corresponding to the current output by the input stage, and an output stage configured to output the voltage generated by the load stage, wherein an output voltage generated in the output stage is fed back and input to the input stage, and the input stage includes the number of unit modules corresponding to the number of bits of the input signal.

According to still another aspect of the present disclosure, there is provided a source driver for driving a plurality of pixels included in a display panel, the source driver including an interpolation amplifier configured to output a voltage corresponding to an input signal with a plurality of bits, wherein the interpolation amplifier includes an input stage including a plurality of unit modules configured to receive one bit of the plurality of bits of the input signal and generate a current corresponding to the bit, a load stage configured to generate a voltage corresponding to the current output by the input stage, and an output stage configured to output the voltage generated by the load stage, wherein an output voltage generated in the output stage is fed back and input to the input stage, and the input stage includes the number of unit modules corresponding to the number of bits of the input signal.

According to the present embodiment, there are provided a source driver and an interpolation amplifier including an input stage with improved nonlinearity.

Hereinafter a source driver and a display device according to the present embodiment will be described with reference to the accompanying drawings.is a schematic view illustrating a display system. Referring to, a display system according to the present embodiment includes a display panel, a gate driver, source drivers,, . . . , and, and a timing controller that changes the characteristics of a screen source applied from the outside or adjusts a driving timing according to the resolution and characteristics of the display system. According to the characteristics of the display panel, the timing controller and the source drivers,, . . . , andmay be formed as separate chips, and as shown in the illustrated drawing, the timing controller and the source drivers,, . . . , andmay be implemented as one chip.

The display panel includes a plurality of pixels Tand T, and each pixel is connected to the gate driver through gate lines gand is electrically connected to the source drivers,, . . . , andthrough source lines s. The source line transmits to each pixel a grayscale signal that should be displayed by the pixel.

The source line sup to the pixel consists of a conductive line, and there are a resistive component of the conductive line and various parasitic capacitances such as parasitic capacitance between adjacent lines and parasitic capacitance with a reference electrode. Such loads and switches such as thin film transistors in the pixels may be modeled as resistor-capacitor pairs (RC pairs). That is, a load which should be driven by the source driver has a configuration of the form of a distributed resistance-capacitance (distributed RC).

is a block diagram illustrating a path through which pixel data is provided to a display panel. Referring to, a signal provided to the display panel is provided to pixels of the display panel through a shift register, a data latch, a sample/hold register (S/H register), a gate driver circuit, a digital-to-analog converter (DAC), and an interpolation amplifier.

The shift register sequentially shifts and outputs input start pulses SP. The data latch latches up and provides image data. In one embodiment, there may be provided the S/H register that samples a latched-up image signal according to the start pulse SP and holds and provides sampled data.

A decoder, for example, receives a plurality of gamma voltages and pixel data, selects a high voltage VH and a low voltage VL corresponding to the pixel data from the gamma voltages, and outputs the selected voltage to the interpolation amplifier. The interpolation amplifierreceives a voltage between the high voltage VH and the low voltage VL and pixel data D[n−1, 0], interpolates the voltage between the high voltage VH and the low voltage VL to correspond to the provided pixel data D[n−1, 0], and outputs the interpolated voltage Vout.

is a block diagram illustrating an outline of an interpolation amplifieraccording to the present embodiment.are schematic block diagrams illustrating an input stage. Referring to, the interpolation amplifierincludes an input selection unitand an amplifier. The amplifiermay include an input stage, a load stage, and an output stage.

The input selection unitreceives 4-bit pixel data D[3,0] and generates and outputs n input voltages IN_0, IN_1, . . . , and IN_3 corresponding to the pixel data, and one voltage IN_DC to the input stage. Table 1 below is a table showing the provided 4-bit pixel data D[3,0] and five input voltages that are output.

As shown inand Table 1 below, the input selection unitmay be a logic circuit that receives a high voltage VH and a low voltage VL and outputs 4-bit input signals IN_3, IN_2, IN_1, and IN_0 and the voltage IN_DC according to pixel data D[n−1, 0]. In the example shown in Table 1, the input selection unitoutputs the low voltage VL at a kbit IN_K−1 of an input signal when a kbit of the pixel data D[n−1, 0] is logic high and outputs the high voltage VH at a kbit of the input signal when the kbit of the pixel data is logic low.

In the shown embodiment, when pixel data D[3:0] is 0001, the signals IN_3, IN_2, IN_1, and IN_0 output by the input selection unitmay have voltages VH, VH, VH, VH, and VL, and the signal IN_DC may have the high voltage VH. As shown, the high voltage VH may be output as the signal IN_DC irrespective of the pixel data D[n−1,0]. As the signal IN_DC, the high voltage VH is always output to allow a current required for operation of the load stageand the output stageto flow.

are block diagrams illustrating an outline of the input stageaccording to the present embodiment. The input stage generates currents corresponding to input signals IN_3, IN_2, IN_1, and IN_0 and outputs the generated currents to the load stage(see). The input stageconverts the provided input voltage signals IN_3, IN_2, IN_1, and IN_0 into corresponding currents and outputs the currents. The input stagemay include a plurality of unit modulesthat output a current corresponding to a provided input signal.

illustrates an example in which the input stageis implemented as the unit modulesto which a signal is input and which output a current corresponding to the signal. As described below, the unit modulemay be implemented to include a connection source module(see). In another example, the unit modulemay be implemented to include a separate source module(see). In still another example, the unit modulemay be implemented to include the connection source module(see) and the separate source module(see).

In the illustrated embodiment, IN_0 corresponds to D[0] of D[3:0], IN_1 corresponds to D[1], IN_2 corresponds to D[2], and IN_3 corresponds to D[3]. An input provided for each site is a value that is twice a value of a previous site. For example, when a value of IN_j is 1 and a value of IN_j+1 is 1, a value of IN_j+1 is twice a value of IN_j at a previous site. Therefore, a magnitude of a current output when IN_j which is a jinput is provided is twice a magnitude of a current output when IN_j−1 which is a j−1input is provided.

Referring to, when the unit moduleis formed using transistors having the same channel area, the number of unit modulesto which the input IN_j+1 is provided may be twice the number of unit modulesto which the input IN_j is provided. In addition, the number of unit modulesto which the input IN_j is provided may be 2j.

In one embodiment, IN_DC may have the high voltage VH irrespective of pixel data D[n−1,0], and the number of unit modules to which IN_DC is input may be one.

In the embodiment shown in, the number of unit modulesto which each bit of an input signal is input may be the same, and a channel area of the transistor included in the unit moduleto which each bit of an input signal IN_j+1 is input may differ by two times from those included in the unit moduleto which each bit of an input signal IN_j is input. By forming the unit modules, magnitudes of currents corresponding to adjacent bits of an input signal may be made to differ by a factor of 2.

is an exemplary circuit diagram of an input stageincluding two unit modules.illustrates an embodiment in which the input stageis implemented as the unit modules each including a connection source moduleand a separate source module. Referring to, the connection source moduleincludes two or more connection source modulesandincluding a first differential pairand a second differential pair, to which an input voltage IN_k is input and an output voltage VFB of an interpolation amplifier is fed back and input, a first current source connected to the first differential pairto provide a bias current, and a second current source connected to the second differential pair to provide a bias current. Sources of first differential pairsandincluded in the two or more connection source modulesandare connected to each other as shown in a bold line, and sources S of second differential pairsandincluded in the two or more connection source modulesandare connected to each other as shown in a bold line.

In an example that is not shown, even when an input stage includes three or more connection source modules, sources of transistors included in first differential pairs are connected to each other, and sources of transistors included in second differential pairs are connected to each other.

In one embodiment, in the first differential pairand the first differential pairincluded in the first connection source moduleand the second connection source module, outputs of transistors to which input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which a fed-back output voltage VFB is provided are connected to each other.

In addition, in the second differential pairand the second differential pair, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other.

In an example that is not shown, when an input stage includes n connection source modules, in each of first differential pairs, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other. In addition, in each of second differential pairs, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other.

In one embodiment, the input stagemay include a plurality of separate source modulesand. The separate source modulesandinclude a third differential pairto which the input signal IN_k is input and the output voltage VFB of the interpolation amplifier is fed back and input and of which sources are connected each other, a fourth differential pairto which the input signal IN_k+1 is input and the output voltage VFB of the interpolation amplifier is fed back and input, and of which sources are connected to each other, a third current source connected to the third differential pairto provide a bias current, and a fourth current source connected to the fourth differential pairto provide a bias current. In two or more separate source modulesand, a source of a third differential pairincluded in one separate source moduleis not electrically connected to a source of a third differential pairincluded in the other separate source module, and in the two or more separate source modules, a source of a fourth differential pairincluded in one separate source moduleis not connected to a source of a fourth differential pairincluded in the other separate source module

In one embodiment, in the third differential pairand the third differential pairincluded in a first separate source moduleand a second separate source module, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other.

In addition, in the fourth differential pairand the fourth differential pair, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other.

In one embodiment, in the first differential pair, the first differential pair, the third differential pair, and the third differential pair, outputs of the transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other and input to a load stage, and outputs of the transistors to which the fed-back output voltage VFB is applied are connected to each other and input to the load stage.

In addition, in the second differential pair, the second differential pair, the fourth differential pair, and the fourth differential pair, the outputs of the transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other and input to the load stage, and the outputs of the transistors to which the fed-back output voltage VFB is provided are connected to each other and input to the load stage.

In the illustrated embodiment, the first differential pairand the third differential pairare respectively connected to the first current source and the third current source to receive a bias current, and the second differential pairand the fourth differential pairare respectively connected to the third current source and the fourth current source to receive a bias current.

In the illustrated embodiment, the first current source and the third current source are each illustrated as serially connected transistors having gate electrodes to which a bias voltage Vbiasis provided. However, this is merely an embodiment, and the first current source and the third current source may each be a single transistor or one branch of a current mirror to which a bias voltage is provided.

In the illustrated embodiment, the second current source and the fourth current source are each illustrated as serially connected transistors having gate electrodes to which the bias voltage Vbiasis provided. However, this is merely an embodiment, and the second current source and the fourth current source may each be a single transistor or one branch of a current mirror to which a bias voltage is provided.

For convenience of illustration and description, in the embodiment shown in, one first connection source moduleand one first separate source moduleto which the input signal IN_K is provided are shown, and one second connection source moduleand one second separate source moduleto which the input signal IN_K+1 is provided are shown. As shown in, the present embodiment relates to a case in which a channel area of modules to which the input signal IN_K+1 is provided is twice a channel area of modules to which the input signal IN_K is provided. However, according to an embodiment that is not shown, the number of second connection source modulesmay be twice the number of first connection source modules, and the number of second separate source modulesmay be twice the number of first separate source modules

In the embodiment shown in, when the input signal IN_k applied to the first differential pair, the second differential pair, the third differential pair, and the fourth differential pairis a low voltage VL, n-type metal oxide semiconductor (NMOS) transistors of the second differential pairand the fourth differential pairto which the input signal IN_k is applied are turned off, but p-type metal oxide semiconductor (PMOS) transistors of the first differential pairand the third differential pairto which the input signal IN_k is applied are turned on. Therefore, a current provided from the current source is provided to the load stage(see) through a drain electrode, which is an output node, to generate a corresponding voltage.

In addition, when the input signal IN_k+1 applied to the first differential pair, the second differential pair, the third differential pair, and the fourth differential pairis a low voltage VL, NMOS transistors of the second differential pairand the fourth differential pairto which the input signal IN_k+1 is applied are turned off, but PMOS transistors of the first differential pairand the third differential pairto which an input is applied are turned on. A current supplied from the current source is provided to the load stage through a drain electrode which is an output node. A case in which the input signal IN_k+1 is the low voltage VL has been described, but in a case in which the input signal IN_k+1 is the high voltage VH, the second and fourth differential pairs to which an input is provided are turned on, and a current is provided to the load stage to generate a corresponding voltage.

A voltage generated in the load stage(see) corresponds to a voltage generated by overlapping a voltage generated by a current output from the first connection source moduleand the first separate source modulewith a voltage generated by a current output from the second connection source moduleand the second separate source module

is a schematic circuit diagram of a load stageand an output stage. Referring to, the load stageincludes a folded cascode circuitof an NMOS transistor, a folded cascode circuitof a PMOS transistor, and current sourcesconnected between the folded cascode circuitof the PMOS transistor and the folded cascode circuitof the NMOS transistor and connected to each other in parallel.

The NMOS folded cascode circuitincludes a first paired gate circuitincluding transistors of which gates are connected and a second paired gate circuitincluding transistors of which gates are connected. The first paired gate circuitand the second paired gate circuitare connected through a cascode. In the first paired gate circuit, a node to which the gate is connected is connected to a drain electrode of the transistor of the second paired gate circuit.

The PMOS folded cascode circuitincludes a third paired gate circuitincluding transistors of which gates are connected and a fourth paired gate circuitincluding transistors of which gates are connected. The third paired gate circuitand the fourth paired gate circuitare connected through a cascode. In the third paired gate circuit, a node to which the gate is connected is connected to a drain electrode of the transistor of the fourth paired gate circuit.

In a first differential pair, a first differential pair, a third differential pair, and a third differential pair, an output current of transistors to which input signals IN_k and IN_k+1 are provided is input to an x node of the load stage, and an output current of transistors to which a fed-back output voltage VFB is provided is input to a y node of the load stageand converted into a corresponding voltage.

In addition, in a second differential pair, a second differential pair, a fourth differential pair, and a fourth differential pair, outputs of transistors to which the input signals IN_k and IN_k+1 are provided are connected to each other and input to an a node of the load stage, and outputs of transistors to which the fed-back output voltage VFB is provided are connected to each other and input to a b node of the load stageand converted into a corresponding voltage.

A converted voltage output from the load stageis provided to the output stagethrough a coupling capacitor. In the illustrated embodiment, the output stageincludes a push-pull amplifier including a PMOS transistor and an NMOS transistor. However, in other embodiments that are not shown, the output stage may be implemented as other power amplifier circuits. Accordingly, a current output from the input stageis converted into a voltage in the load stage, and an amplified output voltage from the output stage is fed back and provided to the input stage.

Simulation Results