Signal receiver, data receiver and data latch thereof

The present invention generally relates to a signal receiver, a data receiver and a data latch thereof, and more particularly to the signal receiver which can meet JEDEC (Solid State Technology Association) standard.

Since a decision feedback equalization (DFE) structure has been added into a circuit structure of double data rate fifth-generation synchronous dynamic random-access memory (DDR5 DRAM). For solving problem for a refection effect of a system, according to the JEDEC specification, the DFE structure should be applied in a strobe signal generator of the signal receiver. Such as that, a propagation delay between the data receiver a data strobe signal receiver is made large, and the data signal received by the data receiver should be a small signal. Such as that, a conventional circuit structure of a signal receiver of DRAM cannot match a requirement of the specification of JEDEC for DDR5. A new circuit structure for the signal receiver should be provided.

The present invention provides a signal receiver can be applied to a dynamic random access memory (DRAM) device. The signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. The plurality of current mode logic circuits are coupled in series, wherein a first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches are coupled to the final stage current mode logic circuit to receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

The data latch can be applied to a data receiver of a DRAM device. The data latch includes a first latch circuit, a differential pair, a current source, a plurality of first DFE summers, a plurality of second DFE summers and a second latch circuit. The differential pair has a first differential end and a second differential end respectively coupled to two ends of the first latch circuit, wherein the differential pair receives a first signal and a second signal, and the first signal and the second signal are a differential signal pair. The current source is coupled to a common end of the differential pair, and draws a common current from the common end according to a first bias voltage. The first DFE summers are coupled to the first differential end, and draw a first bias current from the first differential end according to the plurality of feedback data. The second DFE summers are coupled to the second differential end, and draw a second bias current from the second differential end according to the plurality of feedback data. The second latch circuit is coupled to two inverted ends of the first latch circuit, and obtains the corresponding output data according to two inverted output signals on the two inverted ends.

The data receiver can be applied to a DRAM device. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches as mentioned above. The current mode logic circuits are coupled in series, wherein a first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The data latches are coupled to the final stage current mode logic circuit to receive the amplified data signal. Each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals.

In summary, the data receiver of present disclosure includes a plurality of current mode logic (CML) circuits to amplify data signal to meet a data input swing request for JEDEC. Furthermore, the data receiver can improve a maximum time difference between a data request signal and the data signal (tRX_DQS2DQ) by increasing a propagation delay of the data signal.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

Reference will now be made in detail to the present preferred embodiment of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Please refer to, which illustrates a schematic diagram of a signal receiver according to an embodiment of present disclosure. The signal receiverincludes data (DQ) receiver, a data strobe signal (DQS) receiver and a signal tree. The DQ receiverincludes a plurality of current mode logic (CML) circuits-˜-, a plurality of data latches˜and a decision feedback equalization (DFE) controller. The CML circuits-˜-are coupled in series. The first stage CML circuit-in receives the data signal DQ by a first input end, and receives a reference data signal VREFDQ by a second input end. The CML circuits-to-amplify the data signal DQ stage by stage, and the last stage CML circuit-may generate amplified data signals DOand DO, wherein the amplified data signal DOis inverted to the amplified data signal DO. The data latchestoare coupled in parallel and receive the amplified data signals DOand DOcommonly. The data latchestorespectively receive latch signals Cto C, and each of the data latches sums the amplified data signals DOand DOand a plurality of feedback data to obtain a summing data. Each of the data latchestofurther latches the corresponding summing data to output each of output data DO-DOaccording to each of the latch signals Cto C. In this embodiment, phases of the latch signals Cto Care different, the latch signals Cand Chave a phase difference of 90 degree; the latch signals Cand Chave a phase difference of 90 degree; and the latch signals Cand Chave a phase difference of 90 degree.

Each of the feedback data are generated by each of the output data DO-DO. In detail, take the data latchas an example, the output data DOof the data latchmay be feedback to the data latchestoto be the feedback data of the data latchesto. The data latchalso receives the output data DOto DOto be the feedback data thereof.

In present disclosure, each of the CML circuits-˜-may be formed by a differential pair, resistors and at least one current source. The first stage CML circuit-may be a continuous time linear equalizer (CTLE) for compensating a low pass channel effect. The middle stage CML circuit-may be coupled to the DFE controller, and an amplify gain of the middle stage CML circuit-may be adjusted by a gain tuning signal GTS provided by the DFE controller. In this embodiment, the DFE controllermay receive a setting code MCS, and generates the gain tuning signal GTS according to the setting code MCS. The setting code MCS can be provided by an external electronic device, and may be pre-stored in a storage device in advanced. Furthermore, the setting code MCS may be dynamic adjusted by necessary. Moreover, an amplify gain of the final stage CML circuit-may be fixed.

Please be noted here, the CML circuits-˜-form an amplify string to amplify the data signal DQ for generating the amplified data signals DOand DO. Such as that, a voltage swing of the data signal DQ can be minimized, and a specification of JEDEC for a minimum swing requirement of inputted data signal can be met. On the other hand, the amplify string also provides a propagation delay for transmitting the data signal DQ, and a maximum time difference between the data strobe signal DQS and the data signal DQ may be improved.

In other embodiment, a stage number of the CML circuits in the amplify string can be adjusted, and not limited to three. The three CML circuits-to-inare only example for illustration, and not used to limit the scope of present disclosure.

The latch signals Cto Care generated by the signal tree. The signal treereceives amplified data strobe signals DSto DSfrom the DQS receiver, and generates the latch signals Cto Cby buffering the amplified data strobe signals DSto DS, respectively. The DQS receiveris coupled to the signal tree, receives a data strobe signal DQS and generates the amplified data strobe signals DSto DSby amplifying the data strobe signal DQS, where the amplified data strobe signals DSto DSare 4-phase quadrature signals.

Please refer to, which illustrates a circuit diagram of a DQS receiver according to an embodiment of present disclosure. The DQS receiverincludes a plurality of CML circuits-to-N, an analog to digital amplifierand a frequency divider. The CML circuits-to-N are coupled in series. The first stage CML circuit-receives a data request signal pair including data request signals DQS_t and DQS_c which are complementary to each other. The first stage CML circuit-may be a CTLE circuit. The CML circuits-to-N form an amplify string to amplify the data request signals DQS_t and DQS_c and generate amplified data request signals ADOSand ADOS.

The analog to digital amplifieris coupled to the final stage CML circuit-N, and converts the amplified data request signals ADOSand ADOSfrom analog format to digital format. The frequency divideris coupled to the analog to digital amplifier, and generates the amplified data strobe signals DSto DSby dividing a frequency of at least one of the amplified data request signals ADOSand ADOSwith digital format. The frequency dividermay divide the frequency of the amplified data request signals ADOSand ADOSby. In this embodiment, the amplified data strobe signals DSto DSmay respectively has four different phases and the amplified data strobe signals DSto DSare half frequency signals.

Please refer to, which illustrates a circuit diagram of a part of a signal latch according to an embodiment of present disclosure. The signal latchincludes a data latchand a bias voltage generator. The data latchincludes latch circuitsand, a differential pair, a current source, a plurality of first DFE summersand a plurality of second DFE summers. The latch circuitincludes transistors Mto M. The transistors Mand Mare coupled in series between a power voltage VP and a reference ground voltage GND to form a first inverter. The transistors Mand Mare coupled in series between the power voltage VP and the reference ground voltage GND to form a second inverter. The input end (control ends of the transistors Mand M) of the first inverter is coupled to an output end (a second end of the transistor Mand a first end of the transistor M) of the second inverter. The input end (control ends of the transistors Mand M) of the second inverter is coupled to the output end (a second end of the transistor Mand a first end of the transistor M) of the first inverter. A second end of the transistor Mand a second end of the transistor Mare respectively coupled to differential ends com− and com+ of the differential pair. Furthermore, the transistors Mand Mare coupled to the transistor Min parallel, and controlled by a clock signal CLK. The transistors Mand Mare coupled to the transistor Min parallel, and controlled by the clock signal CLK. The transistors Mto Mare pull up transistors which are used to pull outputs of the latch circuitto the power voltage VP when the clock signal CLK is at logic low. When the clock signal CLK is at logic high, the two output signals OEand OEof the latch circuitare differential signals, and the latch circuitmay latch signals on the two differential ends com− and com+ to generated the output signals on two inverted output ends OEand OE.

Output ends OEand OEof the latch circuitare coupled to the latch circuit. The latch circuitlatches the output signal of the larch circuitto generate output data ODATA.

The differential pairincludes transistors Mand M. A first end of the transistor Mis coupled to the differential end com− and a second end of the transistor Mis coupled to a common end CME of the differential pair, and a control end of the transistor Mreceives an input signal Vin+. A first end of the transistor Mis coupled to the differential end com+ and a second end of the transistor Mis coupled to the common end CME of the differential pair, and a control end of the transistor Mreceives an input signal Vin−. Wherein, the input signals Vin+ and Vin− may be the amplified data signals provided by a plurality of CML circuits in a data receiver of a DRAM.

The current sourceincludes transistors MCand MC, and the transistors MCand MCare coupled in series between the common end CME and the reference ground voltage GND. The transistor MCis controlled by the clock signal CLK. The transistor MCis controlled by a bias voltage Vb.

The first DFE summersare coupled to first differential end com−, and the second DFE summersare coupled to second differential end com+. A number of the first DFE summerscan be determined by a tap number. In this embodiment, the number of the first DFE summersmay equal M, where M is a positive integer. Furthermore, a number of the second DFE summersequals to the number of the first DFE summers. The M first DFE summersare respectively corresponding to a plurality of feedback data (for example, the first feedback data to a Mth feedback data), and the M second DFE summersare respectively corresponding to the plurality of feedback data (for example, the first feedback data to the Mth feedback data), too.

Each of the first DFE summersincludes transistors Mto M. The transistors Mto Mare coupled in series between the first differential end com− and the reference ground voltage GND. In the first DFE summerof a first stage, the transistor Mis controlled by a bias voltage Vb. The transistor Mis controlled by an output signal of a logic gate, and the transistor Mis controlled by the clock signal CLK. Wherein, the logic gatereceives a feedback data Dfband a sign information SGNof feedback data Dfb, and the logic gatemay be an XNOR gate. The first DFE summersare used to draw a bias current from the first differential end com− according to the plurality of feedback data Dfb. Each of the second DFE summersincludes transistors Mto M. In the second DFE summerof a first stage, the transistors Mto Mare coupled in series between the second differential end com+ and the reference ground voltage GND. The transistor Mis controlled by the bias voltage Vb. The transistor Mis controlled by an output signal of a logic gate, and the transistor Mis controlled by the clock signal CLK. Wherein, the logic gatereceives the feedback data Dfband the sign information SGNof feedback data Dfb, and the logic gatemay be an XOR gate. The second DFE summersare used to draw a bias current from the second differential end com+ according to the plurality of feedback data Dfb.

On the other hand, the bias voltage generatoris coupled to the data latch, and the bias voltage generatoris used to provide the bias voltage Vband Vbto the data latch. The bias voltage generatorincludes transistors Mbto Mb. The transistors Mband Mbare coupled in series between the power voltage VP and the reference ground voltage GND. The transistor Mbis controlled by a bias voltage PB. A control end and a first end of the transistor Mbare coupled together to generate the bias voltage Vb. The transistors Mband Mbare coupled in series between the power voltage VP and the reference ground voltage GND. The transistor Mbis controlled by a bias voltage PB. A control end and a first end of the transistor Mbare coupled together to generate the bias voltage Vb. It should be noted here, a current of the transistor Mbcan be adjusted according to a setting code. The setting code can be recorded in a mode register of a memory device. The current of the transistor Mbflows through the transistor Mbto establish the bias voltage Vb. That is, the bias voltage Vbcan be programmed according to the setting code.

Please be noted here, a number of sub-circuitsformed by the transistors Mband Mbmay equal M. That is, the number of the sub-circuitsis same as the number of the first DFE summers, and is also same as the number of the second DFE summers.

Please be noted here, during an operation, both the transistor Mand Mmay be turned on simultaneously.

In additional, in present disclosure, one bias voltage generatorcan be shared by a plurality of signal latches as the signal latchto save a circuit size. For example, one bias voltage generatormay be shared by 4 signal latches.

Please refer toand, which illustrate a schematic diagram of a data latch of a signal receiver in a DRAM device according to an embodiment of present disclosure. In, the data latchincludes latchesand, a differential pair, a current source, a plurality of first DFE summersand a plurality of second DFE summers. In here, detail circuits of the latchesand, the differential pair, the current source, the plurality of first DFE summersand the plurality of second DFE summershave been described in the embodiment of, and no more repeated description here.

It should be noted here, output signals DO+ and DO− generated by the latch circuitmay be feedback to generate feedback data Dfb+ and Dfb−, respectively. Also, the data latchmay receive other output signals from other data latch to obtain feedback data Dfb+ to Dfb+ and Dfb− to Dfb−. Wherein the output signals DO+ and DO− are differential signal pair, the feedback data Dfb+ and Dfb−, Dfb+ and Dfb− and Dfb+ and Dfb− are all differential signal pair.

The feedback data Dfb+ to Dfb+ and Dfb− to Dfb− and corresponding sign information may be inputted to the first DFE summersand the second DFE summers, respectively. In this embodiment, number of the first summersmay be four, and number of the second summersmay be four, too. The four first summersand the four second summersare respectively corresponding to the feedback data Dfb+ to Dfb+ and Dfb− to Dfb−. In, transistors of one of the first summerrespectively receive the feedback data DfbN+, DfbN− and corresponding sign information SGN+ and SGN−. Transistors of one of the second summerrespectively receive the feedback data DfbN+, DfbN− and corresponding sign information SGN+ and SGN−. Wherein, N may be from 1 to 4. Such as that, the first summersand the second summersmay share one bias voltage generator as the bias voltage generatorin, and circuit size can be saved.

In, a plurality of data latchestoare illustrated. A circuit structure of each of the data latchestois similar to a circuit structure of the data latch, and details of the circuit structure of the data latchhas been described in the embodiment of, and no more descriptions here. In, the data latchestorespectively receive data strobe signals DQS_, DQS_, DQS_and DQS. There is a phase difference of 90 degree between the data strobe signals DQS_and DQS_; there is a phase difference of 90 degree between the data strobe signals DQS_and DQS_; there is a phase difference of 90 degree between the data strobe signals DQS_and DQS_; and there is a phase difference of 90 degree between the data strobe signals DQS_and DQS_.

On the other hand, the data latchprovides output signals DO+ and DO−; the data latchprovides output signals DO+ and DO−; the data latchprovides output signals DO+ and DO−; the data latchprovides output signals DO+ and DO−. The output signals DO+ to DO+ respectively form a plurality of output signal pairs with the output signals DO− to DO−, wherein each of the output signal pair is a differential signal pair. There is a phase difference of 90 degree between the output signals DO+ and DO+; there is a phase difference of 90 degree between the output signals DO+ and DO+; there is a phase difference of 90 degree between the output signals DO+ and DO+; and there is a phase difference of 90 degree between the output signals DO+ and DO+0. Furthermore, in presented disclosure, in presented disclosure, the data latchmay feedback the output signals DO+ and DO− to itself to form feedback signals Dfb+ and Dfb−; the data latchmay feedback the output signals DO+ and DO− to the data latchto form feedback signals Dfb+ and Df−; the data latchmay feedback the output signals DO+ and DO− to the data latchto form feedback signals Dfb+ and Df−. It should be noted here, the data latchmay not feedback the output signals DO+ and DO− to the data latchestoto form the feedback signals Dfb+ and Dfb− directly. In this embodiment, the data latchis a last stage data latch, and the data latchmay feedback signals inputted to a latch circuitfor generating the output signals DO+ and DO− to form feedback signals Dfb+ and Dfb−. The signals inputted to the latch circuitare two inverted output signals generated by a latch circuit of the data latch.

The feedback signals Dfb+ to Dfb+ and Dfb− to Dfb− may be transmitted to summers of the data latch.

It should be noted here, the data latchestoalso provide the feedback signals Dfb+ to Dfb+ and Dfb− to Dfb− to each of the data latchedtoby the same manner shown as.

In summary, in the presented disclosure, a plurality of CML circuits are disposed in the data receiver of the signal receiver to amplify the data signal. Furthermore, the CML circuits in the data receiver provides a propagation delay for transmitting the amplified data signal. Such as that, a specification of JEDEC standard for DDR5 DRAM can be met.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.