Memory device

This application is a Continuation Application of PCT Application No. PCT/JP2021/045583, filed Dec. 10, 2021, the entire contents of which are incorporated herein by reference.

Embodiments relate to a memory device.

A NOR flash memory is known as a memory device capable of storing data in a non-volatile manner. In a memory device such as a NOR flash memory, a three-dimensional memory structure has been studied for higher integration and larger capacity.

According to one embodiment, a memory device includes: a first semiconductor layer, a first conductive layer, a second semiconductor layer, and a second conductive layer that are arranged in this order in a first direction, spaced apart from each other; a first semiconductor film extending in the first direction, being in contact with the first semiconductor layer and the second semiconductor layer, and intersecting the first conductive layer and the second conductive layer; a first memory film provided between the first conductive layer and the first semiconductor film; and a second memory film provided between the second conductive layer and the first semiconductor film.

Hereinafter, an embodiment is described with reference to the drawings. The dimensions, scales, etc., used in the drawings are not binding on actual products.

Note that in the following description, the same reference numerals denote components having almost the same functions and configurations. For the purpose of distinguishing between elements having the same or substantially the same configurations, the description may add different characters or numerals after their respective reference signs.

1.1 Memory System

A configuration of a memory system according to an embodiment is described.

is a block diagram showing a configuration example of a memory system including a memory device according to the embodiment. A memory systemis a storage device. The memory systemperforms a write operation and a read operation of data. The memory systemincludes a memory controllerand a memory device.

The memory controlleris constituted by an integrated circuit such as a system-on-a-chip (SoC), for example. The memory controllercontrols the memory devicebased on a request from an external host device (not shown). Specifically, for example, in a write operation, the memory controllertransmits data to be written to the memory device. In a read operation, the memory controllerreceives data that is read from the memory device. The memory controllercontrols the memory device. Specifically, for example, the memory controllerrewrites data written in a certain storage area in the memory deviceto another storage area, and then erases the data written in the certain storage area.

The memory deviceis a non-volatile memory. The memory deviceis, for example, a NOR flash memory. The memory devicestores data in a non-volatile manner.

1.2 Memory Device

An internal configuration of the memory device according to the embodiment will continuously be described with reference to the block diagram shown in. The memory deviceincludes an input/output circuit, a register, a sequencer, a voltage generator, a driver set, a memory cell array, a row decoder, and a sense amplifier module.

The input/output circuittransmits and receives various signals to and from the memory controller. The signals transmitted and received by the input/output circuitinclude, for example, a command CMD, an address ADD, and data DAT. The command CMD specifies an operation that the memory controllerinstructs the memory deviceto perform. The address ADD specifies a storage area in the memory device. The data DAT includes data (write data) to be written to the memory deviceor data (read data) that is read from the memory device.

The input/output circuittransmits the address ADD and command CMD and the write data DAT to the registerand the sense amplifier module, respectively. The input/output circuitreceives the read data DAT from the sense amplifier module.

The registerstores the address ADD and the command CMD.

The sequencercontrols the entire operation of the memory devicebased on the command CMD stored in the register.

The voltage generatorgenerates voltages used in a write operation, a read operation, an erase operation, etc.

The driver setsupplies the voltages generated by the voltage generatorto the memory cell array, the row decoder, and the sense amplifier module.

The memory cell arrayincludes a plurality of blocks BLK, a plurality of bit lines, a plurality of source lines, and a plurality of word lines. In the example of, a case is shown where the memory cell arrayincludes four blocks BLK, BLK, BLK, and BLK. The block BLK is, for example, a storage area corresponding to a predetermined data capacity in the memory cell array. Each block BLK includes a plurality of memory cell transistors. Each memory cell transistor is specified by selecting a bit line, a source line, and a word line. The detailed configuration of the memory cell arraywill be described later.

The row decoderselects one of the blocks BLKto BLKbased on the address ADD in the register. The row decoderfurther selects a word line in the selected block BLK based on the address ADD in the register.

The sense amplifier moduleselects a set of a bit line and a source line based on the address ADD in the register. In a write operation, the sense amplifier moduletransfers write data DAT to the memory cell arrayvia the selected bit line. In a read operation, the sense amplifier modulesenses a threshold voltage of a memory cell transistor via the selected bit line. The sense amplifier modulegenerates read data DAT based on a result of the sensing.

1.3 Circuit Configuration of Memory Cell Array

is a circuit diagram showing an example of a circuit configuration of the memory cell array included in the memory device according to the embodiment.shows one block BLK of the plurality of blocks BLK included in the memory cell array. As shown in, the memory cell arrayis coupled to, for example, four word lines WLto WL, (m+1) source lines SLto SLm, and 16 bit lines BLto BL(m is an integer of 2 or greater).shows a case where m is 2 or greater; however, the embodiment is not limited to this example and m may be 0 or 1.

The block BLK includes a plurality of string units SU. Each string unit SU includes a plurality of NOR strings NS. Each NOR string NS includes a plurality of memory cell transistors MT. Each memory cell transistor MT includes a control gate and a charge storage layer. Each memory cell transistor MT stores data in a non-volatile manner.illustrates a case where each block BLK includes four string units SUto SU, each string unit SU includes (m+1) NOR strings NSto NSm, and each NOR string NS includes four memory cell transistors MTto MT.

In each NOR string NS, the memory cell transistors MTto MTare coupled in series. A first end of each memory cell transistor MT is coupled to a corresponding bit line BL.

Specifically, in the string unit SU, the first ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL.

In the string unit SU, the first ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL.

In the string unit SU, the first ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL.

In the string unit SU, the first ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL. In the string unit SU, the first ends of the memory cell transistors MTand the second ends of the memory cell transistors MTare commonly coupled to the bit line BL.

Each NOR string NS is coupled to a corresponding source line SL.

Specifically, the second ends of the memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the source line SL. The second ends of the memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the source line SL. The second ends of the memory cell transistors MTof each NOR string NSm of respective string units SU are commonly coupled to the source line SLm.

In each NOR string NS, each memory cell transistor MT is coupled to a corresponding word line WL.

Specifically, the gates of the memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the word line WL. The gates of the memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the word line WL. The gates of the memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the word line WL. The gates of memory cell transistors MTof each NOR string NSof respective string units SU are commonly coupled to the word line WL.

The above configuration is repeated for each block BLK. The word lines WLto WLand the bit lines BLto BLare provided independently for each block BLK, for example. The source lines SLto SLm are shared between the blocks BLK, for example.

The circuit configuration of the memory cell arrayincluded in the memory deviceaccording to the embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK may be designed to be any number. The number of NOR strings NS included in each string unit SU may be designed to be any number. The number of memory cell transistors MT included in each NOR string NS may be designed to be any number.

1.4 Structure of Memory Cell Array

Next, a structure of the memory cell array included in the memory device according to the embodiment is described. Note that in the drawings to be referred to hereinafter, an X direction corresponds to the extending direction of the word lines WL and the bit lines BL. A Y direction corresponds to the extending direction of the source lines SL. A Z direction corresponds to a direction perpendicular to the surface of the semiconductor substrate used for forming the memory device. The plan views use hatching as appropriate to achieve better viewability. Such hatching is not necessarily related to materials or properties of the hatched objects or components. The sectional views may also omit components as appropriate to achieve better viewability.

1.4.1 Outline of Planar Layout

is a plan view showing an example of a planar layout of the memory cell array according to the embodiment. What is shown incovers a structural part corresponding to four blocks BLKto BLK. As shown in, the memory cell arrayincludes a stacked interconnect structure and a plurality of members SLTa and SLTb.

The stacked interconnect structure is a structure in which a plurality of interconnects including the word lines WL and the bit lines BL are stacked. The planar layout of the stacked interconnect structure is divided into, for example, a memory region MA and hookup areas HAand HAin the X direction. The memory area MA is an area in which a plurality of NOR strings NS are formed in the stacked interconnect structure. The hookup areas HAand HAare areas used for connection between the plurality of word lines WL and the row decoderand coupling between the plurality of bit lines BL and the sense amplifier module. The memory area MA is interposed between the hookup areas HAand HA.

Each of the plurality of members SLTa is a plate-shaped insulator extending along the X direction. The plurality of members STLa are arranged in the Y direction. Each member SLTa divides the stacked interconnect structure so as to cross the memory region MA and the hookup areas HAand HA. The stacked interconnect structure divided by two members SLTa corresponds to one block BLK.

Each of the plurality of members SLTb is a plate-shaped insulator extending along the X direction. Three members SLTb are arranged in the Y direction between two adjacent members SLTa. Each member SLTb divides the stacked interconnect structure so as to cross the memory region MA and the hookup areas HAand HA. The stacked interconnect structure divided by two members SLTb or one member SLTa and one member SLTb corresponds to one string unit SU.

The planar layout of the memory cell arraydescribed above is repeatedly arranged in the Y direction. The planar layout of the memory cell arrayis not limited to the above-described planar layout. For example, the number of members SLTb disposed between two members SLTa is changed according to the number of string units SU included in one block BLK.

1.4.2 Memory Area

Next, a configuration of the memory area of the memory cell array according to the embodiment is described.

1.4.2.1 Planar Layout

is a plan view showing an example of a detailed planar layout in a memory area of the memory cell array according to the embodiment.illustrates a part of the memory area MA including one block BLK (that is, string units SUto SU) and two members SLTa interposing the block BLK. As shown in, the memory cell arrayin its memory area MA includes a plurality of source pillars SP, a plurality of contacts CVa, and a plurality of source lines SL.

The source pillar SP is, for example, a columnar structure provided in the stacked interconnect structure. Each source pillar SP functions as one NOR string NS. The plurality of source pillars SP are arranged in a matrix in an area between two adjacent members SLTa, for example. Specifically, in one block BLK, the plurality of source pillars SP arranged in the X direction are arranged in four columns in the Y direction. A member SLTb is arranged between the source pillars SP in two adjacent columns.

The plurality of source lines SL are arranged in the X direction. Each source line SL extends in the Y direction. Each source line SL is arranged to overlap at least one source pillar SP in each string unit SU in a plan view. In the example of, a case is shown where one source line SL is arranged so as to overlap one source pillar SP for each string unit SU in a plan view. The source pillars SP and the source line SL arranged so as to overlap the source pillars SP in a plan view are coupled via the contacts CVa.