Impingement cooling in high power package

The disclosed embodiments relate generally to semiconductor packaging technology, and in particular to, methods and systems of using impingement cooling to dissipate heat generated by electronic components in a semiconductor assembly.

High speed and high power electronic components are widely used in electronic devices. These electronic components often generate large amount of heat that must be dissipated quickly and efficiently to maintain normal device performance. Existing solutions either require a larger footprint than that occupied by the high speed components or implement expensive systems to quickly dissipate heat generated by these components. As such, there is a need for compact cooling solutions that can cool down high speed and/or high power components in an electronic system effectively and efficiently.

Various embodiments of systems, methods and devices within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly after considering the section entitled “Detailed Description” one will understand how the aspects of various embodiments are used to reduce heat in a semiconductor system such that electronic components can operate at higher speeds and higher power. Specifically, in an example, an electronic component (e.g., a semiconductor die, a semiconductor package, etc.) is formed on a device substrate that provides cooling to the electronic component through their contact. Specifically, the device substrate absorbs heat generated by the electronic components and is cooled by a jet of coolant that is provided through a cooling substrate and impinges upon the device substrate. Some embodiments described herein include a semiconductor package that applies impingement cooling based on an improved thermal coefficient cooling model. Some embodiments relate to a semiconductor system and method for mounting the semiconductor package in a radio frequency (RF) assembly that creates a coolant path for impingement cooling while maintaining a solid RF ground.

In accordance with some embodiments, a semiconductor system includes a device substrate having a first surface and a second surface opposite the first surface, an electronic component thermally coupled to the device substrate, and a cooling substrate coupled to the device substrate. The cooling substrate includes a third surface facing the second surface of the device substrate, a fourth surface opposite the third surface, and a plurality of vias between the third and fourth surfaces. The second surface of the device substrate and the third surface of the cooling substrate define a cavity therebetween, such that in use coolant flows from the fourth surface through the plurality of vias to exit at the third surface, enters the cavity between the second surface of the device substrate and third surface of the cooling substrate, and impinges on the second surface of the device substrate. At least a portion of one or more of the device substrate and the cooling substrate have similar coefficients of thermal expansion.

In some embodiments, the device substrate is configured to spread heat uniformly across its first and second surfaces.

In some embodiments, the device substrate includes a single crystal diamond configured to spread and dissipate heat. Alternatively, in some embodiments, the device substrate includes a polycrystalline diamond substrate configured to spread and dissipate heat.

In some embodiments, the plurality of vias are coupled to a plurality of nozzle structures, and the cooling substrate and the plurality of nozzle structures have thermal expansion coefficients similar to one another.

In some embodiments, the cooling substrate is coupled to the device substrate via one or more spacers. Further, in some embodiments, the one or more spacers are integral parts of the cooling substrate.

In some embodiments, the cooling substrate is made of one of glass, a nickel-cobalt ferrous alloy, a 36% nickel steel alloy, and Molybdenum.

In some embodiments, the cooling substrate is made of one of a metallic material having a thermal expansion coefficient in a range including a predefined thermal expansion coefficient of 1×10m/(m·° C.). Further, in some embodiments, the range is 0-8×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range. Additionally, in some embodiments, the range is 1-7×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range. Also, in some embodiments, the range is 1-3×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range.

In some embodiments, the cavity is fully sealed except the plurality of vias that allow the coolant to flow between the third and fourth surfaces. The coolant is configured to enter and exit the cavity via the plurality of vias.

In some embodiments, the electronic component is configured to operate in a radio frequency range, and the device substrate is made of silicon carbide. Further, in some embodiments, the silicon carbide has a thermal expansion coefficient approximately equal to 3-4×10m/(m·° C.).

In some embodiments, the plurality of vias have a diameter between 50 to 200 micrometers inclusive.

In some embodiments, each surface has a surface length of approximately 10 millimeters (mm) by 6 mm.

In some embodiments, the cavity separates the second surface and the third surface by at least 100 micrometers. Further, in some embodiments, the cavity separates the second surface by no more than 3 mm.

In some embodiments, the device substrate includes a plurality of patterns configured to remove heat and/or cool the device substrate.

In some embodiments, the electronic component includes a plurality of patterns configured to remove heat and/or cool the electronic component. Further, in some embodiments, the predetermined patterns include one or more fins, pins, depressions, channel, and ridges. Additionally, in some embodiments, the predetermined patterns are symmetrical. Conversely, in some embodiments, the predetermined patterns are asymmetrical.

In another aspect, a method for fabricating a semiconductor system includes providing a device substrate having a first surface and a second surface opposite the first surface. The method further includes forming an electronic component on the first surface of the device substrate and providing a cooling substrate having a third surface, a fourth surface opposite the third surface, and a plurality of vias between the third and fourth surfaces. The cooling substrate is coupled to the device substrate, the third surface faces the second surface of the device substrate, and the second surface and the third surfaces define a cavity therebetween. In use, coolant flows from the fourth surface through the plurality of vias exit at the third surface, enters the cavity between the second and third surfaces, and impinges on the second surface of the device substrate. In some embodiments, the method further includes coupling a plurality of nozzle structures to the plurality of vias. In some embodiments, the method further includes forming predetermined patterns on the device substrate and/or the electronic component. Further, in some embodiments, the predetermined patterns include one or more fins, pins, depressions, channel, and ridges.

The fabricated semiconductor of any embodiments of the above methods is any of the fore-mentioned semiconductor systems.

Note that the various embodiments described above can be combined with any other embodiments described herein. The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures.

Numerous details are described herein in order to provide a thorough understanding of the example embodiments illustrated in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the scope of the claims is only limited by those features and aspects specifically recited in the claims. Furthermore, well-known processes, components, and materials have not been described in exhaustive detail so as not to unnecessarily obscure pertinent aspects of the embodiments described herein.

is a cross sectional view of a semiconductor systemhaving a cavity for impingement cooling, in accordance with some embodiments. The semiconductor systemincludes one or more of a device substrate, an electronic component, a cooling substrate, a plurality of vias, one or more nozzles, a cavity, and one or more spacers. The device substrateincludes a first surface-and a second surface-, and the second surface-is opposite the first surface-. In some embodiments, the first surface-and the second surface-have a surface area of approximately 10×6 mm. In some embodiments, each of the first and second surfaces-and-is flat.

In some embodiments, each of the first and second surfaces-and-has a predetermined pattern (also called surface profile) including one or more heat transfer structures known in the art. For example, the predetermined pattern of the device substrateincludes one or more fins, pins, depressions, channels, and/or ridges. Each heat transfer structure in the predetermined pattern of the device substratecan have different sizes and/or geometric shapes. For example, the fins formed in the pattern of the device substrateoptionally include circular or square pillars having different surface areas. The one or more heat transfer structures can be arranged in a symmetric or asymmetric manner in the predetermined pattern of the device substrate. By these means, the predetermined pattern increases a surface area of the device substrateand allows impingement cooling not to be limited to a specific location of the device substrate, thereby enhancing the device substrate's ability to dissipate heat from its surfaces-and-with or without impingement cooling by a jet of coolant. More details on the predetermined pattern and surface profile of the device substrate are discussed below with reference to.

The device substrateis configured to spread (and dissipate) heat across its body and surfaces, e.g., the first surface-and the second surface-. In some embodiments, the device substrateis configured to uniformly spread (and dissipate) heat across its body and/or surfaces. Alternatively, in some embodiments, the device substrateis configured to spread the heat more efficiently on one or more portions (e.g., a portion coupled to the electronic component). In some embodiments, the device substrateincludes a single crystal diamond configured to spread and dissipate heat. Alternatively, in some embodiments, the device substrateincludes a polycrystalline diamond substrate configured to spread and dissipate heat. In some embodiments, the device substratehas a thermal expansion coefficient no greater than (i.e., equal to or less than) 1×10m/(m·° C.). In some embodiments, the thermal expansion coefficient of the device substrateis a linear thermal expansion coefficient that varies linearly with a temperature.

The electronic componentis thermally coupled to the device substrate. The electronic componentcan be coupled on the first surface-or the second surface-of the device substrate. In some embodiments, the electronic componentis an integral part of the device substrate. Alternatively, in some embodiments, the electronic componentis mounted on the device substratein a hybrid manner. The electronic componentis configured to be smaller than the device substrateand/or the cooling substrate. A smaller size of the electronic componentallows for a greater relative variance in size with respect to the device substrate, and this relative variance in size is optionally caused by a mismatch of thermal expansion between the electronic componentand device substrate. In an example, the electronic componentis less than one tenth the size of the device substrate, and a device substratehaving a surface area of 10×6 mmis thermally coupled to an electronic componenthaving a surface area less than 1×6 mm.

During its normal operation, the electronic componentgenerates heat that may increase an operating temperature of the electronic componentlocally. The heat generated by the electronic component can also be distributed to the entire semiconductor systemto increase a temperature of the semiconductor system. In some embodiments, the electronic component(e.g., a RF component) is configured to operate with a high power (e.g., >10 Watts) and/or at a high speed (e.g., >1 GHz), which causes the electronic componentto excessive heat that needs to be dissipated via the semiconductor system. Specifically, the heat generated by the electronic componentis partially dissipated to air from an open surface of the electronic component, and partially absorbed by the device substratethat is thermally coupled to the electronic component. As its operating temperature increases, the electronic componentexpands according to its thermal expansion coefficient (e.g., in a range of 3-4×10m/(m·° C.)).

In some embodiments, the electronic componentis a semiconductor die or a semiconductor device package. In some embodiments, the electronic componenthas a substrate made of silicon carbide. In some embodiments, the electronic componentis configured to operate in an RF range (e.g., 20 kHz to around 300 GHz). In some embodiments, the electronic componentis configured to operate in a plurality of RF bandwidths in an RF range (e.g., RF bandwidths in 20 kHz to around 300 GHz). Alternatively, in some embodiments, the electronic componentis configured to operate in a radio frequency range between 100 MHz to 500 MHz.

The electronic componentis configured to be cooled down by the device substrate. In some embodiments, the electronic componentincludes a predetermined pattern (i.e., surface profile) configured to increase a surface area of the electronic component. The predetermined pattern of the electronic componentis optionally identical to or distinct from the predetermined pattern of the device substrate. The predetermined pattern of the electronic componentincludes one or more heat transfer structures (e.g., fins, pins, depressions, channels, and ridges). Optionally, these heat transfer structures have identical or different sizes (e.g., cross sectional areas and heights). Optionally, these heat transfer structures have identical or different geometric shapes. Optionally, the heat transfer structures are arranged in a symmetric or asymmetric manner in the predetermined pattern of the electronic component. As such, the predetermined pattern of the electronic componentincreases a surface area of the electronic component, thereby helping dissipation of the heat generated by the electronic component.

The cooling substrateis coupled to the device substrate. The cooling substrateincludes a third surface-, and a fourth surface-opposite the third surface-. In some embodiments, the third surface-faces (or is adjacent to) the second surface-of the device substrate. A cavityis formed between the third surface-and the second surface-. In some embodiments, the third surface-and the fourth surface-have the same length and/or surface area as the first surface-and the second surface-of the device substrate(e.g., a surface area of approximately 10×6 mm).

In some embodiments, the cooling substrateis coupled to the device substratevia the one or more spacers. The one or more spacersare configured to separate the second surface-of the device substrateand the third surface-of the cooling substrateand define a height of the cavityformed between the surfaces-and-. The one or more spacershave a predetermined length (represented by “L_s” in), e.g., between 100 um and 3 mm. In some embodiments, the one or more spacersare integral parts of the cooling substrate. Conversely, in some embodiments, the one or more spacersare standalone components coupled between the cooling substrateand the device substrate. The cooling substrateis configured to be easy to machine and couple into the semiconductor system.

In some embodiments, the cooling substrateis made of one or more of glass, a nickel-cobalt ferrous alloy, a 36% nickel steel alloy (e.g., Invar), and Molybdenum. An example of the nickel-cobalt ferrous alloy is a Kovar metal alloy that is approximately made of 29% nickel, 17% cobalt and the balance iron. Alternatively or additionally, in some embodiments, the cooling substrateis a metallic material having a thermal expansion coefficient in a range including a predefined thermal expansion coefficient. In some embodiments, the range is 1×10m/(m·° C.) to 8×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range. In some embodiments, the range is 1×10m/(m·° C.) to 7×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range. In some embodiments, the range is 1×10m/(m·° C.) to 3×10m/(m·° C.), and the thermal expansion coefficient of the metallic material is in the range. In some embodiments, the predefined thermal expansion coefficient is 1×10m/(m·° C.). In some embodiments, at least a portion of the device substrateand the cooling substratehave similar coefficients of thermal expansion, i.e., a mismatch of the thermal expansion coefficients of the portion of the device substrateand cooling substrateis less than a threshold mismatch (e.g., 0.5%, 1%). In some embodiments, the threshold mismatch is based on a thermal cycle and the size of the interface (e.g., contact surface) between components.

The range of 1×10m/(m·° C.) to 8×10m/(m ° C.) allows for the cooling substrateto be implemented in a wide variety of systems at an affordable price. In particular, this range allows for the cooling substrateto be implemented in high precision systems that have strict design constraints as well as more tolerant systems that allow for greater variances. Further, this range allows for a material to be selected based on its ease of use (e.g., Invar is harder to work with than Molybdenum). Additionally or alternatively, the range of 1×10m/(m·° C.) to 8×10m/(m·° C.) allows for a thermal expansion coefficient for the cooling substrateto be selected based on its operational use (e.g., high or low temperature systems, constant temperature systems, variable temperature systems, etc.).

The cooling substrateincludes the plurality of viasbetween the third surface-and the fourth surface-. The plurality of viashave a predetermined size. In some embodiments, the predetermined size of the plurality of viasis a diameter of between 50 to 200 micrometers inclusive. This diameter range allows for coolant to efficiently enter and exit the cooling substratewhile also providing efficient heat transfer. In particular, as discussed below, in some implementations, the efficiency of the heat transfer between the device substrateand the coolant is based, in part on the shape and/or size of the plurality of vias. In some embodiments, each via of the plurality of viashas the same predetermined size. Alternatively, in some embodiments, at least one via of the plurality of viashas a predetermined size that is distinct from other vias of the plurality of vias. When impingement cooling is applied to dissipate heat of the device substrate, coolant (e.g., air, water, etc.) flows through the plurality of viasand enter the cavitybetween the cooling substrateand the device substrate.

In some embodiments, the plurality of viasare coupled to the one or more nozzles(also referred to as a plurality of nozzle structures). The one or more nozzlesare configured to force or push in the coolant through the plurality of vias. In some embodiments, the cooling substrateand the one or more nozzleshave thermal expansion coefficients similar to one another, i.e., a difference of the thermal expansion coefficients of the cooling substrateand nozzlesis less than a threshold mismatch (e.g., 1%). By these means, the cooling substrateand the one or more nozzlescan expand proportionally or in a controlled manner, without compromising a corresponding impingement cooling process. In some embodiments, the one or more nozzlesare optional as the plurality of viasoperate as a nozzle.

The cavityis defined by at least the device substrateand the cooling substrate. The distance between the second surface-of the device substrateand the third surface-of the cooling substratedefines the height of the cavity. In some embodiments, the distance between the second surface-of the device substrateand the third surface-of the cooling substrateis equal to the predetermined length of the one or more spacers. In an example, the distance between the second surface-and the third surface-is between 100 micrometers (μm) to 3 mm, so is the height of the cavity. In another example, the cavityseparates the second surface-of the device substrateand the third surface-of the cooling substrateby at least 100 μm. This separation distance between the second surface-and the third surface-allows for coolant to efficiently and substantially impinge on the second surfaceand thus provide efficient heat transfer. In particular, as discussed below, in some implementations, the efficiency of the heat transfer between the device substrateand the coolant is based, in part, distance (e.g., separation distance) to diameter (predetermined size of the plurality of vias) ratio. In some embodiments, a ratio with a separation distance of 100 μm to vias with a diameter between 50 to 200 micrometers has been found to provide efficient heat transfer while allowing the device substrateand the cooling substrateto remain thermally coupled.

In some embodiments, the cavityis fully sealed except the plurality of vias, thereby allowing coolant to flow through the plurality of viasof the cooling substrate(e.g., to enter at the fourth surface-and exit at the third surface-of the cooling substrate, and vice versa). Stated another way, the viasallow the coolant to flow between the third and fourth surfaces, and the coolant is configured to enter and exit the cavity via the plurality of vias. In some embodiments, the coolant is one of: air, water, refrigerants, or other fluids and/or gasses. The coolant flowing through the plurality of viasof the cooling substrateimpinges on the second surface-of the device substrate. After the coolant impinges upon the device substrate, the coolant absorbs and carries away part of the heat that has been dissipated from the electronic componentto the device substrate, thereby providing an efficient heat dissipation path to the electronic componentfrom a rear surface of the electronic component.

Specifically, the device substratereceives heat generated by the electronic componentfrom the rear surface of the electronic component. For example, the first surface-of the device substratereceives heat generated by the electronic component's operation. The device substratespreads the received heat across a body, the first surface-and the second surface-. The device substratedissipates the heat received from the electronic componentto the coolant that is injected into the cavitythrough the plurality of vias(and/or one or more nozzles). By these means, the device substratecools the electronic componentthrough heat transfer with the coolant injected into the cavity.

In some embodiments, an efficiency of the heat transfer between the device substrateand the coolant is based, in part, on sizes and shapes of the vias, sizes and shapes of the one or more nozzles, a distance to diameter ratio, an impingement angle, Reynolds number, the number of vias, the number of nozzles, separations among the vias, separations among the nozzles, a coolant flow rate, a type of coolant, a coolant temperature, and/or other factors known in the art. The distance to diameter ratio refers to a ratio between the height of the cavity(e.g., L_s) and a predetermined diameter of the plurality of vias.

is a cross sectional view of a semiconductor systemin a thermally expanded state, in accordance with some embodiments. The semiconductor systemis an instance of the semiconductor systemofwhen the semiconductor systemexperiences temperature changes (e.g., heating or cooling). The semiconductor systemincludes one or more of: a device substrate, an electronic component, a cooling substrate, a plurality of vias, one or more nozzles, a cavity, and one or more spacers.

One or more components of the semiconductor systemexpand with an increase in temperature. For example, heat generated by the electronic componentmay cause the increase in temperature in the semiconductor system. In some situations, heat is introduced into the semiconductor systemby environmental conditions (e.g., ambient air, gases, friction, etc.) and/or one or more components external to the semiconductor system(e.g., other electrical components, engines, etc.). Conversely, the one or more components of semiconductor systemcontracts with a drop in temperature. Heat is dissipated by a surrounding airflow, impingement cooling (generated by the device substrateand cooling substrateworking in conjunction), environmental conditions, and/or one or more components external to the semiconductor system(e.g., fans). In some embodiments, thermal expansion or contraction is approximated by a linear thermal expansion equation as follows:Δ=(α)*(Δ)where ΔL is a change of length, αis a linear thermal expansion coefficient, and ΔT is a change in temperature (e.g., the increase or drop in temperature).

In some embodiments, the device substratehas a thermal expansion coefficient that is less than a predefined threshold expansion coefficient, i.e., 1×10m/(m·° C.), and has a relatively low propensity to change in size when exposed to temperature changes. As described above with reference to, the device substrateis configured to spread heat across its body and surfaces (i.e., the first surface-and the second surface-). In some embodiments, the device substrateuniformly spreads heat across its body and surfaces. Alternatively, in some embodiments, the device substratehas improved heat transfer on one or more regions of its surfaces using a predetermined pattern or surface profile. This allows the device substrateto dissipate heat generated by the electronic componentefficiently, particularly when the predefined pattern is applied jointly with impingement cooling.

In some embodiments, the electronic componentis mounted on the device substratein a hybrid manner. The electronic componenthas a first thermal expansion coefficient, and the device substratehas a second thermal expansion coefficient. Further, in some embodiments, a mismatch of the second thermal expansion coefficient of the electronic component and the first thermal expansion coefficient of the device substrateis less than a threshold mismatch (e.g., within ±5%). Alternatively, in some embodiments, a size of the electronic componentis much smaller than a size of the device substrate, e.g., less than one tenth of the size of the device substrate. When exposed to a temperature variation that is within a temperature tolerance, the electronic componentcan be secured on the device substratewithout being detached, regardless of whether the mismatch of the first and second thermal expansion coefficients exceeds the threshold mismatch.

In some embodiments, the spacersare distinct from the device substrateand the cooling substrate. The spacershave a third thermal expansion coefficient, and the cooling substratehas a fourth thermal expansion coefficient. A mismatch of the second thermal expansion coefficient of the device substrateand the third thermal expansion coefficient of the spacersis less than a respective threshold mismatch (e.g., within ±5%). Similarly, a mismatch of the third thermal expansion coefficient of the spacersand the fourth thermal expansion coefficient of the cooling substrateis less than a respective threshold mismatch (e.g., within ±5%). Alternatively and additionally, in some embodiments, the spacersare integrated in the cooling substrate. A mismatch of the second thermal expansion coefficient of the device substrateand the fourth thermal expansion coefficient of the cooling substrateis less than a respective threshold mismatch (e.g., within ±5%). It is noted that different threshold mismatches in the semiconductor systemare optionally identical to or distinct from each other.

In the illustrative example shown in semiconductor system, the device substratemaintains substantially similar dimensions to the device substrateshown in semiconductor system(e.g., showing a +/−1% increase to no increase) when exposed to high temperatures (e.g., relative to baseline conditions, such as ambient temperature). For example, the first surface-and the second surface-of the device substratemaintain substantially similar surface lengths as those shown in the semiconductor system(e.g., approximately 10×6 mmwith a +/−1% increase or no increase) when the device substrateis exposed to high temperatures. High temperatures, for purposes of this disclosure, means temperatures 5° C. above baseline conditions. As further shown in semiconductor system, in some embodiments, the device substrate(including the first surface-and the second surface-) expands disproportionately relative to the electronic component, the cooling substrate, and/or other components when exposed to high temperatures. More specifically, the device substratedoes not expand or slightly expands in relation to the electronic component, the cooling substrate, and/or other components when exposed to high temperatures. The disproportionate expansion of the device substrateis due to its thermal expansion coefficient (e.g., 1×10−6 m/(m·° C.)).

Additionally, in some embodiments, the device substrate(including the first surface-and the second surface-) contracts (or returns to an unaltered size) when exposed to low temperatures (e.g., relative to baseline conditions, such as ambient temperature) and/or when heat is removed from the device substrate. Low temperatures, for purposes of this disclosure, means temperatures 5° C. below baseline conditions. In some embodiments, impingement cooling received by the device substratecounteracts high temperatures that the device substrateexperiences (e.g., due to heat transfer from the electronic component). For example, in some embodiments, the electronic componentgenerates heat through operation that is transferred to the device substrateand causes the device substrateto expand a first length. Simultaneously, or near simultaneously, the device substrateis impingement cooled by the cooling substratesuch that the device substratecontracts the first length (i.e., effectively leaving the size of the device substrateunchanged). In another example, in some embodiments, the electronic componentgenerates heat through operation that causes the device substrate to expand the first length while the impingement cooling causes the device substrateto contract a second length (less than the first length). In this example, the device substrateis exposed to high temperatures, which cause the device substrateto expand; however, the change in size of the device substratewould be minimized (e.g., less than a 1% increase in size) due to the impingement cooling. In another example, in some embodiments, the electronic componentgenerates heat through operation that causes the device substrate to expand the first length while the impingement cooling causes the device substrateto return to its unaltered size. In other words, the device substrateis exposed to low temperatures (relative to the baseline conditions) or has returned to baseline conditions, which results in no change in size. Although the above examples describe providing impingement cooling on the device substrateto minimize or counteract thermal expansion due to heat, it should be noted that the device substratewould experience minimal to no thermal expansion without cooling due to its low thermal expansion coefficient.

The above examples are non-exhaustive and provided for illustrative purposes. In some embodiments, the overall temperature change of a respective component of the semiconductor system(e.g., the device substrate) is used to determine the change in the component's size. In other words, the change in size in not determined by subtracting the thermal contraction from the thermal expansion, but by using the overall change in temperature with the linear thermal expansion equation and/or other similar equations.

Thermally expanded electronic componentis an instance of the electronic componentwhen exposed to high temperatures (relative to baseline conditions, such as ambient temperature) and/or operating at high temperatures. The electronic componentis configured to expand based, in part, on its own generated heat (through operation) and/or other sources of heat as described above. In some embodiments, the electronic componenthas a higher propensity to change in size than the device substratewhen exposed to temperature changes due to its a higher thermal expansion coefficient (e.g., approximately equal to 3×10m/(m·° C.) to 4×10m/(m·° C.)). Thus, in some embodiments, the device substrateis selected to substantially match the thermal expansion coefficient of the device substratewith that of the electronic componentincluded in the semiconductor system.

As shown in semiconductor system, in some embodiments, the thermally expanded electronic component, when exposed to high temperatures and/or operating at high temperatures, expands across a surface of the device substrate(e.g., the first surface-or the second surface-, whichever surface of the device substratethe electronic componentis thermally coupled to). The smaller size of the electronic component(in relation to the device substrate) allows the electronic componentto change in size while remaining coupled to a surface of the device substrate. In some embodiments, the change in size of the thermally expanded electronic componentis substantial (e.g., at least two times greater than electronic component). In some embodiments, the smaller size of the electronic componentallows for greater variances in size changes (e.g., increases of at least two times its initial size) while remaining coupled to the device substrate. For example, in some embodiments, when the electronic componentis not generating heat (or generating minimal heat) through operation, or when the semiconductor systemis not exposed to high temperatures, the electronic componentis approximately one tenth the size of the device substrate. When the electronic componentgenerates heat through operation and/or when the semiconductor systemis exposed to high temperatures, the size of the electronic componentexpands to be greater than one tenth the size of the device substrate(while remaining thermally coupled the device substrate(as shown in semiconductor system)).

In some embodiments, the electronic componentcontracts (or returns to an unaltered size) when exposed to low temperatures (e.g., relative to baseline conditions, such as ambient temperature) and/or when heat is removed from the electronic component. As described above, the electronic componentand the device substrateare thermally coupled, which allows the device substrateto transfer heat from the electronic component. The removed heat from the electronic componentminimizes or reduces the total thermal expansion of the electronic component. As an example, in some embodiments, the electronic componentgenerates heat through operation that causes the it to expand a first length. Simultaneously, or near simultaneously, the device substrate(which is impingement cooled by the cooling substrate) transfers heat from the electronic componentvia their thermal coupling. The removed heat from the electronic componentreduces its overall temperature change and, as such, reduces its overall change in size due to thermal expansion. Similar to the process described above with respect to the device substrate, the overall temperature change of the electronic componentis used to determine its change in size (e.g., using the linear thermal expansion equation and/or other similar equations). In contrast to the device substrate, the electronic componentis configured to expand substantially when exposed to high temperatures. In particular, the electronic componenthas a thermal expansion coefficient 3 to 4 times greater than the device substrate, which gives it a greater propensity to increase its size when heated. The heat removed by the device substratehelps reduce the expansion by decreasing the overall temperature change while allowing for better performance gains (e.g., operating at higher speeds and/or operating at higher power).