Temperature sensor and electronic system for executing trimming operations

The present application claims priority under 35 U.S.C. § 119 (a) to Korean application number 10-2023-0031304, filed in the Korean Intellectual Property Office on Mar. 9, 2023, the entire disclosure of which is incorporated herein by reference.

The present disclosure relates to a temperature sensor and an electronic system for performing trimming operations.

Recently, an electronic system includes a sensor circuit capable of sensing various operating conditions in order to adjust the speed of an internal operation and whether an internal operation has been activated. Operating conditions that are sensed by the sensor circuit may include a temperature and the amount of light. The sensor circuit may include a temperature sensor for generating a temperature sensing signal in response to a temperature and an optical sensor for generating an optical sensing signal in response to the amount of light.

In an embodiment, a temperature sensor may include a first trimming resistor having a first resistance value that is trimmed based on a first trimming code and configured to adjust a gate voltage, a MOS transistor turned on based on the gate voltage and configured to drive a variable voltage having a voltage level set for each sensing temperature, and a second trimming resistor connected to the MOS transistor, the second trimming resistor having a second resistance value that is trimmed based on a second trimming code.

Furthermore, in an embodiment, a temperature sensor may include a driving voltage regulator configured to drive a driving voltage to a high voltage based on a result of a comparison between a source reference voltage and a voltage generated by dividing the driving voltage, a variable voltage generation circuit including a MOS transistor that drives a variable voltage based on the driving voltage, the variable voltage generation circuit configured to: perform a first trimming operation of adjusting a resistance value of a first trimming resistor in order to adjust a voltage level of a gate voltage of the MOS transistor, and perform a second trimming operation of adjusting a resistance value of a second trimming resistor that is connected to the MOS transistor, and a temperature sensing signal generation circuit configured to generate a temperature sensing signal based on the variable voltage and a temperature reference voltage that is generated by dividing the driving voltage.

Furthermore, in an embodiment, an electronic system may include an external device configured to generate and output a first trimming code and a second trimming code, a logic bit set of each being set based on whether fuses included in the external device have been cut, and a temperature sensor including a MOS transistor that drives a variable voltage based on a driving voltage, the temperature sensor configured to: perform a first trimming operation of adjusting a resistance value of a first trimming resistor based on the first trimming code in order to adjust a voltage level of a gate voltage of the MOS transistor, perform a second trimming operation of adjusting a resistance value of a second trimming resistor that is connected to the MOS transistor based on the second trimming code, and generate a temperature sensing signal based on the variable voltage and a temperature reference voltage.

In the descriptions of the following embodiments, the term “preset” indicates that the numerical value of a parameter is previously decided, when the parameter is used in a process or algorithm. According to an embodiment, the numerical value of the parameter may be set when the process or algorithm is started or while the process or algorithm is performed.

Terms such as “first” and “second,” which are used to distinguish among various components, are not limited by the components. For example, a first component may be referred to as a second component, and vice versa.

When one component is referred to as being “coupled” or “connected” to another component, it should be understood that the components may be directly coupled or connected to each other or coupled or connected to each other through another component interposed therebetween. In contrast, when one component is referred to as being “directly coupled” or “directly connected” to another component, it should be understood that the components are directly coupled or connected to each other without another component interposed therebetween.

A “logic high level” and a “logic low level” are used to describe the logic levels of signals. A signal having a “logic high level” is distinguished from a signal having a “logic low level.” For example, when a signal having a first voltage corresponds to a signal having a “logic high level,” a signal having a second voltage may correspond to a signal having a “logic low level.” According to an embodiment, a “logic high level” may be set to a voltage higher than a “logic low level.” According to an embodiment, the logic levels of signals may be set to different logic levels or opposite logic levels. For example, a signal having a logic high level may be set to have a logic low level in some embodiments, and a signal having a logic low level may be set to have a logic high level in some embodiments.

A “logic bit set” may mean a combination of logic levels of bits included in a signal. When a logic level of each of the bits included in the signal is changed, a logic bit set of the signal may be differently set. For example, if two bits are included in a signal, a logic bit set of the signal may be set as a first logic bit set when logic levels of the two bits included in the signal are a “logic low level” and a “logic low level”, and may be set as a second logic bit set when logic levels of the two bits included in the signal are a “logic low level”, and a “logic high level.”

Hereafter, the present disclosure will be described in more detail through embodiments. The embodiments are only used to exemplify the present disclosure, and the scope of the present disclosure is not limited by the embodiments.

is a block diagram illustrating a construction of an electronic systemaccording to an example of the present disclosure. As illustrated in, the electronic systemmay include an external deviceand a temperature sensor.

The external devicemay include a first control pin_, a second control pin_, a third control pin_, and a fourth control pin_. The temperature sensormay include a first sensor pin_, a second sensor pin_, a third sensor pin_, and a fourth sensor pin_. The external devicemay transmit a power supply voltage VDD to the temperature sensorthrough a first transmission line_that is connected between the first control pin_and the first sensor pin_. The external devicemay transmit a high voltage VPP_E to the temperature sensorthrough a second transmission line_that is connected between the second control pin_and the second sensor pin_. The voltage level of the high voltage VPP_E may be set at a voltage level that is higher than the voltage level of the power supply voltage VDD. The external devicemay transmit a trimming control signal TM_CNT to the temperature sensorthrough a third transmission line_that is connected between the third control pin_and the third sensor pin_. For example, referring to both, the external devicemay include multiple fuses (not illustrated) and may set a logic bit set of bits that are included in the trimming control signal TM_CNT based on whether the fuses have been cut. The trimming control signal TM_CNT may include bits for generating a first trimming code TR_CDfor a first trimming operation and a second trimming code TR_CDfor a second trimming operation. For example, the external devicemay set a logic bit set of the first trimming code TR_CDbased on a logic bit set of some bits, among the bits included in the trimming control signal TM_CNT, and may set a logic bit set of the second trimming code TR_CDbased on a logic bit set of some other bits, among the bits included in the trimming control signal TM_CNT. The first trimming operation may be performed in a way that a resistance value of a first trimming resistor_is adjusted by the first trimming code TR_CDin order to adjust the voltage level of a gate voltage VG so that an NMOS transistorthat drives a variable voltage VTEMP operates in an inversion area. The second trimming operation may be performed in a way that a resistance value of a second trimming resistor_that is connected to a node ndconnected to a source terminal of the NMOS transistoris adjusted by the second trimming code TR_CD. However, a variable voltage generation circuitA, illustrated in, is merely an example, and the present disclosure is not limited thereto. For example, the variable voltage generation circuitA may be constructed as a circuit capable of linearly adjusting the voltage level of a variable voltage through a trimming operation based on a variable resistor. The external devicemay transmit a ground voltage VSS to the temperature sensorthrough a fourth transmission line_that is connected between the fourth control pin_and the fourth sensor pin_. The external devicemay be implemented by a controller (not illustrated) or a test device (not illustrated).

is a circuit diagram of a temperature sensorA according to an example of the temperature sensor. As illustrated in, the temperature sensorA may include a source reference voltage generation circuit (SVREF GEN), a driving voltage regulator (VDRV REG), a trimming code generation circuit (TR_CD GEN), a temperature reference voltage generation circuit (TVREF GEN), a variable voltage generation circuit (VTEMP GEN), and a temperature sensing signal generation circuit (T_COMP GEN).

The source reference voltage generation circuitmay generate a source reference voltage SVREF by being supplied with the power supply voltage VDD and the ground voltage VSS. The source reference voltage generation circuitmay include multiple resistor elements (not illustrated) that are connected in series between the power supply voltage VDD and the ground voltage VSS and may generate the source reference voltage SVREF by dividing the power supply voltage VDD based on resistance values of the resistor elements.

The driving voltage regulatormay receive the source reference voltage SVREF from the source reference voltage generation circuit. The driving voltage regulatormay generate a driving voltage VDRV based on the source reference voltage SVREF, the high voltage VPP_E, and the ground voltage VSS. The driving voltage regulatormay be implemented with a low drop out (LDO) regulator and may generate the driving voltage VDRV that is set so that a change in the voltage level of the driving voltage VDRV is small. For example, based on a result of a comparison between the source reference voltage SVREF and a voltage generated by dividing the driving voltage VDRV, the driving voltage regulatormay generate the driving voltage VDRV in a way to control the driving voltage VDRV to be driven to the high voltage VPP_E. The driving voltage VDRV may be driven to the high voltage VPP_E that has been set to have a higher voltage level than the power supply voltage VDD so that the voltage level of the driving voltage VDRV can be set at a preset voltage level rapidly and stably.

The trimming code generation circuitmay generate the first trimming code TR_CDand the second trimming code TR_CDbased on a trimming control signal TM_CNT. The trimming code generation circuitmay generate the first trimming code TR_CDand the second trimming code TR_CD, the logic bit set of each being determined based on a logic bit set of bits that are included in the trimming control signal TM_CNT. For example, the trimming code generation circuitmay set the logic bit set of the first trimming code TR_CDbased on a logic bit set of some bits, among bits included in the trimming control signal TM_CNT, and may set a logic bit set of the second trimming code TR_CDbased on a logic bit set of some other bits, among the bits included in the trimming control signal TM_CNT.

The temperature reference voltage generation circuitmay receive the driving voltage VDRV from the driving voltage regulator. The temperature reference voltage generation circuitmay generate a temperature reference voltage TVREF by being supplied with the driving voltage VDRV and the ground voltage VSS. The temperature reference voltage generation circuitmay include multiple resistor elements (_to_L in) that are connected in series between the driving voltage VDRV and the ground voltage VSS and may generate the temperature reference voltage TVREF by dividing the driving voltage VDRV based on resistance values of the resistor elements (_to_L in).

The variable voltage generation circuitmay receive the driving voltage VDRV from the driving voltage regulatorand may receive the first trimming code TR_CDand the second trimming code TR_CDfrom the trimming code generation circuit. Based on the driving voltage VDRV, the ground voltage VSS, the first trimming code TR_CD, and the second trimming code TR_CD, the variable voltage generation circuitmay perform the first trimming operation and the second trimming operation and may generate the variable voltage VTEMP. The first trimming operation may be performed in a way that a resistance value of the first trimming resistor (_in) is adjusted by the first trimming code TR_CDin order to adjust the voltage level of the gate voltage (VG in) so that the NMOS transistor (in) that drives the variable voltage (VTEMP in) operates in the inversion area. The second trimming operation may be performed in a way that a resistance value of the second trimming resistor (_in) that is connected to the node (ndin) that is connected to the source terminal of the NMOS transistor (in) is adjusted by the second trimming code TR_CD. In response to the second trimming operation, the variable voltage generation circuitmay adjust the gate voltage (VG in) by the first trimming resistor (_in), the resistance value of which is trimmed in response to the first trimming operation, and may generate the variable voltage VTEMP that is driven to the driving voltage VDRV by the NMOS transistor (in) that is turned on by the gate voltage (VG in) in the state in which the resistance value of the second trimming resistor (_in) has been adjusted. The variable voltage generation circuitmay generate the variable voltage VTEMP, the voltage level of which is linearly changed for each sensing temperature. The sensing temperature may be defined as a temperature surrounding the place at which the temperature sensorA is disposed.

The temperature sensing signal generation circuitmay receive the temperature reference voltage TVREF from the temperature reference voltage generation circuitand may receive the variable voltage VTEMP from the variable voltage generation circuit. The temperature sensing signal generation circuitmay generate a temperature sensing signal T_COMP based on the temperature reference voltage TVREF and the variable voltage VTEMP. For example, the temperature sensing signal generation circuitmay generate the temperature sensing signal T_COMP having a logic level set at a first logic level when the temperature reference voltage TVREF has a lower voltage level than the variable voltage VTEMP and may generate the temperature sensing signal T_COMP having a logic level set at a second logic level when the temperature reference voltage TVREF has a voltage level equal to or higher than the variable voltage VTEMP. The temperature sensing signal T_COMP may be generated based on the variable voltage VTEMP having an improved characteristic in which the variable voltage VTEMP is linearly changed in response to a change in the sensing temperature. Accordingly, the matching of the temperature sensing signal T_COMP can be improved, and a characteristic of various internal operations that are controlled by the temperature sensing signal T_COMP can be improved. For example, since the temperature sensing signal T_COMP is generated at a preset sensing temperature, timing of internal operations that need to be performed for each sensing temperature can be accurately set.

is a circuit diagram of a driving voltage regulatorA according to an example of the driving voltage regulator. As illustrated in, the driving voltage regulatorA may include a comparator, a driving element, and a voltage divider. The comparatormay generate a comparison pulse COMP by comparing the source reference voltage SVREF with a voltage divided by the voltage divider. The comparatormay generate the comparison pulse COMP having a logic low level when the voltage divided by the voltage dividerhas a lower voltage level than the source reference voltage SVREF. The driving elementmay drive the driving voltage VDRV to the high voltage VPP_E based on the comparison pulse COMP. The driving elementmay generate the driving voltage VDRV having a voltage level set as a preset voltage level rapidly and stably, by driving the driving voltage VDRV to the high voltage VPP_E, which has been set to have a higher voltage level than the power supply voltage VDD, when the comparison pulse COMP has a logic low level. The voltage dividermay include resistor elements_and_, divide the driving voltage VDRV, and output a divided voltage to a node nd. When the resistor elements_and_have the same resistance values, the voltage dividermay output, to the node nd, a voltage having a voltage level set to be half the voltage level of the driving voltage VDRV.

is a circuit diagram of a temperature reference voltage generation circuitA according to an example of the temperature reference voltage generation circuit. As illustrated in, the temperature reference voltage generation circuitA may include the resistor elements_to_L that are connected in series between the driving voltage VDRV and the ground voltage VSS. The temperature reference voltage generation circuitA may generate the temperature reference voltage TVREF by dividing the driving voltage VDRV based on resistance values of the resistor elements_to_L.

is a circuit diagram of a variable voltage generation circuitA according to an example of the variable voltage generation circuit. As illustrated in, the variable voltage generation circuitA may include resistor elements_,_, the NMOS transistor, the first trimming resistor_, and the second trimming resistor_. The resistor element_may be connected between the driving voltage VDRV and a node nd. The first trimming resistor_may be connected between the node ndand the ground voltage VSS. A resistance value of the first trimming resistor_may be adjusted by the first trimming code TR_CD. The gate voltage VG that is output from the node ndmay be set based on a ratio of a resistance value of the resistor element_and a resistance value of the first trimming resistor_, which is adjusted by the first trimming code TR_CD. The voltage level of the gate voltage VG may be set so that the NMOS transistoroperates in the inversion area. Accordingly, when the sensing temperature is changed, the variable voltage VTEMP can be linearly changed. In the present embodiment, a gate source voltage VGS, that is, a voltage difference between the gate voltage VG and a voltage at the node ndthat is connected to the source terminal of the NMOS transistor, may be set to 0.4 V to 0.6 V. The resistor element_may be connected between the driving voltage VDRV and a node ndfrom which the variable voltage VTEMP is output. The NMOS transistormay be turned on by the gate voltage VG and may control the variable voltage VTEMP to be driven by the driving voltage VDRV. The second trimming resistor_may be connected between the node ndthat is connected to the source terminal of the NMOS transistorand the ground voltage VSS. A structure for a common source amplifier having a degeneration resistor is formed by the second trimming resistor_that is connected to the source terminal of the NMOS transistor. Accordingly, when the gate voltage VG of the NMOS transistoris changed, the variable voltage VTEMP can be linearly changed. The variable voltage generation circuitA may perform the first trimming operation of adjusting the resistance value of the first trimming resistor_by the first trimming code TR_CDin order to adjust the voltage level of the gate voltage VG so that the NMOS transistorthat drives the variable voltage VTEMP operates in the inversion area. The variable voltage generation circuitA may perform the second trimming operation of adjusting, to the second trimming code TR_CD, a resistance value of the second trimming resistor_that is connected to the node ndconnected to the source terminal of the NMOS transistor. The variable voltage generation circuitA may adjust the ratio of the variable voltage VTEMP that is changed when the sensing temperature is changed by the second trimming operation. For example, as the resistance value of the second trimming resistor_is increased by the second trimming operation, the ratio of the variable voltage VTEMP that is changed when the sensing temperature is changed may be set to be decreased.

is a graph illustrating an area in which the NMOS transistoroperates.

The NMOS transistormay operate in another area based on the gate voltage VG. When the gate voltage VG is a flat band voltage or less, the NMOS transistormay operate in a depletion area in which charges are accumulated on a boundary surface between metal and silicon. The flat band voltage may be set to a voltage capable of flattening an energy band of the NMOS transistor. When the gate voltage VG is higher than the flat band voltage, the NMOS transistormay operate in the inversion area in which a channel is formed because the state in which metal and silicon have been doped is inverted. The inversion area may include a weak inversion area and a strong inversion area based on a degree that the state in which metal and silicon have been doped has been inverted. Referring to, when the gate source voltage VGS is 0.2 V to 0.3 V, the NMOS transistormay operate in the depletion area. When the gate source voltage VGS is 0.4 V to 0.6 V, the NMOS transistormay operate in the inversion area. It may be seen that as the gate source voltage VGS is changed when the NMOS transistoroperates in the inversion area, a change in the drain current ID of the NMOS transistormay be linearly increased. More specifically, when the NMOS transistoroperates in the inversion area rather than the depletion area, a change in the drain current ID for a change in the gate source voltage VGS may be increased. When the gate source voltage VGS is changed, the drain current ID may be linearly changed.

is a circuit diagram of a temperature sensing signal generation circuitA according to an example of the temperature sensing signal generation circuit. As illustrated in, the temperature sensing signal generation circuitA may receive the temperature reference voltage TVREF through a positive terminal “+” of the temperature sensing signal generation circuitA and may receive the variable voltage VTEMP through a negative terminal “−” of the temperature sensing signal generation circuitA. The temperature sensing signal generation circuitA may generate the temperature sensing signal T_COMP by comparing the temperature reference voltage TVREF with the variable voltage VTEMP. The temperature sensing signal generation circuitA may generate the temperature sensing signal T_COMP having a logic level set based on a result of the comparison between the temperature reference voltage TVREF and the variable voltage VTEMP.

is a table for describing an operation of the temperature sensing signal generation circuitA. As illustrated in, the temperature sensing signal generation circuitA may generate the temperature sensing signal T_COMP having a logic level set at a logic high level “H” when the variable voltage VTEMP has a voltage level equal to or lower than the voltage level of the temperature reference voltage TVREF and may generate the temperature sensing signal T_COMP having a logic level set as a logic low level “L” when the variable voltage VTEMP has a higher voltage level than the temperature reference voltage TVREF.

The embodiments of the present disclosure have been described so far. A person having ordinary knowledge in the art to which the present invention pertains will understand that the present invention may be implemented in a modified form without departing from an intrinsic characteristic of the present disclosure. Accordingly, the disclosed embodiments should be considered from a descriptive viewpoint, not from a limitative viewpoint. The range of the present disclosure is described in the claims not the aforementioned description, and all differences within an equivalent range thereof should be construed as being included in the present disclosure.