A low-dropout regulator with an automatic adjustment stability compensation circuit is provided. The low-dropout regulator includes an analog positive power supply; a compensation circuit; a PMOS; an error amplifier; a reference voltage; a load capacitance; a soft start circuit; a first resistor; and a second resistor. The drain of the PMOS is connected to one end of the first resistor and a node is formed at the connection to output voltage; the gate of the PMOS is connected to the output of the error amplifier and compensation circuit; the other end of the first resistor is connected in series with the second resistor, and the other end of the second resistor is grounded; the non-inverting input end of the error amplifier is connected to the reference voltage, and the inverting input end is connected to the one of the two resistors.
Legal claims defining the scope of protection, as filed with the USPTO.
. A low-dropout regulator with an automatic adjustment stability compensation circuit, the low-dropout regulator comprising:
. The low-dropout regulator of, wherein the PMOS can be replaced with a n-type metal oxide semiconductor field effect transistor (NMOS).
. The low-dropout regulator of, wherein the low-dropout regulator is suitable for a variety of different load capacitance needs.
Complete technical specification and implementation details from the patent document.
This application claims the priority benefit of Taiwan application no. 112117825, filed on May 12, 2023, the full disclosure of which is incorporated herein by reference.
The present invention is related to an application of the existing soft start circuit of the low dropout regulator to detect the soft start time to estimate the size of the load capacitance, and then change the compensation circuit to improve the stability of the low dropout regulator.
When using a low-dropout regulator (LDO), it can be operated with or without an external capacitor. However, the capacitance of the external capacitor will also change greatly, which can make it difficult to design the stability of the low-dropout regulator.
A first aspect of this invention is to meet the needs of different customers using low dropout regulator circuits and can output stable voltage without oscillation under different applications.
A second aspect of this invention is to complete the normal operation of the low-dropout regulator without additional power consumption.
A third aspect of this invention is to change the compensation circuit to achieve the optimization of the stability of the low dropout regulator.
To achieve the above aspects and other aspects, this invention provides a low-dropout regulator with auto-adjusting stability compensation circuit. The low-dropout regulator comprises an analog virtual device driver; a compensation circuit; a P-type metal oxide semiconductor field effect transistor; an error amplifier; a voltage reference; a load capacitance; a soft start circuit; a first resistor; and a second resistor. Wherein a source of the PMOS is connected to the analog virtual device driver. A drain of the PMOS is connected to one end of the first resistor to form a node at the connection to output voltage. A gate of the PMOS is connected to the output of the error amplifier and the compensation circuit. The other end of the first resistor connected in series with the second resistor, and the other end of the second resistor is grounded. The load capacitance is connected in parallel with the first resistor and the second resistor. A non-reverse input terminal of the error amplifier is connected to the reference voltage, the reverse phase input terminal is connected to the connection point between the first resistor and the second resistor. A negative power supply terminal of the error amplifier is connected to the compensation circuit. The soft start circuit is signally connected to the compensation circuit.
The present disclosure discloses a low-dropout regulator with auto-adjusting stability compensation circuit.is a circuit structure diagram of the present disclosure. In, the low-dropout regulator (LDO)comprises an analog virtual device driver AVDD, also known as virtual voltage; a compensation circuit; a P-type metal oxide semiconductor field effect transistor PMOS; an error amplifier; a voltage reference VREF; a load capacitance CL; a soft start circuit; a first resistor R; and a second resistor R. The source of the P-type metal oxide semiconductor field effect transistor PMOS is connected to the analog virtual device driver AVDD. The drain of the P-type metal oxide semiconductor field effect transistor PMOS is connected to one end of the first resistor Rto form a nodeat the connection site to output voltage. The gate of the P-type metal oxide semiconductor field effect transistor PMOS is connected to the output of the error amplifierand the compensation circuit. The other end of the first resistor Ris connected in series with the second resistor R, and the other end of the second resistor Ris grounded. The load capacitance CL is connected in parallel with the first resistor Rand the second resistor R. A non-reverse input terminal of the error amplifieris connected to the reference voltage VREF. A reverse phase input terminal is connected to a connection point between the first resistor Rand the second resistor R. A negative power supply terminal of the error amplifier is connected to the compensation circuit. The soft start circuitis signally connected to the compensation circuit.
is a diagram of the change in soft start time caused by different load capacitance CL of the present disclosure. In, the vertical axis represents the output voltage (Vout), and the horizontal axis represents the soft start time (Trdy). When the output voltages (Vout) of the compensation circuitare the same but the load capacitance values are different (such as CL˜CL), the soft start time of the compensation circuitis correspondingly changed (such as T˜T). By detecting the soft start time of the LDO through the soft start circuit, the load capacitance (CL) value range of the LDOcan be determined, and then the LDO compensation circuitis controlled based on the load capacitance value range, to improve the stability of the LDO. After the LDO soft-start procedure is completed, the soft-start circuitcan be automatically turned off, or the LDO soft-start time detection function of the soft-start circuitcan be turned off to avoid unnecessary power consumption.
is a circuit structure diagram according to another embodiment of this invention. In, the P-type metal oxide semiconductor effect transistor PMOS inis replaced with an N-type metal oxide semiconductor effect transistor NMOS. The rest of the structure is as stated above, and the operation mode and functions are the same as those of the embodiment shown inand will not be described again here.
is a detailed circuit diagram of the compensation circuit of the present disclosure. Two embodiments are provided for explanation of the LDO compensation circuit. When the first switch SWis turned on and the second switch SWis turned off, the first embodiment of the compensation circuitcomprises a first capacitor C, a second capacitor Cand a first switch SW, where Cis an adjustable capacitor. If the detected load capacitance CL value is larger, the capacitance value of capacitor Ccan be reduced to perform compensation. When the first switch SWis turned off and the second switch SWis turned on, the second embodiment of the compensation circuitcomprises a first capacitor C, a third resistor R, and a second switch SW, where Cis an adjustable capacitor. If the detected load capacitance CL value is large, the capacitance value of Ccan be reduced to perform compensation.
The compensation circuitsof,andare only examples, and the compensation method of the LDO in the present disclosure is not limited to the above methods.
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March 31, 2026
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