Circuits for online adaptive DC offset correction and receivers

This application is a continuation application of International Patent Application No. PCT/CN2021/107418, filed on Jul. 20, 2021, and claiming the priority to Chinese Application No. 202110680221.8 filed on Jun. 18, 2021, the contents of all of which are incorporated herein by reference in their entirety.

Embodiments of the present disclosure relate to the field of circuit correction, in particular to circuits for online adaptive DC offset correction and receivers including the same.

With the development of integrated circuits, the architecture of on-chip zero-IF receivers is becoming more and more widely used. In a zero-IF receiver, the RF signal undergoes a frequency conversion by a mixer to obtain an analog baseband signal. The analog baseband signal is filtered by a low-pass filter and then enters the ADC to realize the conversion from analog to digital. In a zero-IF receiver, due to factors such as local oscillator feedthrough and low-pass filter device offset, the output signal of the low-pass filter not only has useful AC signals but also has a certain amount of DC components. Due to the existence of the DC component, the dynamic range of the entire receiving channel is greatly reduced. When the gain of the RF front-end of the receiver is large, the DC component may even cause the ADC to enter a saturated state, thereby causing the entire receiving channel to work abnormally.

Embodiments of the present disclosure provide circuits for online adaptive DC offset correction and receivers.

Embodiments of the present disclosure provide a circuit for online adaptive DC offset correction, which is applied to a zero-IF receiver. The circuit includes an analog adder circuit, an analog-to-digital conversion circuit, a DC detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit.

The analog adder circuit is configured to receive a first input signal generated by a zero-IF receiver and a second input signal generated by a digital-to-analog conversion circuit and generate a first output signal according to the first input signal and the second input signal.

The analog-to-digital conversion circuit is configured to receive the first output signal and perform analog-to-digital conversion on the first output signal to obtain a second output signal.

The DC detection circuit is configured to perform DC detection on the second output signal under the control of a detection control signal generated by an adaptive update signal generating circuit to generate a detection result.

The adaptive update signal generating circuit is configured to receive the detection result and generate an update control signal according to the detection result.

The output circuit is configured to receive the update control signal and generate a first mode selection signal according to the update control signal.

The mode selection circuit is configured to receive the first mode selection signal and generate a correction signal according to the first mode selection signal and a second mode selection signal, wherein the correction signal is used as an input signal of the digital-to-analog conversion circuit.

In some exemplary embodiments, the DC detection circuit includes a delay sub-circuit, a digital adder sub-circuit, a divider sub-circuit, and an accumulator sub-circuit.

The delay sub-circuit is configured to receive the second output signal and perform delay processing on the second output signal to generate a delayed signal.

The digital adder sub-circuit is configured to receive the delay signal and perform an addition operation on the second output signal and an output signal of the delay sub-circuit to generate an addition signal.

The divider sub-circuit is configured to receive the addition signal and perform division operation on the addition signal.

The accumulator sub-circuit is configured to receive the division signal and the update control signal and generate a detection result according to the division signal and the update control signal.

In some exemplary embodiments, the delay sub-circuit includes a plurality of delay elements connected in sequence.

In some exemplary embodiments, the accumulator sub-circuit includes an adder element and a unit delay element. The adder element includes a first input end and a second input end. The first input end is connected to an output end of the divider sub-circuit. The second input end is connected to the output end of the unit delay element. An output end of the adder element is connected to an input of the unit delay element.

In some exemplary embodiments, the DC detection circuit includes a reset circuit generating sub-circuit, a frequency division sub-circuit, an accumulator sub-circuit, a latch sub-circuit, and a divider sub-circuit.

In some exemplary embodiments, the reset circuit generating sub-circuit is configured to receive the detection control signal and generate a reset control signal according to the detection control signal.

In some exemplary embodiments, the frequency division sub-circuit is configured to receive the detection control signal and generate a high pulse signal according to the detection control signal.

In some exemplary embodiments, the accumulator sub-circuit is configured to receive the reset control signal and the second output signal and perform accumulation processing to generate an accumulation signal;

In some exemplary embodiments, the latch sub-circuit is configured to receive the high pulse signal and latch the accumulation signal based on the high pulse signal.

In some exemplary embodiments, the divider sub-circuit is configured to receive the high pulse signal and an output of the latch sub-circuit and perform a division operation to obtain the detection result.

In some exemplary embodiments, the accumulator sub-circuit includes an adder element and a unit delay element. The adder element includes a first input end and a second input end. The first input end is connected to an output end of the analog-to-digital conversion circuit. The second input end is connected to the output end of the unit delay element. The output end of the adder element is connected to the input end of the unit delay element.

In some exemplary embodiments, the update control signal includes a first control signal, a second control signal, and a third control signal.

In some exemplary embodiments, the adaptive update signal generating circuit includes a programmable timing sub-circuit, a latch sub-circuit with a setting function, and a comparator sub-circuit.

In some exemplary embodiments, the programmable timing sub-circuit is configured to generate a first control signal when timing exceeds a set threshold.

In some exemplary embodiments, the latch sub-circuit with a setting function is configured to receive the first control signal and latch the detection result according to the first control signal.

In some exemplary embodiments, the comparator sub-circuit is configured to receive the detection result and compare the detection result with a set threshold to generate a second control signal and a third control signal.

In some exemplary embodiments, the comparator sub-circuit is configured to generate a second control signal upon determining that the detection result exceeds a high threshold value and generate a third control signal upon determining that the detection result is lower than a low threshold value.

In some exemplary embodiments, the output circuit includes a decoder sub-circuit, a selection sub-circuit, and an accumulator sub-circuit.

In some exemplary embodiments, the decoder sub-circuit is configured to receive the update control signal and generate a selection control signal according to the update control signal.

In some exemplary embodiments, the selection sub-circuit is configured to receive the selection control signal and generate a selection signal according to the selection control signal.

In some exemplary embodiments, the accumulator sub-circuit is configured to accumulate the selection signal to generate the first mode selection signal.

In some exemplary embodiments, the accumulator sub-circuit includes an adder element and a unit delay element. The adder element includes a first input end and a second input end. The first input end first input end is connected to an output end of the selection sub-circuit. The second input end is connected to an output end of the unit delay element. The output end of the adder element is connected to the input end of the unit delay element.

Embodiments of the present disclosure also provide a zero-IF receiver, which includes the above-mentioned circuit for online adaptive DC offset correction.

As mentioned above, the circuit for online adaptive DC offset correction provided by embodiments of the present disclosure may have one or more of the following beneficial effects.

A circuit for online adaptive DC offset correction according to embodiments of the present disclosure, which is applied to a zero-IF receiver and includes: an analog adder circuit, an analog-to-digital conversion circuit, a DC detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit. The analog adder circuit is configured to receive a first input signal generated by a zero-IF receiver and a second input signal generated by a digital-to-analog conversion circuit and generate a first output signal according to the first input signal and the second input signal. The analog-to-digital conversion circuit is configured to receive the first output signal and perform analog-to-digital conversion on the first output signal to obtain a second output signal. The DC detection circuit is configured to perform DC detection on the second output signal under the control of a detection control signal generated by an adaptive update signal generating circuit to generate a detection result. The adaptive update signal generating circuit is configured to receive the detection result and generate an update control signal according to the detection result. The output circuit is configured to receive the update control signal and generate a first mode selection signal according to the update control signal. The mode selection circuit is configured to receive the first mode selection signal and generate a correction signal according to the first mode selection signal and a second mode selection signal, wherein the correction signal is used as an input signal of the digital-to-analog conversion circuit.

The circuit for online adaptive DC offset correction according to embodiments of the present disclosure may automatically detect the magnitude of the DC offset value in the input signal, and adaptively compensate the DC offset value, thereby eliminating the influence of the DC offset on the performance of the receiver. The circuit may adaptively change the adjustment rate during the compensation process, and perform DC compensation quickly in the case of a large offset and slowly update the DC value in the case of a small offset. Using this adaptive method, the correction circuit may achieve a fast convergence speed, and may also minimize the impact on the signal chain.

Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

It should be noted that the figures provided in the following embodiments are only schematically illustrating the basic ideas of the present disclosure. Only the components related to the present disclosure are shown in the figures. The number, shape, and size of the components may not be shown as they are in actual implementation. During actual implementation, the type, quantity, and proportion of each component can be changed arbitrarily, and the layout of components may also be more complicated.

Traditional DC offset circuits/algorithms are usually divided into foreground correction algorithms and online correction algorithms. The foreground correction algorithm usually corrects the circuit when the circuit is turned off or when the receiving link is idle (TDD mode). This kind of correction method has high correction accuracy, but the correction circuit cannot perform correction during normal receiving work, which limits the use of the circuit. In addition, when the working environment changes, the performance of the foreground correction algorithm will decrease. Another correction method, i.e., online correction, overcomes the shortcomings of the working mode of the foreground correction and enables the algorithm to correct the DC offset while the algorithm is working normally. However, this method usually introduces an additional circuit on the main signal chain, which has a certain influence on the main signal channel during real-time correction.

In order to overcome the shortcomings of the above mentioned methods. Exemplary embodiments of the present disclosure propose a circuit for online adaptive DC offset correction. In some exemplary embodiments, the circuit includes an analog adder circuit, a digital-to-analog conversion circuit, a DC detection circuit, an adaptive update signal generating circuit, an output circuit, a mode selection circuit, and the like. In some exemplary embodiments, the circuit receives an input signal with a DC component, detects the DC component, obtains a compensation value through calculation, converts the compensation value into an analog signal, and feeds it back to the input terminal of the signal chain, thereby eliminating the DC component of the signal itself. During the compensation process, the circuit may adaptively adjust the rate of the compensation according to the DC offset value in the input signal. Thus, DC compensation may be performed quickly under the condition of a large DC offset, and DC value may be updated slowly in the situation of a small DC offset. Therefore, the circuit may achieve a fast convergence speed, and may also minimize the impact on the signal chain.

is a functional block diagram of a circuit for online adaptive DC offset correction according to exemplary embodiments of the present disclosure. The circuit for online adaptive DC offset correction includes an analog adder circuit, an analog-to-digital conversion circuit, a DC detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit.

The analog adder circuit is configured to receive a first input signal generated by a zero-IF receiver and a second input signal generated by a digital-to-analog conversion circuit and generate a first output signal based on the first input signal and the second input signal.

The analog-to-digital conversion circuit is configured to receive the first output signal and perform analog-to-digital conversion on the first output signal to obtain a second output signal.

The DC detection circuit is configured to perform DC detection on the second output signal under the control of a detection control signal generated by an adaptive update signal generating circuit to generate a detection result.

The adaptive update signal generating circuit is configured to receive the detection result and generate an update control signal according to the detection result.

The output circuit is configured to receive the update control signal and generate a first mode selection signal according to the update control signal.