Package substrate having embedded electronic component in a core of the package substrate

The present disclosure generally relates to a substrate, and more particularly, to a package substrate having an embedded electronic component mounted in a core of the package substrate, and methods of making the package substrate.

Integrated circuit (IC) technology has achieved great strides in advancing computing power through miniaturization of electrical components. An IC may be implemented in the form of an IC chip that has a set of circuits integrated thereon. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where various power and signal nodes of the one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed in a package substrate of the IC package. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing techniques can be used to implement complex devices, such as multi-electronic component devices and system on a chip (SOC) devices, which may include multiple function blocks, with each function block designed to perform a specific function, such as, for example, a microprocessor function, a graphics processing unit (GPU) function, a communications function (e.g., Wi-Fi, Bluetooth, and other communications), and the like.

In some implementations, embedded electronic components, such as deep trench capacitors, have been incorporated in IC packaging for performance improvement and package size reduction. One factor driving the use of such embedded electronic components is the desire for obtaining small form factor products with equivalent or better electrical performance than their larger electronic components counterparts. Depending on the size and/or thickness of the package substrate and the size and/or the process node of the IC Chip carried thereon, the process for embedding an electronic component in a package substrate in one packaging task may not be suitable for another packaging task.

Accordingly, there is a need for improved methods for embedding an electronic component in a substrate, such as a package substrate, that may be suitable for a broader variety of packaging tasks.

The following presents a simplified summary relating to one or more aspects disclosed herein. Thus, the following summary should not be considered an extensive overview relating to all contemplated aspects, nor should the following summary be considered to identify key or critical elements relating to all contemplated aspects or to delineate the scope associated with any particular aspect. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects relating to the mechanisms disclosed herein in a simplified form to precede the detailed description presented below.

In an aspect, a substrate includes a core having an upper planar surface and an interior planar surface; a cavity extending at least partially through the upper planar surface of the core to the interior planar surface of the core; an electronic component mounted in the cavity, the electronic component including an upper planar surface having one or more electronic component terminals, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

In an aspect, an electronic device includes a substrate including a core having an upper planar surface and an interior planar surface; a cavity extending at least partially through the upper planar surface of the core to the interior planar surface of the core; an electronic component in the cavity, the electronic component including an upper planar surface having one or more electronic component terminals, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

In an aspect, a method of forming a substrate includes forming a cavity extending from an upper planar surface of a core to an interior planar surface of the core; inserting an electronic component in the cavity so that an upper planar surface of the electronic component having one or more electronic component terminals is supported by the interior planar surface of the core, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core; and forming an upper metallization structure over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternate aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the illustrative embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

In certain described example implementations, instances are identified where various component structures and portions of operations can be taken from known, conventional techniques and then arranged in accordance with one or more exemplary embodiments. In such instances, internal details of the known, conventional component structures and/or portions of operations may be omitted to help avoid potential obfuscation of the concepts illustrated in the illustrative embodiments disclosed herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising.” “includes,” and/or “including.” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

is a cross-sectional view of a first example substratewith an embedded electronic component, according to aspects of the disclosure. In this example, the substrateincludes a corehaving a cavitythat extends entirely through the core. An electronic componentis disposed within the cavity. The electronic componenthas an upper surfacewith metal terminalsthat provide an electrical connection to the electronic component. In accordance with various aspects of the disclosure, the electronic componentmay be one or more of an active electronic component, a passive electronic component (e.g., a deep trench capacitor (DTC)), a die, etc.

In accordance with various aspects of the disclosure, the substrates described herein (e.g., substrate) that include a core and an embedded electronic component are directed to package substrates. A package substrate is the part of an integrated circuit package that gives the board its mechanical strength and allows it to connect with external devices. Such package substrates are to be distinguished from other substrates, such as the substrates that may be included in the embedded electronic component itself, dies including substrates (e.g., silicon substrates or other similar electronic devices).

The substratefurther includes a plurality of dielectric layersand corresponding patterned metallization layersoverlying an upper surfaceof the core. A patterned metallization layeris disposed at the upper surfaceof the coreto provide an electrical connection between the metal terminalsof the electronic componentand the patterned metallization layers. In an aspect, the same dielectric resin material as used in forming the plurality of dielectric layersmay be used in the regionsof the cavitybetween the sidewalls of the electronic componentand the sidewalls of the cavity. Dispensing a dielectric resin over the electronic componentand in the regionsassists in securing the electronic componentwithin the cavityso that the metal terminalsremain electrically connected with corresponding portions of the patterned metallization layeronce the dielectric resin is cured.

In an aspect, an uppermost patterned metallization layerat an upper surfaceof the substrateis connected to a plurality of metal terminals. The patterned metallization layersprovide a conductive path between the metal terminalsof the electronic componentand the metal terminals. In an aspect, the plurality of metal terminalsmay be configured for connection to an electronic package of a surface-mounted device (not shown in).

In an aspect, a further plurality of dielectric layersand corresponding patterned metallization layersoverlie a lower surfaceof the core. Here, a patterned metallization layeris disposed over the lower surfaceof the core. A lowermost patterned metallization layerat a lower surfaceof the substrateis connected to a plurality of metal terminals. The patterned metallization layersprovide a conductive path to the metal terminals. In an aspect, the plurality of metal terminalsmay be configured for connection to an electronic package of a further surface-mounted device (not shown in) or to a circuit board for connection with other devices.

In, the electronic componenthas a height Hthat is substantially the same as the thickness Hof the core. During manufacture of the substrate, the electronic componentis inserted in the cavitybefore a dielectric resin is injected to fill the regionsbetween the cavityand electronic component. During insertion, the electronic componentis carefully aligned within the cavityto ensure that the metal terminalsproperly contact and electrically bond with the corresponding portions of the patterned metallization layer. Additionally, the injection of the dielectric resin in the regionsshould be undertaken with care so as not to disturb the initial alignment of the electronic component. In an aspect, the dielectric resin, once cured, secures the electronic componentat its proper location within the cavity.

In scenarios in which the height Hof the electronic componentand thickness Hof the coreare substantially the same, the insertion of the electronic componentin the cavityand subsequent injection and cure of the dielectric resin may be implemented using the processing technology as described with reference to. In an example, the height Hof the electronic component and the thickness Hof the coreinmay each be equal to or less than about 760 micrometers.

Although the structure of the substrateshown inhas been suitable for use in many high-performance applications (e.g., compute and automotive applications), current trends are directed to applications requiring substrates having larger body sizes. However, substrates having large bodies present unique design and manufacturing issues that must be addressed (e.g., substrate warpage, a need for larger cavity sizes, a need for larger keep-out zones, etc.). These issues may be addressed, at least in part, by employing thick cores in the design and manufacture of such substrates. For example, warpage control is more easily achieved with thick cores than with thin cores. Additionally, the need for larger cavity sizes and keep-out zones can be met by employing such thick cores.

However, substrates employing thick cores may be difficult to manufacture using the same packaging technologies that are used in manufacturing substrates having thin cores of the type described in connection with. With thick cores, there is a significant gap between the electronic component and the cavity resulting from the increased depth of the cavity compared to the height of the electronic component (e.g., the thick core has a thickness that is greater than the height of the electronic component). In such thick core scenarios, it may be difficult or impossible to fill the gap surrounding the electronic component with the dielectric resin in a manner that maintains the proper initial alignment of the electronic component in the cavity during the resin injection. Further, it may be difficult or impossible to inject a sufficient amount of dielectric resin in the gap to secure the electronic component at its desired position once the dielectric resin is cured.

is a cross-sectional view of an example substratewith an embedded electronic component, according to aspects of the disclosure. In this example, it is assumed that the substratehas been manufactured using the same processing operations as used to manufacture the substrateshown in. For purposes of simplicity, certain reference numbers used inhave also been used to designate similar elements in.

In the example shown in, the substratediffers from the substrateofin that the substrateemploys a thick corehaving a thickness Hthat is greater than the height Hof the electronic component. In accordance with certain aspects of the disclosure, the thickness His greater than about 760 micrometers and, as such, is thicker than the electronic componentand its thin corecounterpart. In certain scenarios, the thick core may have a thickness that is substantially greater than 760 micrometers (e.g., 820 micrometers, 1240 micrometers, etc.).

The substratehas a cavitythat is substantially deeper than the cavityof the substrate. As such, it becomes more difficult to align the metal terminalswith the corresponding portions of the patterned metallization layerduring the initial placement of the electronic componentwithin the cavity. Initial misalignment of the electronic componentmay fail to establish an electrical connection between the metal terminalsand corresponding portions of the patterned metallization layer. Additionally, it becomes challenging to correctly fill the cavity(e.g., particularly including the extended regions of the cavity) with an amount of dielectric resin that, once cured, properly surrounds and secures the electronic componentin place within the cavity. An insufficient fill of the cavitywith the dielectric resin can lead to subsequent delamination of the electronic componentfrom electrical contact with the corresponding portions of the patterned metallization layeronce the substrateis incorporated in a more extensive electronic system (e.g., automobile sensors/computers, mobile devices, or any other type of electronic device as described herein). In, an instance of delamination is shown at region, where some of the metal terminalshave pulled away from the corresponding portions of the patterned metallization layer.

Certain aspects of the disclosure are implemented with a recognition of the problems associated with using existing processing technologies to manufacture substrates having certain types of cores (e.g., thick cores) and/or certain types of electronic component (e.g., deep trench capacitors). In accordance with certain aspects of the disclosure, the electronic component may be embedded in the substrate within a cavity formed in an upper planar surface of a core to an interior planar surface of the core. In an aspect, the electronic component is supported by the interior planar surface of the core so that an upper planar surface of the electronic component on which the electronic component contacts are located is level with the upper planar surface of the core. This architecture allows the same upper face routing of the electronic component contacts (e.g., as shown in) without the embedded electronic component support and delamination issues associated with a cavity extending completely through the core (e.g., as shown in). In an aspect, the cavity may be filled with a fill material, such as a dielectric resin, to secure the electronic component within the cavity. The fill material may be deposited in the cavity without voids that may otherwise lead to failure of the substrate. In accordance with certain aspects of the disclosure, the thickness of the core is no longer a limiting factor that needs to be considered when embedding the electronic component in the substrate.

According to certain aspects of the disclosure, the electronic component may be a DTC.is a cross-sectional view of an example DTC, according to aspects of the disclosure. In, a capacitoris deposited in trenchesof an insulatoron a substrate. The capacitormay include a metal layer, a dielectric layer, and a metal layer. The dielectric layerseparates the metal layerfrom the metal layer. The metal layers,form electrodes of the capacitorand may be connected to terminals at, for example, a surface (see, e.g., the upper surfacewith metal terminalsof electronic componentshown in). In some scenarios, the capacitors are formed from an array of deep trenches in a substrate and filled with an electrical insulator (e.g., a dielectric) between layers of electrodes. In some scenarios, the capacitors are attached on the land side under in integrated circuit die shadow (land-side capacitor: LSC) or adjacent to the die on the die side (die-side capacitor: DSC).

is a cross-sectional of view of an example substrate, according to aspects of the disclosure. In this example, the substrateincludes an electronic componenthaving a lower planar surfaceand an upper planar surface. The upper planar surfaceof the electronic componentincludes one or more electronic component terminalsproviding an electrical connection with the electronic component.

The substratefurther includes a corehaving a lower planar surface(e.g., a first planar surface), an upper planar surface(e.g., a second planar surface), and an interior planar surface. A cavityis formed in the upper planar surfaceof the coreand extends through at least a portion of the coreto the interior planar surfaceof the core. The interior planar surfaceof the coremay be an interior portion of the core. The lower planar surfaceof the electronic componentfaces the interior planar surface, which either directly supports the electronic componentor indirectly supports the electronic componentthrough an intermediate layer(e.g., an adhesive layer). The depth of Hthe cavityis substantially the same dimension as the height Hof the electronic componentas measured between the upper planar surfaceand lower planar surfaceof the electronic component. As such, the upper planar surfaceof the electronic componentis substantially level with the upper planar surfaceof the core, as shown at dashed line. In an aspect, the cavityis dimensioned so that it may be filled with a filler material, such as a dielectric resin, without voids. This configuration allows the electronic componentto be connected using the same upper face connection configuration as shown inwhile also being mounted at a fixed position within the cavityso as to limit the chances of delamination of the electronic componentfrom connection with the other layers of the substrate. If the intermediate layer(e.g., adhesive layer) is used, the thickness of the intermediate layershould be such that the upper planar surface of the electronic componentstill remains level with the upper planar surface of the core.

In an aspect, the coremay include a patterned metallization layeron the upper planar surface. In the example shown in, the patterned metallization layermay be connected to the one or more electronic component terminals. A patterned metallization layermay also be disposed over the lower planar surfaceof the core.

According to certain aspects of the disclosure, the substratemay include an upper metallization structureconfigured to provide one or more conductive paths from the one or more electronic component terminalsto one or more upper metal terminalsof the upper metallization structure. In the example shown in, the upper metallization structureincludes one or more dielectric layersdisposed over the upper planar surfaceof the core. Although the dielectric layersare shown inas separate layers, it will be understood that multiple dielectric layers may be fused during the manufacturing process so as to appear and function as a single dielectric structure. Further, it will be understood that different layers of the dielectric layersmay be formed from different dielectric materials during the manufacturing process. In an aspect, different dielectric materials for the different dielectric layers may be used when one or more of the dielectric layersare to have a different dielectric constant than another of the dielectric layers.

In accordance with certain aspects of the disclosure, each of the dielectric layersis associated with a corresponding patterned metallization layer. One or more metal via structures may be formed through the dielectric layers. The metal via structures provide an electrically conductive path between the one or more electronic component terminalsof the electronic componentand the metal terminalsformed by an upper metallization layer of the upper metallization structure. In accordance with certain aspects of the disclosure, the metal terminalsmay be configured for connection to an electronic circuit package (not shown in) mounted at the upper surface of the substrate.

As noted, the cavitymay be filled with the filler materialto mount the electronic componentwithin the cavity. In an aspect, the filler materialmay completely fill the cavityso that the entirety of the electronic componentis enclosed by the filler material. In an aspect, the filler materialmay be comprised of the same dielectric material used to form the dielectric layers. Again, it will be understood that the filler materialin the cavitymay be fused with the dielectric layersso as to appear and function as a single dielectric structure that surrounds the electronic component. Further, it will be understood that the filler materialmay comprise a material other than the dielectric material used to form the dielectric layers.

In an aspect, substratemay include a lower metallization structurehaving a further set of one or more dielectric layersand a corresponding set of patterned metallization layersdisposed over the lower planar surfaceof the core. As shown, the dielectric layersmay separate the patterned metallization layersfrom one another. One or more metal via structures may extend between the patterned metallization layersand connect with metal terminalsat a lowermost patterned metallization layerat a lower surface of the substrate. In accordance with various aspects of the disclosure, the metal terminalsmay be configured for mounting the substrateto another substrate and/or to an electrical device package (not shown in).

is a cross-sectional view of an example substrate, according to aspects of the disclosure. In this example, the substrateis similar in most respects to substrateshown in. Accordingly, like reference numbers have been used to reference similar elements. Unlike the substrate, the substrateincludes a non-conductive pastedisposed between the lower planar surfaceof the electronic componentand the interior planar surfaceof the cavityto facilitate securement of the electronic componentin the cavity. In an aspect, the non-conductive pasteat least partially surrounds one or more sidewalls of the electronic component. In addition to facilitating securement of the electronic componentin place in a completed substrate, the non-conductive pastemay also serve to hold the electronic componentin position during fabrication (e.g., filling of the cavity).

illustrate example steps undertaken in fabricating a substrate, according to aspects of the disclosure. As shown in, a first intermediate structureis formed with a patterned metallization layerthat is disposed over an upper planar surfaceof a core. Additionally, a further patterned metallization layeris formed over a lower surfaceof the core.

As shown in, a cavityis formed in the upper planar surfaceof the first intermediate structureto form a second intermediate structure. The cavityis bounded by sidewallsof the coreand an interior planar surfaceof the core. In an aspect, depth Hof the cavitycorresponds to the height of the electronic component that is to be mounted in the cavity.

As shown in, a third intermediate structureis formed when an adhesive layer(and/or a layer of non-conductive paste) is placed over the interior planar surfaceof the core. In an aspect, the amount of adhesive (or non-conductive paste) dispensed for the adhesive layerdepends on the extent to which the adhesive layer is to engage the electronic component that is mounted in the cavity. A larger amount of adhesive may be used when the electronic component is to be at least partially embedded in the adhesive layer (e.g., the adhesive layer extends to the regions between sidewallsof the coreand the peripherals sidewalls of the electronic component).

As shown in, a fourth intermediate structureis formed when an electronic componentis inserted into the cavitywith its upper planar surfacehaving the electronic component terminalsfacing upward and its lower planar surfacefacing the interior planar surfaceof the core. In this example, the lower planar surfaceof the electronic componentis adhered to the interior planar surfaceby the adhesive layer. As noted herein, the depth of the cavityis substantially the same dimension as the height of the electronic componentso that the upper planar surfaceof the electronic componentis level with the upper planar surfaceof the core(e.g., as shown at dotted line) when the electronic componentis seated in the cavity. It will be understood, based on the teachings of the disclosure, that the depth of the cavitymay take into account the amount by which the electronic componentis elevated by the adhesive layer. As such, the depth of the cavitymay depend on the amount of material used to form the adhesive layeror any other thin layer overlying the interior planar surface.

shows a fifth intermediate structurein which the cavityhas been filled with a filler material, which assists in securing the electronic componentwithin the cavity. In an aspect, the filler materialmay be formed from a dielectric resin or other non-conductive viscous material. The fifth intermediate structureis subject to a layer build-up process in which a further layerincluding a dielectric layerand patterned metallization layeris formed over the upper surface of the fourth intermediate structure. In an aspect, the filler materialmay be formed from the same dielectric material as dielectric layerand deposited during the same layer build-up operation. Additionally, a layerincluding dielectric layerand a patterned metallization layerare formed over the lower surface of the fourth intermediate structureduring a layer build-up process.

In, a sixth intermediate structureis formed by subjecting the fifth intermediate structureto a further layer build-up process to form layersand. It will be understood that metal via structures may be formed during the layer build-up processes to establish electrically conductive paths between the layers.

shows a completed substrate, according to aspects of the disclosure. Here, a plurality of metal terminalsmay be formed at the upper surfaceof the substrate to provide an electrical connection with the patterned metallization layer. The patterned metallization layermay be connected with the electronic component terminalsof the electronic componentthrough electrically conductive paths formed by metal vias deposited during the layer build-up processes. As noted herein, the metal terminalsmay be configured for connection with an electronic package of a surface-mounted device.

As shown in, an additional plurality of metal terminalsare formed at the lower surfaceof the substrate and are electrically connected with the lowermost patterned metallization layer. As noted herein, the metal terminalsmay be configured for connection with another electronic package of a surface-mounted device, connection with another substrate, or the like.

is a flowchart showing an example methodfor fabricating a substrate, according to aspects of the disclosure. At operation, a cavity is formed in a core that extends from an upper planar surface of the core to an interior planar surface of the core. At operation, an electronic component is inserted in the cavity so that an upper planar surface of the electronic component having one or more electronic component terminals is supported by the interior planar surface of the core, wherein the electronic component is supported by the interior planar surface of the core so that the upper planar surface of the electronic component is level with the upper planar surface of the core. At operation, an upper metallization structure is formed and configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure

A technical advantage of the methodis that it may be used to form a substrate with an embedded electronic component (e.g., deep trench capacitor) and a core, where the fabrication processes are not dependent on the thickness of the core.

illustrates a profile view of a packagethat includes a surface mount substrate, an integrated device, and an integrated passive device(e.g., a substrate having an embedded electronic component and a core), according to aspects of the disclosure. The packagemay be coupled to a printed circuit board (PCB)through a plurality of solder interconnects. The PCBmay include at least one board dielectric layerand a plurality of board interconnects.

The surface mount substrateincludes at least one dielectric layer(e.g., substrate dielectric layer), a plurality of interconnects(e.g., substrate interconnects), a solder resist layerand a solder resist layer. The integrated devicemay be coupled to the surface mount substratethrough a plurality of solder interconnects. The integrated devicemay be coupled to the surface mount substratethrough a plurality of pillar interconnectsand the plurality of solder interconnects. The integrated passive devicemay be coupled to the surface mount substratethrough a plurality of solder interconnects. The integrated passive devicemay be coupled to the surface mount substratethrough a plurality of pillar interconnectsand the plurality of solder interconnects.

The package (e.g.,) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. A package (e.g.,) may be configured to provide Wireless Fidelity (WiFi) communication and/or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g.,) may be configured to support Global System for Mobile (GSM) Communications, Universal Mobile Telecommunications System (UMTS), and/or Long-Term Evolution (LTE). The package (e.g.,) may be configured to transmit and receive signals having different frequencies and/or communication protocols.

illustrates an example methodfor providing or fabricating a package that includes an integrated device comprising an electronic component mounted in a core, according to aspects of the disclosure. In some implementations, the methodofmay be used to provide or fabricate the packageofdescribed in the disclosure. However, the methodmay be used to provide or fabricate any of the packages described in the disclosure.

It should be noted that the method ofmay combine one or more processes in order to simplify and/or clarify the method for providing or fabricating a package that includes an integrated device comprising an electronic component mounted in a core, according to aspects of the disclosure. In some implementations, the order of the processes may be changed or modified.