Memory device having improved P-N junction and manufacturing method thereof

This application is a divisional application of U.S. Non-Provisional application Ser. No. 18/097,338 filed Jan. 16, 2023, which is incorporated herein by reference in its entirety.

The present disclosure relates to a memory device and a manufacturing method thereof, and more particularly, to a memory device having an insulating layer and a conductive layer corresponding to the insulating layer to form a channeled P-N junction, and a manufacturing method of the memory device.

Dynamic random-access memory (DRAM) is a type of semiconductor arrangement for storing bits of data in separate capacitors within an integrated circuit (IC). DRAMs are commonly formed as trench capacitor DRAM cells. An advanced method of fabricating a buried gate electrode involves building a gate electrode of a transistor and a word line in a trench in an active area (AA) comprising a shallow trench isolation (STI) structure.

Over the past few decades, as semiconductor fabrication technology has continuously improved, sizes of electronic devices have been correspondingly reduced. As a size of a P-N junction is-reduced to a few nanometers in length, an undesired conduction within the P-N junction may significantly decrease performance of the DRAM. It is therefore desirable to avoid P-N junction leakage.

One aspect of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface; a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface; a doped member extending into the semiconductor substrate and surrounded by the active area; a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion; and a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, wherein the first portion of the conductive layer is disposed between the gate structure and the doped member.

Another aspect of the present disclosure provides a memory device. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface; a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface; an insulating layer disposed within the active area; and a conductive layer including a first portion extending into the active area and a second portion disposed over the insulating layer and the active area, wherein the first portion is coupled to and extends from the second portion, and the first portion contacts the insulating layer and the active area.

Another aspect of the present disclosure provides a method of manufacturing a memory device. The method includes steps of providing a semiconductor substrate defined with an active area, wherein the semiconductor substrate includes a gate structure adjacent to the active area and an isolation structure surrounding the active area and the gate structure; forming a recess extending into the semiconductor substrate and within the active area; and forming an insulating layer conformal to the recess. The method further includes removing a portion of the insulating layer to expose a first side of the recess, wherein the first side of the recess is adjacent to the gate structure; forming a first portion of a conductive layer on the first side of the recess; forming a doped member within the recess and over the insulating layer and the first portion of the conductive layer; and forming a second portion of the conductive layer over the doped member and coupled to the first portion of the conductive layer.

In conclusion, because an insulating layer disposed between a doped member and an active area of a semiconductor substrate is coupled to a conductive layer adjacent to a gate structure and over the doped member, leakage from a P-N junction may be avoided. Therefore, an overall performance of a memory device and a process of manufacturing the memory device are improved.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

is a schematic cross-sectional side view of a first memory devicein accordance with some embodiments of the present disclosure. In some embodiments, the first memory deviceincludes several unit cells.

In some embodiments, the first memory deviceincludes a semiconductor substrate. In some embodiments, the semiconductor substrateincludes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrateincludes bulk semiconductor material. In some embodiments, the semiconductor substrateis a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrateis a silicon substrate. In some embodiments, the semiconductor substrateincludes lightly-doped monocrystalline silicon. In some embodiments, the semiconductor substrateis a p-type substrate.

In some embodiments, the semiconductor substrateincludes a first surfaceand a second surfaceopposite to the first surface. In some embodiments, the first surfaceis a front side of the semiconductor substrate, wherein electrical devices or components are subsequently formed over the first surfaceand configured to electrically connect to an external circuitry. In some embodiments, the second surfaceis a back side of the semiconductor substrate, where electrical devices or components are absent.

In some embodiments, the semiconductor substrateincludes several active areas (AA)separated from each other. Each of the active areasis a doped region in the semiconductor substrate. In some embodiments, each of the active areaextends horizontally over or under the first surfaceof the semiconductor substrate. In some embodiments, each of the active areasincludes a same type of dopant. In some embodiments, each of the active areasincludes a type of dopant that is different from the types of dopants included in other active areas. In some embodiments, each of the active areashas a same conductive type. In some embodiments, the active areaincludes N-type dopants.

In some embodiments, the semiconductor substrateincludes a first recessextending into the semiconductor substrate. In some embodiments, the first recessextends from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, the first recessis disposed between the active areas, such as between a first active areaand a second active area. In some embodiments, the first recessis tapered from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, a depth of the first recessis substantially greater than a depth of each of the active areas.

In some embodiments, the first memory deviceincludes a gate structuredisposed within the first recess. In some embodiments, the gate structureis disposed between the active areas, such as between the first active areaand the second active area

In some embodiments, the gate structureincludes a gate oxidedisposed within the first recess, and a gate electrodesurrounded by the gate oxide. In some embodiments, the gate oxideis disposed conformal to and within the first recess. In some embodiments, the gate oxideis disposed along an entire sidewall of the first recess. In some embodiments, the gate electrodeis conformal to the gate oxide. In some embodiments, the gate oxideincludes silicon oxide, or the like. In some embodiments, the gate electrodeincludes conductive material such as tungsten (W).

In some embodiments, the first memory devicefurther includes an isolation structureadjacent to the gate structure. In some embodiments, the isolation structureextends into the semiconductor substratefrom the first surfacetoward the second surface. In some embodiments, the isolation structureis a shallow trench isolation (STI). In some embodiments, the isolation structuredefines a boundary of the active areas. In some embodiments, the semiconductor substrateis defined with the active areasand includes the isolation structuresurrounding the active areasand the gate structure. In some embodiments, the isolation structureis formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. In some embodiments, a depth of the isolation structureis substantially greater than a depth of the gate structure.

In some embodiments, the semiconductor substrateincludes a second recessextending into the semiconductor substrate. In some embodiments, the second recessis adjacent to the gate structure. In some embodiments, the second recessextends from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, the second recessis tapered from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, the second recessis disposed within one of the active areas, such as the first active area. In some embodiments, the second recessis disposed between the gate structureand the isolation structure. In some embodiments, a depth of the second recessis substantially equal to or less than the depth of the first recess. In some embodiments, the depth of the second recessis less than the depth of the first recess. In some embodiments, the second recesshas a first sideadjacent to the gate structureand a second sideopposite to the first side

In some embodiments, the first memory deviceincludes a first insulating layerdisposed within the second recess. In some embodiments, the first sideof the second recessis exposed through the first insulating layer. In some embodiments, the first insulating layeris conformal to the second sideof the second recess. In some embodiments, the first insulating layeris disposed within and surrounded by the first active area. In some embodiments, the first insulating layeris disposed within the first active areaand over the isolation structureadjacent to the second recess. In some embodiments, the first insulating layerincludes oxide. In some embodiments, the first insulating layerincludes silicon oxide, or the like.

In some embodiments, the first memory deviceincludes a doped memberextending into the semiconductor substrateand surrounded by the first active area. In some embodiments, the doped memberis disposed within the second recess. In some embodiments, the doped memberis disposed over the first insulating layer. In some embodiments, the first insulating layeris disposed under the doped memberand surrounded by the first active area. In some embodiments, the doped memberis disposed between the isolation structureand the gate structure.

In some embodiments, the doped memberincludes polycrystalline silicon (polysilicon). In some embodiments, the doped memberincludes a type of dopant that is same as the types of dopants included in the active areas. In some embodiments, the doped memberincludes N-type dopants.

In some embodiments, the first memory deviceincludes a conductive layer. In some embodiments, the conductive layeris disposed over the first active area. In some embodiments, the conductive layercovers the first active area. In some embodiments, the conductive layeris disposed between the gate structureand the isolation structure. In some embodiments, the conductive layeris disposed over the doped member. In some embodiments, the doped memberis surrounded by the first insulating layerand the conductive layer. In some embodiments, the conductive layerincludes conductive material, such as metal or alloy. In some embodiments, the conductive layerincludes cobalt.

In some embodiments, the conductive layerincludes a first portionextending into the first active areaof the semiconductor substratefrom the first surface, and a second portiondisposed over the doped memberand coupled to the first portion. The first portionis coupled to and extends from the second portion. In some embodiments, the first portionof the conductive layeris substantially orthogonal to the second portionof the conductive layer.

In some embodiments, the first portionand the second portionare integral. In some embodiments, the first portionand the second portionare formed simultaneously or separately. In some embodiments, the formation of the first portionis performed prior to the formation of the second portion. The conductive materials included in the first portionand the second portionmay be same or different.

In some embodiments, the first portionof the conductive layeris disposed between the gate structureand the doped member. In some embodiments, the first portionof the conductive layeris disposed between the first active areaand the doped member. In some embodiments, the first portionof the conductive layerextends into the first active areaof the semiconductor substratefrom the first surface. In some embodiments, the first portionof the conductive layeris disposed within the first active area. In some embodiments, the first portionof the conductive layeris disposed within the second recess. In some embodiments, the first portionof the conductive layeris in contact with the doped member.

In some embodiments, the first portionof the conductive layeris disposed adjacent to the first insulating layer. In some embodiments, the first portionof the conductive layeris coupled to the first insulating layer. In some embodiments, the first portionof the conductive layeris disposed on the first sideof the second recess. In some embodiments, the first portionof the conductive layercontacts the first insulating layerand the first active area. When a current (not shown) flows through the first memory device, the current may flow in a direction indicated by an arrow A. In some embodiments, the current may flow along the gate structurefrom the second active areato the first active area. Because the first insulating layeris disposed within the first active areaand blocks the current, the current flows to the first portionof the conductive layer, and flows through the first portionof the conductive layerto the second portionof the conductive layer. In addition, because the first insulating layeris configured to limit a P-N junction area within the first active area, the current must pass through the conductive layer, and P-N junction leakage can therefore be prevented. Overall performance of the first memory deviceis thereby improved.

In some embodiments, in order to avoid junction leakage, a length Lof the first portionof the conductive layeris substantially equal to or less than a length Lof the first insulating layer. In some embodiments, the length Lis less than the length L. In some embodiments, the length Lis more than twice the length L. In some embodiments, the length Lis 2 times to 30 times the length L.

In some embodiments, the second portionof the conductive layercovers the doped member. In some embodiments, the second portionof the conductive layeris in contact with the doped member. In some embodiments, the second portionis disposed over the first insulating layerand the first active area. In some embodiments, the second portionof the conductive layeris disposed over the first portionof the conductive layer. In some embodiments, the second portionof the conductive layeris in contact with the first insulating layer. In some embodiments, the doped memberis disposed between the first insulating layerand the second portionof the conductive layer.

In some embodiments, the first memory deviceincludes a second insulating layerdisposed over the gate structure. In some embodiments, the first insulating layerand the second insulating layerare separated from each other. In some embodiments, the second insulating layeris disposed over the gate structure, the second active areaand the isolation structureadjacent to the second active area. In some embodiments, the second insulating layeris in contact with the gate structure. In some embodiments, the second insulating layerincludes oxide. In some embodiments, the second insulating layerincludes silicon oxide or the like. In some embodiments, the first insulating layerand the second insulating layerinclude same materials. In some embodiments, a thickness Tof the first insulating layeris less than or equal to a thickness Tof the second insulating layer. In some embodiments, the first insulating layerand the second insulating layerare formed simultaneously or separately.

In some embodiments, the first portionof the conductive layeris disposed between and coupled to the first insulating layerand the second insulating layer. In some embodiments, the second portionof the conductive layeris disposed between the first insulating layerand the second insulating layer. In some embodiments, the second portionof the conductive layeris substantially coplanar with a top surfaceof the second insulating layer. In some embodiments, a top surfaceof the doped memberis substantially coplanar with the top surfaceof the second insulating layer. In some embodiments, the top surfaceof the second insulating layeris substantially lower than the second portionof the conductive layer.

is a schematic cross-sectional side view of a second memory devicein accordance with some embodiments of the present disclosure. In some embodiments, the second memory deviceillustrated inis similar to the first memory deviceillustrated in, except the second memory devicefurther includes a contactdisposed over the conductive layer, and a capacitorelectrically connected to the conductive layerthrough the contact. In some embodiments, a landing padis disposed over the contact, and a contactis disposed over the landing pad, the landing padand the contactare disposed between the contactand the capacitor. In some embodiments, the capacitoris electrically connected to the first active regionin the semiconductor substrateby the contacts,, the landing pad, and the conductive layer. In some embodiments, the capacitoris disposed over the contacts,and the landing pad. In some embodiments, the second memory deviceis a DRAM.

In some embodiments, the second memory devicefurther includes a contactdisposed over the second active region, and a bit lineelectrically connected to the second active regionin the semiconductor substratethrough the contact. In some embodiments, the contactpenetrates through the second insulating layer. In some embodiments, the contactis surrounded by the second insulating layerand electrically connected to the second active region. In some embodiments, the bit lineis disposed adjacent to the landing pad.

In some embodiments, the contacts,,include conductive material, such as polycrystalline silicon, tungsten (W), copper (Cu), or the like. In some embodiments, the capacitor, the landing padand the bit lineinclude conductive material, such as polycrystalline silicon, tungsten (W), copper (Cu), or the like. The contacts,,, the capacitor, the landing padand the bit lineinclude a same material or different materials.

In some embodiments, the second memory deviceincluding a first dielectric layersurrounding the contacts,and covering the conductive layer, the first insulating layer, the second insulating layer, the doped member, the active areaand the gate structure. In some embodiments, the contacts,penetrates through the first dielectric layer. In some embodiments, the first dielectric layerincludes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or another applicable dielectric material.

In some embodiments, the second memory deviceincluding a second dielectric layerover the first dielectric layerand surrounding the capacitor. In some embodiments, the second dielectric layerincludes a plurality of sub-layers,,. In some embodiments, the sub-layeris disposed over the first dielectric layer, and the landing padis surrounded by the sub-layer. In some embodiments, the sub-layeris disposed over the sub-layer, and the contactis surrounded by the sublayer. In some embodiments, the sub-layeris disposed over the sub-layer, and the capacitorsis surrounded by the sublayer. In some embodiments, the bit lineis surrounded by the second dielectric layer. In some embodiments, the bit lineis surrounded by the sub-layer

In some embodiments, a plurality of capacitorsare disposed within the second dielectric layer. In some embodiments, the capacitorsare electrically connected to corresponding active regionsin the semiconductor substrateby a plurality of landing padsand a plurality of contacts,. In some embodiments, the capacitorsare disposed within second dielectric layer. In some embodiments, the second dielectric layerincludes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or another applicable dielectric material. The first dielectric layerand the second dielectric layerinclude a same material or different materials. In some embodiments, the second dielectric layeris an inter-layer dielectric (ILD).

is a flow diagram illustrating a method Sof manufacturing the first memory deviceor the second memory devicein accordance with some embodiments of the present disclosure, andillustrate cross-sectional views of intermediate stages in formation of the first memory deviceor the second memory devicein accordance with some embodiments of the present disclosure.

The stages shown inare also illustrated schematically in the flow diagram in. In following discussion, the fabrication stages shown inare discussed in reference to process steps shown in. The method Sincludes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method Sincludes a number of steps (S, S, S, S, S, S, Sand S).

Referring to, a semiconductor substrateis provided according to step Sin. The semiconductor substrateis defined with a first active area, and includes a gate structureadjacent to the first active areaand an isolation structuresurrounding the first active areaand the gate structure. In some embodiments, the gate structureis disposed adjacent to the first active areaand extends from a first surfacetoward a second surfaceof the semiconductor substrate. In some embodiments, the isolation structureextends from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, the gate structureis disposed between the first active areaand a second active area. In some embodiments, the first active areaincludes N-type dopants. In some embodiments, the semiconductor substrateis a p-type substrate.

Referring to, a recessis formed extending into the semiconductor substrateand within the first active areaaccording to step Sin. In some embodiments, referring to, a pattern maskis disposed over the first surfaceof the semiconductor substrate. In some embodiments, the pattern maskincludes an openingprovided over the first active area. The openingexposes the first active areaproximal to the gate structure. The pattern maskis formed by steps including (1) conformally coating a photosensitive material on the first surfaceof the semiconductor substrate, (2) exposing portions of the photosensitive material to radiation (not shown), (3) performing a post-exposure baking process, and (4) developing the photosensitive material, thereby forming the openingto expose the first active areaproximal to the gate structure.

Referring to, the recessextending into the semiconductor substrateis formed. In some embodiments, the recessextends within the first active area. In some embodiments, the formation of the recessincludes removing some portions of the semiconductor substrate. In some embodiments, the recessextends from the first surfacetoward the second surfaceof the semiconductor substrate. In some embodiments, a depth Dof the recessis less than a depth Dof the gate structure. In some embodiments, the recesshas a first sideadjacent to the gate structureand a second sideopposite to the first sideand adjacent to the isolation structure. In some embodiments, the recessis formed by etching or any other suitable process. In some embodiments, the recessis formed by dry etching. Referring to, in some embodiments, the pattern maskis removed after the recessis formed.

Referring to, an implanted regionof the first active areais formed on the first sideof the recessaccording to step Sin. In some embodiments, the implanted regionis formed by implanting implants in the recessand toward the gate structure. In some embodiments, the implanted regionis formed by implanting implants at an angle σ into the first active areaof the semiconductor substrate. In some embodiments, the angle σ relative to the first surfaceof the semiconductor substrateranges between 7 degrees and 30 degrees. In some embodiments, the implanted regionis formed by nitrogen ion implantation. In some embodiments, step Sis omitted.

Referring to, an insulating layeris formed conformal to the recessaccording to step Sin. In some embodiments, the insulating layeris formed over the isolation structure, the recess, the gate structureand the second active area. In some embodiments, the insulating layeris formed over the first surfaceof the semiconductor substrate. In some embodiments, the insulating layeris formed by deposition, oxidation, a spin-coating process, or any other suitable process. In some embodiments, the insulating layeris formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or any other suitable process. In some embodiments, the insulating layerincludes oxide such as silicon oxide.

In some embodiments, the insulating layeris not easily formed on the first sideof the recess. In some embodiments, the insulating layeris not easily formed on the implanted region. In some embodiments, a thickness Tof a portionof the insulating layerover the implanted regionis less than a thickness Tof a portionof the insulating layerover the second sideof the recess

Referring to, according to step Sin, the portionof the insulating layeris removed to expose the first sideof the recess, wherein the first sideof the recessis adjacent to the gate structure. In some embodiments, the portionof the insulating layeris disposed over the implanted region. In some embodiments, the portionof the insulating layeris removed by etching or any other suitable process. In some embodiments, the portionof the insulating layeris washed away by a dilute hydrofluoric acid solution (DHF). In some embodiments, the implants of the implanted regionare removed after the first sideof the recessis exposed.

In some embodiments, after the removal of the portionof the insulating layer, the insulating layeris separated into a first segmentdisposed within the recessand a second segmentdisposed over the gate structure. In some embodiments, the thickness Tof the first segmentof the insulating layeris less than a thickness Tof the second segmentof the insulating layerafter the removal of the portionof the insulating layer. In some embodiments, the first segmentof the insulating layerforms a first insulating layer, and the second segmentof the insulating layerforms a second insulating layer

Referring to, a first portionof a conductive layeron the first sideof the recessis formed according to step Sin. In some embodiments, referring to, a first conductive materialis disposed over the first sideof the recess, the first insulating layerand the second insulating layer. In some embodiments, the first conductive materialis conformal to the first sideof the recess. In some embodiments, the first conductive materialincludes the first portionof the conductive layer. In some embodiments, the first conductive materialis formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process or any other suitable process. In some embodiments, the first conductive materialincludes cobalt.