Manufacturing method of gate structure

The present invention relates to a manufacturing method of a gate structure, and more particularly, to a manufacturing method of a gate structure formed on an active region and an isolation structure.

In the integrated circuit, transistors may be different from one another in structure for different operation voltages. For example, the transistors for relatively low operation voltage may be applied in core devices, input/output (I/O) devices, and so on. The transistors capable of high voltage processing may be applied in high operation voltage environment such as CPU power supply, power management system, AC/DC converter, and power amplifier. However, in order to form transistors corresponding to different operation voltages on the same wafer or chip, the processes are often complicated and the manufacturing cost and/or the manufacturing yield will be influenced accordingly. Therefore, how to improve the related problems through the design of structure and/or the design of process is a continuous issue for those in the related fields.

A manufacturing method of a gate structure is provided in the present invention. A part of a capping layer located above an interface between an active region and an isolation structure is removed, the thickness of a gate structure located above the interface may be reduced by other process accordingly, and the purposes of manufacturing yield enhancement and/or process simplification may be achieved.

According to an embodiment of the present invention, a manufacturing method of a gate structure is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure, and the gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention.

Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below.

The terms “on,” “above,” and “over” used herein should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

The ordinal numbers, such as “first”, “second”, etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name.

The term “etch” is used herein to describe the process of patterning a material layer so that at least a portion of the material layer after etching is retained. When “etching” a material layer, at least a portion of the material layer is retained after the end of the treatment. In contrast, when the material layer is “removed”, substantially all the material layer is removed in the process. However, in some embodiments, “removal” is considered to be a broad term and may include etching.

The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to.are schematic drawings illustrating a manufacturing method of a gate structure according to a first embodiment of the present invention, whereinis a top view schematic drawing,is a cross-sectional diagram taken along a line A-A′ in,is a schematic drawing in a step subsequent to,is a cross-sectional diagram taken along a line B-B′ in,is a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to, andis a schematic drawing in a step subsequent to. The manufacturing method in this embodiment may include the following steps. Firstly, as shown in, a semiconductor substrateis provided. An isolation structureis formed in the semiconductor substrateand surrounds an active regionA in the semiconductor substrate. Subsequently, a gate pattern GP is formed on the active regionA and the isolation structure, and the gate pattern GP includes a first gate structureand a first capping layer (such as a capping layer CLillustrated in) disposed on the first gate structure. As shown in, a part of the capping layer CLlocated above an interface TF between the active regionA and the isolation structureis removed for exposing a part of the first gate structurelocated above the interface TF between the active regionA and the isolation structure. As shown in, a removing processis then performed for reducing a thickness of the part of the first gate structurelocated above the interface TF between the active regionA and the isolation structure. The thickness of the first gate structurelocated above the interface TF may be reduced for reducing the surface height of this portion of the first gate structure. The negative impact of the too thick first gate structurein subsequent processes, such as damages to and/or changes in condition of the first gate structurein processes configured for other regions, may be avoided, and the manufacturing yield may be enhanced accordingly.

In some embodiments, a vertical direction (such as a direction Dillustrated in) may be regarded as a thickness direction of the semiconductor substrate, the semiconductor substratemay have a top surfaceTS and a bottom surfaceBS opposite to the top surfaceTS in the direction D, and the gate pattern GP described above may be formed on the top surface LOTS of the semiconductor substrate. Horizontal directions substantially orthogonal to the direction D(such as a direction Dand a direction Dillustrated inand other directions orthogonal to the direction D) may be substantially parallel with the top surfaceTS and/or the bottom surfaceBS of the semiconductor substrate, but not limited thereto. In this description, a distance between the bottom surface LOBS of the semiconductor substrateand a relatively higher location and/or a relatively higher part in the vertical direction (such as the direction D) may be greater than a distance between the bottom surface LOBS of the semiconductor substrateand a relatively lower location and/or a relatively lower part in the direction D. The bottom or a lower portion of each component may be closer to the bottom surfaceBS of the semiconductor substratein the direction Dthan the top or upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surfaceBS of the semiconductor substratein the direction D, and another component disposed under a specific component may be regarded as being relatively close to the bottom surfaceBS of the semiconductor substratein the direction D.

Specifically, the manufacturing method in this embodiment may include but is not limited to the following steps. As shown inand, the isolation structuremay be formed in the semiconductor substratefor defining the active regionA in the semiconductor substrate. In other words, the active regionA may be a part of the semiconductor substrate, and the material composition of the active regionA may be the same as the material composition of the semiconductor substrate. In some embodiments, the semiconductor substratemay include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a semiconductor substrate made of other suitable semiconductor materials and/or made with other suitable structural designs. The isolation structuremay include a single layer or multiple layers of insulation materials, such as an insulation liner layer and an insulation gap-filling material, but not limited thereto. The insulation liner layer described above may include oxide insulation material or other suitable insulation materials, and the insulation gap-filling material described above may include a spin-on dielectric material, an insulation material formed by a deposition process (such as a chemical vapor deposition process), or a structure formed with other suitable manufacturing approaches and/or materials. In some embodiments, the isolation structuremay include a notchN located at an edge of the isolation structureadjacent to the active regionA, and a surface of the notchN is lower than a top surfaceTS of the isolation structurein the direction D. In some embodiments, the contact area between the first gate structureand the active regionA may be increased by the notchN, and the notchN may be formed by adjusting the material composition and/or the material distribution in the isolation structurefor being accompanied with the corresponding planarization process and/or the corresponding etching process, but not limited thereto.

After the step of forming the isolation structure, the gate pattern GP may be formed on the active regionA and the isolation structure. In some embodiments, the active regionA may be elongated in the direction D, the gate pattern GP may be elongated in the direction Dand may be formed straddling the active regionA, and the direction Dmay be substantially orthogonal to the direction D, but not limited thereto. The gate pattern GP includes the first gate structureand the capping layer CL, and the capping layer CLis disposed on the first gate structurein the direction D. In some embodiments, the first gate structureand the capping layer CLmay be formed concurrently by the same patterning process, and the projection pattern and the projection area of the capping layer CLin the direction Dmay be substantially the same as those of the first gate structurein the direction D, but not limited thereto. In addition, the first gate structuremay include electrically conductive non-metallic materials (such as an electrically conductive polycrystalline silicon material) or other suitable electrically conductive materials, and the capping layer CLmay include an oxide insulation material (such as silicon oxide) or other suitable insulation materials. In some embodiments, a dielectric layer DLmay be formed and located between the active regionA and the gate pattern GP, and the dielectric layer DLmay include oxide (such as silicon oxide) or other suitable dielectric materials. In some embodiments, the notchN of the isolation structuremay be located adjacent to the interface TF between the active regionA and the isolation structure, and the notchN is lower than the top surfaceTS of the isolation structurein the direction D. The top surfaceTS of the isolation structureis lower than a top surface of the active regionA (such as the top surfaceTS described above), and the gate pattern GP formed on the active regionA and the isolation structurewill be influenced by the surface condition of the active regionA, the isolation structure, and the interface TF.

For example, the first gate structuremay include a first portion P, and second portion P, and a third portion Pconnected with one another. The first portion Pis located above the active regionA in the direction D, the second portion Pis located above the isolation structurein the direction D, and the third portion Pis located above the interface TF between the active regionA and the isolation structurein the direction D. The third portion Pmay be located between the first portion Pand the second portion P, and the third portion Pmay be directly connected with the first portion Pand the second portion P. Because of the influence of the surface condition of the active regionA, the isolation structure, and the interface TF, a top surface TSof the second portion Pmay be lower than a top surface TSof the first portion Pin the direction D, and a top surface TSof the third portion Pmay be higher than the top surface TSof the second portion Pand the top surface TSof the first portion Pin the direction D, but not limited thereto. In addition, the capping layer CLmay be formed conformally on the first gate structuresubstantially, and the thickness of the capping layer CLlocated on the first portion P, the thickness of the capping layer CLlocated on the second portion P, and the thickness of the capping layer CLlocated on the third portion Pmay be substantially equal to one another, but not limited thereto.

As shown in, a part of the capping layer CLlocated above the interface TF between the active regionA and the isolation structuremay be removed for exposing a part of the first gate structurelocated above the interface TF between the active regionA and the isolation structure, such as the third portion described above. In this embodiment, the method for removing a part of the capping layer CLlocated above the interface TF between the active regionA and the isolation structuremay include but is not limited to the following steps. As shown inand, a patterned mask layermay be formed on the capping layer CL, the active regionA, and the isolation structure, and an opening OPmay penetrate through the patterned mask layerin the direction Dfor exposing the capping layer CLlocated above the interface TF between the active regionA and the isolation structure. In some embodiments, two openings OPmay be formed and located at two opposite sides of the active regionA in the direction D, and each of the openings OPmay be elongated in the direction D, but not limited thereto. Subsequently, as shown in, an etching process using the patterned mask layeras an etching mask may be performed for forming an opening OPin the capping layer CL, and the opening OPmay penetrate through the capping layer CLin the direction Dand expose the third portion Pof the first gate structure. In other words, the opening OPmay be regarded as an opening formed by transferring the pattern of the opening OPto the capping layer CLvia the etching approach described above, the opening OPmay be elongated in the direction Dalso, and the length of the opening OPin the direction Dmay be greater than the length of the opening OPin the direction Daccordingly. Additionally, the patterned mask layermay be removed after the opening OPis formed.

Subsequently, as shown inand, the removing processmay be performed for removing a part of the third portion Pof the first gate structureexposed by the opening OPand reducing the thickness of the third portion P. During the removing process, the first portion Pand the second portion Pof the first gate structuremay be covered by the capping layer CL, and a part of the third portion Pof the first gate structurelocated adjacent to the top surface and exposed by the opening OPmay be removed by the removing processfor lowering the top surface of the third portion P. For instance, the top surface TSmay become a top surface TS′ via the removing process. Therefore, after the removing process, the top surface TS′ of the third portion Pmay be lower than the top surface TSof the first portion Pand higher than the top surface TSof the second portion Pin the direction D. Relatively, before the removing process, the top surface TSof the third portion Pmay be higher than the top surface TSof the first portion Pb and the top surface TSof the second portion Pin the direction D. It is worth noting that, in this description, the top surface of a specific component may include the topmost surface of this component in the direction D, but not limited thereto. Additionally, the removing processmay include a planarization process, such as a chemical mechanical polishing (CMP) process, or other suitable removing approaches for controlling the removed part of the first gate structureand avoiding excessive removal of the third portion Pof the first gate structureso that the top surface TS′ of the third portion Pis too low.

As shown inand, after the removing process, the capping layer CLmay be removed, and another capping layer (such as a capping layer CL) may then be formed on the first gate structure. In some embodiments, the capping layer CLmay include an oxide insulation material (such as silicon oxide) or other suitable insulation materials, and the top surface of the first gate structure, such as the top surface TSof the first portion P, the top surface TSof the second portion P, and the top surface TS′ of the third portion P, may be completely covered by the capping layer CL. By reducing the thickness of the first gate structurelocated above the interface TF between the active regionA and the isolation structurevia the removing process, the protruding top surface (such as the top surface TSdescribed above) of the first gate structuremay become a flatter top surface (such as the top surface TS′), and the negative impact of the first gate structurehaving the protruding surface in the subsequent processes, such as damages to and/or changes in condition of the first gate structurein the processes configured for other regions, may be avoided, and the manufacturing yield may be enhanced accordingly.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

Please refer to, and.are schematic drawings illustrating a manufacturing method of a gate structure according to a second embodiment of the present invention, whereinis a schematic drawing in a step subsequent to,is a schematic drawing in a step subsequent to, andis a schematic drawing of a region in a step subsequent to. In some embodiments, a portion ofmay be regarded as a schematic drawing in a step subsequent to, andmay be regarded as a schematic drawing in a step subsequent to a portion ofand a schematic drawing in a step before a portion of, but not limited thereto. As shown inand, in some embodiments, the first gate structuredescribed above may be formed above a first region Rof the semiconductor substrate, and the manufacturing method may further include forming a second gate structureabove a second region Rof the semiconductor substrate. The second gate structuremay include electrically conductive non-metallic materials (such as an electrically conductive polycrystalline silicon material) or other suitable electrically conductive materials. In some embodiments, the electrically conductive material for forming the second gate structuremay be formed on the second region Rof the semiconductor substratebefore the removing process, and the removing processmay include a planarization process performed to this electrically conductive material (may be regarded as a planarization process performed to the second gatestructure also). A capping layer CLmay be formed on the second gate structureafter the removing process, and the capping layer CLmay include an oxide insulation material (such as silicon oxide) or other suitable insulation materials. In other words, the planarization process performed to the second gate structurelocated on the second region Rmay be used to reducing the thickness of the third portion Pof the first gate structurelocated on the first region R, and the purposes of process simplification and/or manufacturing cost reduction may be achieved accordingly.

In some embodiments, the first region Rmay include a high-voltage semiconductor device region, the second region Rmay include a memory cell region, the first gate structuremay be a gate electrode of a high-voltage semiconductor device, and the second gate structuremay be a word line in a memory cell, but not limited thereto. In some embodiments, the manufacturing method may further include forming a dielectric layer DLand a mask layeron a third region Rof the semiconductor substrateand forming a dielectric layer DL, and the dielectric layer DLis located between the second gate structureand the semiconductor substrate. The dielectric layer DLand the dielectric layer DLmay include oxide (such as silicon oxide) or other suitable dielectric materials, and the mask layermay include nitride (such as silicon nitride) or other suitable dielectric materials. Subsequently, as shown in,,, and, after the removing process, the mask layerand the dielectric layer DLmay be removed, and a dielectric layer DLand a dummy gate structuremay be formed on the third region Rof the semiconductor substrate. The dielectric layer DLmay include oxide (such as silicon oxide) or other suitable dielectric materials, a thickness of the dielectric layer DLmay be less than a thickness of the dielectric layer DL, and the dummy gate structuremay include polycrystalline silicon or other suitable materials. After the step of forming the dummy gate structure, another capping layer CLmay be formed. A portion of the capping layer CLmay be formed on the capping layer CL, and another portion of the capping layer CLmay be formed on the dummy gate structure. The material composition of the capping layer CLmay be different from the material composition of the capping layer CLfor providing required etching selectivity in the subsequent processes. For instance, the capping layer CLmay include nitride (such as silicon nitride) or other insulation materials different from the capping layer CL.

Subsequently, as shown in, a replacement metal gate processmay be performed for removing the dummy gate structureand replacing the dummy gate structurewith a metal gate structure. In some embodiments, the metal gate structuremay include a work function layer (not illustrated) and a low electrical resistivity layer (not illustrated) disposed on the work function layer. The work function layer may include titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium tri-aluminide, aluminum titanium nitride, or other suitable electrically conductive work function materials, and the low electrical resistivity layer may include tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable materials with low electrical resistivity. Additionally, in some embodiments, another dielectric layer (not illustrated), such as a high dielectric constant dielectric layer, may be formed and located between the metal gate structureand the dielectric layer DL, but not limited thereto. A gate trench TR may be formed by removing the dummy gate structurevia the replacement metal gate process, and the metal gate structuremay be formed in the gate trench TR, but not limited thereto. In some embodiments, the third region Rmay include a low-voltage semiconductor device region, a logic circuit region, or other regions different from the first region Rand the second region R, and the metal gate structuremay be a gate electrode in a low-voltage semiconductor device and/or a gate electrode in the logic circuit region, but not limited thereto.

As shown in, the capping layer CLmay be formed before the step of removing the dummy gate structure, and the capping layer CLlocated on the capping layer CLand the capping layer CLlocated on the dummy gate structuremay be removed before the step of removing the dummy gate structure. The method of removing the capping layer CLmay include a chemical mechanical polishing process or other suitable removing approaches. By reducing the thickness of some area of the first gate structurelocated on the first region R(such as reducing the thickness of the third portion Pof the first gate structureillustrated in), the first gate structurewith the protruding surface may be kept from being exposed in the chemical mechanical polishing process configured for removing the capping layer CL, at least a portion of the first gate structuremay be kept from being replaced with a metal gate structure in the replacement metal gate process, and the purpose of manufacturing yield enhancement may be achieved accordingly. In other words, the top surface of the first gate structuremay be completely covered by the capping layer CLfor being protected by the capping layer CLbefore the step of removing the dummy gate structure, during the step of removing the dummy gate structure, and after the step of removing the dummy gate structure. As shown in, the first gate structurelocated above the active regionA, the first gate structurelocated above the isolation structure, and the first gate structurelocated above the interface TF between the active regionA and the isolation structuremay be covered by the capping layer CL.

Please refer toand.andare schematic drawings illustrating a manufacturing method of a gate structure according to a third embodiment of the present invention, whereinis a cross-sectional diagram taken along a line C-C′ in. As shown inand, in some embodiments, the opening OPpenetrating through the patterned mask layermay further overlap the gate pattern GP located on the isolation structurein the direction D, and the opening OPformed corresponding to the opening OPmay further expose the second portion Pof the first gate structureaccordingly. The design of the opening OPin this embodiment may be used to ensure the thickness reduction of the third portion Pof the first gate structure, and the condition where the opening OPis too small to reduce the thickness of the third portion Pas desired may be avoided accordingly. In other words, the thickness reduction of the third portion Pof the first gate structurein the removing process described above may be controlled by adjusting the location and/or the dimension of the opening OP.

Please refer to.is a schematic drawing illustrating a manufacturing method of a gate structure according to a fourth embodiment of the present invention. As shown in, in some embodiments, the opening OPpenetrating through the capping layer CLmay expose the third portion Pand the second portion Pof the first gate structure, and the opening OPmay further expose a part of the first portion Pof the first gate structure. The design of the opening OPin this embodiment may be used to ensure the thickness reduction of the third portion Pof the first gate structure, the thickness of the first portion Pof the first gate structuremay also be reduced by the removing process described above because of the design of the opening OPin this embodiment, and the negative impact of the first gate structurewith the protruding surface on the subsequent processes may be further avoided accordingly.

To summarize the above descriptions, in the manufacturing method of the gate structure according to the present invention, a portion of the capping layer located above the interface between the active region and the isolation structure may be removed, and the thickness of the gate structure located above the interface may then be reduced in other process accordingly. The purposes of manufacturing yield enhancement and/or process simplification may be achieved accordingly.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.