Power supply circuit with short circuit protection

Certain aspects of the present disclosure generally relate to power supply circuits and, more particularly, to techniques and apparatus for providing short circuit protection.

A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators may be classified as linear regulators or switching regulators. While linear regulators tend to be relatively compact, many applications may benefit from the increased efficiency of a switching regulator. A linear regulator may be implemented by a low-dropout (LDO) regulator, for example. A switching regulator (also known as a “switching converter” or “switcher”) may be implemented, for example, by a switched-mode power supply (SMPS), such as a buck converter, a boost converter, a buck-boost converter, or a charge pump.

For example, a buck converter is a type of SMPS typically comprising: (1) a high-side switch coupled between a relatively higher voltage rail and a switching node, (2) a low-side switch coupled between the switching node and a relatively lower voltage rail, (3) and an inductor coupled between the switching node and a load (e.g., represented by a shunt capacitive element). The high-side and low-side switches are typically implemented with transistors, although the low-side switch may alternatively be implemented with a diode.

A charge pump is a type of SMPS typically comprising at least one switching device to control the connection of a supply voltage across a load through a capacitor. In a voltage doubler (also referred to as a “multiply-by-two (×2) charge pump”), for example, the capacitor of the charge pump circuit may initially be connected across the supply, charging the capacitor to the supply voltage. The charge pump circuit may then be reconfigured to connect the capacitor in series with the supply and the load, doubling the voltage across the load. This two-stage cycle is repeated at the switching frequency for the charge pump. Charge pumps may be used to multiply or divide voltages by integer or fractional amounts, depending on the circuit topology.

Power management integrated circuits (power management ICs or PMICs) are used for managing the power scheme of a host system and may include and/or control one or more voltage regulators (e.g., buck converters or charge pumps). A PMIC may be used in battery-operated devices, such as mobile phones, tablets, laptops, wearables, etc., to control the flow and direction of electrical power in the devices. The PMIC may perform a variety of functions for the device such as DC-to-DC conversion (e.g., using a voltage regulator as described above), battery charging, power-source selection, voltage scaling, power sequencing, etc.

The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims that follow, some features are discussed briefly below. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of this disclosure provide the advantages described herein.

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes a switching regulator including an output coupled to a first power supply node, a battery node for coupling to a battery, a switch coupled between the first power supply node and the battery node, a first transistor including a gate coupled to the first power supply node and a source coupled to a reference potential node of the power supply circuit, and a first current source or a resistive element, coupled between a power supply rail and a drain of the first transistor.

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes a switching regulator including an output coupled to a power supply node, a battery node for coupling to a battery, a switch coupled between the power supply node and the battery node, and a logic circuit coupled to the power supply node and configured to detect a short circuit on the power supply node, after completion of a soft start of a voltage on the power supply node.

Certain aspects of the present disclosure are directed to a method of supplying power. The method generally includes after completion of a soft start of a voltage of a first power supply node coupled to an output of a switching regulator and coupled to a battery node via a switch, enabling a detection mode, and when, during the enabled detection mode, the voltage of the first power supply node is less than a threshold voltage (V) of a first transistor including a gate coupled to the first power supply node, triggering an automatic fault protection (AFP) mode.

Certain aspects of the present disclosure provide an integrated circuit (e.g., a power management integrated circuit (PMIC)) comprising at least a portion of any of the power supply circuits described above.

Certain aspects of the present disclosure provide a battery charging circuit comprising any of the power supply circuits described above.

To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

Certain aspects of the present disclosure provide techniques and apparatus for providing short circuit protection in a power supply circuit. Such a power supply circuit may be configured to detect a short circuit on a power supply node included in the power supply circuit and trigger an automatic fault protection (AFP) mode after completion of a soft start of a voltage on the power supply node.

Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element B). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

An Example Device

It should be understood that aspects of the present disclosure may be used in a variety of applications. Although the present disclosure is not limited in this respect, the circuits disclosed herein may be used in any of various suitable apparatus, such as in the power supply, battery charging circuit, or power management circuit of a communication system, a video codec, audio equipment such as music players and microphones, a television, camera equipment, and test equipment such as an oscilloscope. Communication systems intended to be included within the scope of the present disclosure include, by way of example only, cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), and the like.

illustrates an example devicein which aspects of the present disclosure may be implemented. The devicemay be a battery-operated device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop computer, a tablet, a smartphone, an Internet of things (IoT) device, a wearable device, an augmented reality device, etc. For certain aspects, the devicemay be a foldable device (e.g., a flip phone).

The devicemay include a processorthat controls operation of the device. The processormay also be referred to as a central processing unit (CPU). Memory, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor. A portion of the memorymay also include non-volatile random access memory (NVRAM). The processortypically performs logical and arithmetic operations based on program instructions stored within the memory.

In certain aspects, the devicemay also include a transmitterand/or a receiverto allow transmission and/or reception, respectively, of data between the deviceand a remote location. For certain aspects, the transmitterand receivermay be combined into a transceiver. One or more antennasmay be attached or otherwise coupled to a housingof the deviceand electrically connected to the transceiver. The devicemay also include (not shown) multiple transmitters, multiple receivers, and/or multiple transceivers.

The devicemay also include a signal detectorthat may be used in an effort to detect and quantify the level of signals received by the transceiver. The signal detectormay detect such signal parameters as total energy, energy per subcarrier per symbol, and power spectral density, among others. The devicemay also include a digital signal processor (DSP)for use in processing signals.

The devicemay further include a battery, which may be used to power the various components of the device(e.g., when another power source—such as a wall adapter or a wireless power charger—is unavailable). The batterymay comprise a single cell or multiple cells connected in series and/or in parallel. The devicemay further include additional independent batteries (not shown). Each of the additional independent batteries may comprise a single cell or multiple cells connected in series and/or in parallel.

The devicemay also include a power management systemfor managing the power from the battery(or batteries), a wall adapter, and/or a wireless power charger to the various components of the device. The power management systemmay perform a variety of functions for the device such as DC-to-DC conversion, battery charging, power-source selection, voltage scaling, power sequencing, source mode power, etc. In certain aspects, the power management systemmay include a power management integrated circuit (power management IC or PMIC)and one or more power supply circuits, such as a battery charger, which may be controlled by the PMIC or logic associated with the battery charger, for example. For certain aspects, at least a portion of one or more of the power supply circuits (e.g., at least a portion of the battery charger) may be integrated in the PMIC. The PMICand/or the one or more power supply circuits may include at least a portion of a switched-mode power supply (SMPS) circuit, which may be implemented by any of various suitable switched-mode power supply circuit topologies, such as a two-level buck converter, a three-level buck converter, a charge pump, or an adaptive combination power supply circuit (e.g., the SMPS circuitof), which can switch between operating in a buck converter mode and a charge pump mode, as described below.

The various components of the devicemay be coupled together by a bus system, which may include a power bus, a control signal bus, and/or a status signal bus in addition to a data bus. Additionally or alternatively, various combinations of the components of the devicemay be coupled together by one or more other suitable techniques.

Example Power Supply Circuits and Operation

As described above, the PMICand/or the one or more power supply circuits (e.g., battery charger) may include at least a portion of an SMPS circuit (e.g., a buck converter, a charge pump converter, or an adaptive combination power supply circuit capable of switching therebetween), which may be a single-phase or multi-phase converter. In the case of an adaptive combination power supply circuit, both converter modes may be single-phase, both converter modes may be multi-phase, one converter mode may be single-phase while the other converter mode is multi-phase or capable of changing between single-phase and multi-phase, or one converter mode may be multi-phase while the other converter mode is capable of changing between single-phase and multi-phase.

is a circuit diagram of an example power supply circuit, which may be used to charge one or more batteries. As illustrated, the power supply circuitincludes a power multiplexer(labeled “PMUX”), a reverse-current-blocking transistor Q(which may also be referred to as an overvoltage protection (OVP) field-effect transistor (FET) or an input FET), and an SMPS circuit(e.g., an adaptive SMPS circuit).

The power multiplexermay be configured to select between receiving power from, for example, (i) a Universal Serial Bus (USB) port for connecting to a wall adapter and (ii) a wireless power port (both not shown). The power multiplexermay be implemented as a single-pole, double-throw (SPDT) switch by two OVP FETs, and in this case, transistor Qmay be eliminated.

In certain aspects, the output of the power multiplexermay be coupled to an input voltage node(labeled “VIN”). The input voltage nodemay be coupled to a source of the transistor Q, and a drain of the transistor Qmay be coupled to a voltage node (labeled “MID”) of the SMPS circuit. The MID voltage node may serve as the power supply rail of the SMPS circuit, and in some cases, may alternatively be considered as an input node of the SMPS circuit. In some cases, the power multiplexerand/or transistor Qmay be removed.

For certain aspects, the SMPS circuitmay have a two-level buck converter topology. For other aspects, the SMPS circuitmay have a single-phase three-level buck converter topology (as illustrated in the power supply circuitof), and may include a second transistor Q, a third transistor Q, a fourth transistor Q, a fifth transistor Q, a flying capacitive element Cfly, an inductive element L, and a load, which is represented here by a capacitor. For other aspects, the SMPS circuitmay have a dual-phase three-level buck converter topology. To realize an adaptive SMPS circuit, a switch Smay be added across the inductive element Lof the three-level buck converter topology. With the switch Sclosed, the adaptive SMPS circuit may function as a single-phase divide-by-two (Div2) charge pump converter, as further described below. In certain aspects, switch Smay be implemented by two back-to-back transistors.

Transistor Qmay be coupled to transistor Qvia a first node (labeled “CFH” for flying capacitor high node), transistor Qmay be coupled to transistor Qvia a second node (labeled “VSW” for voltage switching node), and transistor Qmay be coupled to transistor Qvia a third node (labeled “CFL” for flying capacitor low node). For certain aspects, the transistors Q-Qmay be implemented as n-type metal-oxide-semiconductor (NMOS) transistors, as illustrated in. In this case, the drain of transistor Qmay be coupled to the source of transistor Q, the drain of transistor Qmay be coupled to the source of transistor Q, and the drain of transistor Qmay be coupled to the source of transistor Q. The source of transistor Qmay be coupled to a reference potential node(e.g., electric ground) for the power supply circuit. The flying capacitive element Cfly may have a first terminal coupled to the first node and a second terminal coupled to the third node. The inductive element Lmay have a first terminal coupled to the second node and a second terminal coupled to an output voltage node(labeled “VOUT,” which may also be referred to as “VPH_PWR” or “VPH”) and the load.

Control logicmay control operation of the SMPS circuitand other aspects of the power supply circuit. For example, the control logicmay control operation of the transistors Q-Qvia output signals to the inputs of respective gate drivers,,, and. The outputs of the gate drivers,,, andare coupled to respective gates of transistors Q-Q. During operation of the adaptive SMPS circuit (or of a three-level buck converter), the control logicmay cycle through four different phases, which may differ depending on whether the duty cycle is less than 50% or greater than 50%.

Operation of the adaptive SMPS circuit with a duty cycle of less than 50% is described first. In a first phase (referred to as a “charging phase”), transistors Qand Qare activated, and transistors Qand Qare deactivated, to charge the flying capacitive element Cfly and to energize the inductive element L. In a second phase (called a “holding phase”), transistor Qis deactivated, and transistor Qis activated, such that the VSW node is coupled to the reference potential node, the flying capacitive element Cfly is disconnected (e.g., one of the Cfly terminals is floating), and the inductive element Lis deenergized. In a third phase (referred to as a “discharging phase”), transistors Qand Qare activated, and transistor Qis deactivated, to discharge the flying capacitive element Cfly and to energize the inductive element L. In a fourth phase (also referred to as a “holding phase”), transistor Qis activated, and transistor Qis deactivated, such that the flying capacitive element Cfly is disconnected and the inductive element Lis deenergized.

Operation of the adaptive SMPS circuit with a duty cycle greater than 50% is similar in the first and third phases, with the same transistor configurations. However, in the second phase (called a “holding phase”) following the first phase, transistor Qis deactivated, and transistor Qis activated, such that the VSW node is coupled to the MID node, the flying capacitive element Cfly is disconnected, and the inductive element Lis energized. Similarly in the fourth phase (also referred to as a “holding phase”) with a duty cycle greater than 50%, transistor Qis activated, and transistor Qis deactivated, such that the flying capacitive element Cfly is disconnected and the inductive element Lis energized.

Furthermore, the control logicmay have a control signal (not shown in) configured to control operation of switch Sand selectively enable divide-by-two (Div2) charge pump operation. For certain aspects, when this control signal is logic low, switch Sis open, and the power supply circuitoperates as a three-level buck converter using the inductive element L. When this control signal is logic high for certain aspects, switch Sis closed, thereby shorting across the inductive element Land effectively removing the inductive element Lfrom the circuit, such that the adaptive SMPS circuit operates as a Div2 charge pump. The control logicmay be configured to automatically control operation of switch S(e.g., through the logic level of the control signal) based on an output current (also referred to as a “load current”) and/or an input current for the adaptive SMPS circuit.

Example Power Supply Circuit

is a circuit diagram of an example power supply circuitA, in accordance with certain aspects of the present disclosure. The power supply circuitA may include a switching regulator (e.g., the SMPS circuit), a first power supply node (labeled “VPH1”), a load(e.g., labeled “VPH Load”), a first switch (e.g., implemented by one or more transistors QBAT), and a first battery.

For certain aspects, the batterymay be external to an integrated circuit (IC) (e.g., a PMIC), whereas at least a portion of the SMPS circuitand the first switch (implemented by transistor(s) QBAT) may be internal to the IC. The batterymay represent a single-cell (1S) battery, a two-cell-in-series (2S) battery, or more than two stacked cells in a battery (e.g., a multi-cell-in series battery). The loadmay be analogous to the loadof. The loadmay represent one or more circuits of a device (e.g., the deviceof) that are powered internally by the SMPS circuit(e.g., with power supply node VPH1=VOUT) (e.g., when an external power source is provided to the power multiplexer) or by the battery(e.g., when no external power source is available). The loadmay be coupled (in shunt) to the reference potential node.

In certain aspects, the output voltage nodeof the SMPS circuitmay be coupled to transistor(s) QBATand the load. In certain aspects, transistor(s) QBATmay be a bidirectional switch implemented with one or more transistors. In some cases, transistor(s) QBATmay be implemented by back-to-back transistors or a body-switchable transistor, for example. The gate(s) of transistor(s) QBATmay be driven by logic circuitry (e.g., the control logicofor other logic not shown in). Transistor(s) QBATmay be coupled to the batteryvia a first battery node(labeled “VBAT1”).

When the batteryis external to an IC with other circuitry of the power supply circuitA, the IC may include a positive first battery port (e.g., a pin) coupled to the battery nodeand to the positive terminal of the battery. In some cases, the IC may include a negative first battery port coupled to another battery nodeand to the negative terminal of the battery. The other battery nodemay be coupled to the reference potential node.

According to certain aspects, the power supply circuitA may perform charging (via the SMPS circuit) of the battery. Electrical power received from a wall adapter or wireless charger, for example, at the power multiplexer(illustrated in) may be converted by the SMPS circuitand used to independently charge the battery. For example, current from the output voltage nodemay be routed to the battery nodevia transistor(s) QBATfor charging the battery.

In power supply circuits, the term “soft start” generally refers to an initial bring-up of a voltage in a slow and controlled manner, for example, to avoid an initial in-rush current to the bypass capacitors when turning on a device, switching power sources, etc. As used herein, a soft start may refer to a phase during which one or more associated transistors (e.g., transistor(s) QBATfor the battery) are biased in a linear region of operation before the transistors are fully turned on (e.g., biased in saturation). Soft start may be performed to charge a capacitive element (e.g., the bypass capacitor(s) on a power supply rail) to a voltage that is within a certain threshold of the battery voltage before the associated transistor for the battery is fully turned on, as described in more detail herein.

Many power supply circuits used in portable devices may utilize short circuit protection. For example, a power supply circuit (e.g., power supply circuitA) may provide short circuit protection during the initial power up of a power supply rail (e.g., the power supply node VPH1) by a SMPS circuit (e.g., SMPS circuit), which may involve turning off or disabling the SMPS circuit when a voltage at the power supply rail is less than a certain threshold (e.g., 2 V). In another example, short circuit protection may be provided during the initial power up of the power supply rail by a battery (e.g., battery) and may involve entering an automatic fault protection (AFP) mode when a voltage of the power supply rail does not reach a voltage at the battery. However, power supply circuits often lack any short circuit protection after the completion of a soft start of the voltage of the power supply rail. Any occurrence of a short circuit after the completion of a soft start may result in damage to the power supply circuit.

Accordingly, certain aspects of the present disclosure provide techniques and apparatus for selectively triggering an AFP mode after completion of a soft start of a voltage on a power supply node included in a power supply circuit. For example, after completion of a soft start of a voltage of a power supply node, an AFP mode may be triggered when the voltage of the power supply node is less than a threshold voltage (V) of a transistor. Certain aspects described herein for providing short circuit protection may consume minimal current and may function even when the power supply circuit is in a shutdown (e.g., low power) mode.

Example Power Supply Circuit with Short Circuit Protection

is a circuit diagram of an example power supply circuitB that includes short circuit protection, in accordance with certain aspects of the present disclosure. The power supply circuitB may be similar to the power supply circuitA of, but also includes a logic circuit. For example, and as shown in, the logic circuitmay include a transistor Q, a first current source(labeled “I1”), a debounce circuit, and automatic fault protection (AFP) logic.

The output voltage nodemay be coupled to a gate of transistor Q. Transistor Qmay include a source coupled to the reference potential nodeand a drain coupled to a first terminal of the current sourceand the debounce circuit. The debounce circuitmay also be coupled to the AFP logicand may be configured to debounce signals (e.g., ringing or bouncing signals due to a sudden voltage level transition) from transistor Q. The debounce may last, for example, about 10 microseconds (μs). Transistor Qmay be implemented as an n-type field-effect transistor. In certain aspects, the current sourcemay be replaced by a resistive element (e.g., a relatively high resistance resistor, not shown). In some cases, the current sourcemay generate 0.5 microamperes (μA) of current.

The logic circuitmay be configured to detect a short circuit on the power supply node VPH1 (e.g., using a signal labeled “vph1_lt_vt” at the drain of transistor Q), after completion of a soft start of a voltage on the power supply node VPH1. With the topology of the logic circuitillustrated in, a short circuit is detected when the voltage of the power supply node VPH1 is less than a threshold voltage (V) of transistor Q. In response to the detection of the short circuit on the power supply node, the logic circuitmay be configured to trigger an AFP mode. In some case, in response to the AFP mode being triggered, the logic circuitmay be configured to cause transistor(s) QBATto open. In this manner, the AFP mode may prevent damage to transistor(s) QBAT. The logic circuitmay be configured to ignore the voltage of the power supply node VPH1 being less than the threshold voltage of transistor Q(e.g., to ignore the vph1_lt_vt signal) before and during the soft start of the voltage of the power supply node VPH1.