Package structure

This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 16/944,173, filed on Jul. 31, 2020. The prior application Ser. No. 16/944,173 is a continuation application of and claims the priority benefit of a prior application Ser. No. 15/900,808, filed on Feb. 21, 2018 and now allowed, which claims the priority benefit of U.S. provisional application Ser. No. 62/590,257, filed on Nov. 22, 2017. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

Semiconductor devices and integrated circuits used in a variety of electronic applications, such as cell phones and other mobile electronic equipment, are typically manufactured on a signal semiconductor wafer. The semiconductor chips of the wafer may be processed and packaged with other semiconductor devices, semiconductor chips, semiconductor package.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In addition, terms, such as “first,” “second,” “third,” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

toare schematic cross sectional views of various stages in a manufacturing method of a package structure in accordance with some exemplary embodiments of the present disclosure.is a schematic bottom view illustrating a relative position between a metallization layer of an interconnection structure, connecting pads, connecting vias, and a metallization layer of a redistribution structure of a package structure in accordance with some exemplary embodiments of the present disclosure, whereis an enlarged schematic bottom view showing the positioning configuration of an interconnection structure (e.g. a topmost metallization layer), connecting pads, connecting vias, and a redistribution structure (e.g. a bottommost metallization layer) of the package structuredepicted in(indicated by a dotted box X). Into, a package structureis shown to represent a package structure obtained following the manufacturing method, for example. In exemplary embodiments, the manufacturing method is part of a wafer level packaging process. It is to be noted that the processing steps described herein cover a portion of the manufacturing processes used to fabricate a package structure. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure. Into, one integrated circuit component is shown to represent signal or plural integrated circuit components, the disclosure is not limited thereto. In other embodiments, two or more integrated circuit components are shown to represent plural integrated circuit components, and two or more package structuresare shown to represent plural package structures obtained following the (semiconductor) manufacturing method, the disclosure is not limited thereto.

Referring to, in some embodiments, a carrier C having a de-bonding layer DB and an insulating layer IN formed thereon is provided. In some embodiments, the de-bonding layer DB is between the carrier C and the insulating layer IN. In some embodiments, the carrier C is a glass substrate, the de-bonding layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate, and the insulating layer IN is a polybenzoxazole (PBO) layer formed on the de-bonding layer DB, for example. It is noted that the formation of the insulating layer IN is optional in some alternative embodiments. It may also be noted that materials for the carrier C, the de-bonding layer DB, and the insulating layer IN are not limited to what are disclosed herein according to the disclosure.

In some embodiments, after the carrier C having the de-bonding layer DB and the insulating layer IN formed thereon is provided, a redistribution structureis formed over the carrier C, and then a plurality of conductive pillars CP and one or more integrated circuit componentsA are formed on the redistribution structure. The numbers of the conductive pillars CP and the integrated circuit componentsA may be selected based on demand, and are not limited in the disclosure. For example, in, the redistribution structureis formed on the insulating layer IN, and the formation of the redistribution structureincludes sequentially forming one or more polymer dielectric layersand one or more metallization layersin alternation. In some embodiments, the redistribution structureincludes one polymer dielectric layerand one metallization layeras shown in; however, the disclosure is not limited thereto. The numbers of the metallization layers and the polymer dielectric layers included in the redistribution structureis not limited thereto. For example, the numbers of the metallization layers and the polymer dielectric layers may be one or more than one.

As shown in, for example, a bottom surface of the metallization layeris covered by the insulating layer IN, and portions of a top surface of the metallization layerare exposed by the polymer dielectric layerfor connecting the conductive pillars CP. Due to the configuration of the redistribution structure, a routing function is provided to the package structure. The redistribution structureis referred as a back-side redistribution structure of the integrated circuit componentA, for example.

In certain embodiments, as shown in, the metallization layeris disposed on the insulating layer IN and covered by the polymer dielectric layer. In some embodiments, the material of the polymer dielectric layermay include polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material, and the polymer dielectric layermay be formed by deposition. In some embodiments, the material of the metallization layermay include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof, and the metallization layermay be formed by electroplating or deposition. The disclosure is not limited thereto.

In some embodiments, after the redistribution structureis formed on the insulating layer IN, the conductive pillars CP are formed on the redistribution structure. In some embodiments, the conductive pillars CP are formed over the carrier C (e.g., directly on the insulating layer IN) by photolithography, plating, and photoresist stripping process. In some alternative embodiments, the conductive pillars CP are pre-fabricated through other processes and are mounted over the carrier C. For example, the conductive pillars CP include copper posts or other metallic posts.

Continued on, in some embodiments, the integrated circuit componentA is picked-up and placed on the insulating layer IN carried by the carrier C. In some embodiments, the integrated circuit componentA is attached or adhered on the insulating layer IN through a connecting film DA. For example, the connecting film DA may be a die attach film, an adhesion paste or the like. In some embodiments, the integrated circuit componentA may have a thickness less than a height of the conductive pillars CP, as shown in. However, the disclosure is not limited thereto. In an alternative embodiment, the thickness of the integrated circuit componentA may be greater than or substantially equal to the height of the conductive pillars CP. As shown in, the integrated circuit componentA may be picked-up and placed on the insulating layer IN after the formation of the conductive pillars CP. However, the disclosure is not limited thereto. In an alternative embodiment, the integrated circuit componentA may be picked-up and placed on the insulating layer IN before the formation of the conductive pillars CP. The cross-sectional shape of the conductive pillars CP may be selected based on demand, and are not limited in the disclosure.

As shown in, the integrated circuit componentA includes a semiconductor diehaving an active surface, an interconnection structureformed on the active surface, contact padsformed on the interconnection structure, a protection layerpartially covering the contact pads, connecting viasconnecting to the contact padspartially exposed by the protection layer, and a passivation layerdisposed on the protection layerand wrapping at least sidewalls of the connecting vias.

In some embodiments, the semiconductor diemay be a silicon substrate including active components (e.g., transistors or the like) and/or passive components (e.g., resistors, capacitors, inductors or the like) formed therein. The disclosure is not limited thereto.

In some embodiments, the interconnection structureincludes the interconnection structureincludes one or more inter-dielectric layersand one or more patterned conductive layersstacked alternately. In certain embodiments, the patterned conductive layersare sandwiched between the inter-dielectric layers, where a top surface of a topmost layer of the patterned conductive layersis exposed by a topmost layer of the inter-dielectric layersand physically connected to the contact pads, and a bottommost layer of the patterned conductive layersis exposed by a bottommost layer of the inter-dielectric layersand electrically connected to the active components and/or passive components (not shown) formed in the semiconductor die. As shown in, the bottommost layer of the inter-dielectric layersis located on the active surfaceof the semiconductor die, and the topmost layer of the inter-dielectric layersis at least partially in contact with the contact pads. The numbers of the inter-dielectric layersand the patterned conductive layersmay be selected based on demand, and are not limited in the disclosure.

In one embodiment, the inter-dielectric layersmay be polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be patterned using a photolithography and/or etching process. In some embodiments, the inter-dielectric layersmay be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. In one embodiment, the patterned conductive layersmay be made of conductive materials formed by electroplating or deposition, such as copper, copper alloy, aluminum, aluminum alloy, or combinations thereof, which may be patterned using a photolithography and etching process. In some embodiments, the patterned conductive layersmay be patterned copper layers or other suitable patterned metal layers. Throughout the description, the term “copper” is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium, etc.

In some embodiments, the contact padsmay be aluminum pads, copper pads or other suitable metal pads, and may be formed by an electroplating process. In some embodiments, a size of the contact padsis ranging approximately from 10 μm to 80 μm, the disclosure is not limited thereto. In some embodiments, in a plane view of the package structurealong a stacking direction of the semiconductor die, the interconnection structure, the contact padsand connecting vias, the contact padsmay be in a polygon-shape (see the bottom view depicted in), a circle-shape, an ellipse-shape, a triangle-shape, a rectangle-shape, or the like. The number and shape of the contact padsmay be selected based on demand, and are not limited in the disclosure.

In some embodiments, the protection layerand/or the passivation layermay be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer or a dielectric layer formed by other suitable dielectric materials, and may be formed by an electroplating process. In some embodiments, the protection layerand/or the passivation layermay be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers, and may be formed by an coating process. The disclosure is not limited thereto. In one embodiment, the material of the protection layerand the passivation layermay be the same. In an alternative embodiment, the materials of the protection layerand the passivation layermay be different.

In some embodiments, the connecting viasincludes one or more signal connecting vias, one or more ground connecting vias, and one or more power connecting vias. In some embodiments, a size Rof each of the signal connecting vias, a size Rof each of the ground connecting viasand a size Rof the power connecting viaare ranging approximately from 10 μm to 80 μm, the disclosure is not limited thereto. As shown in, only two signal connecting vias, only two ground connecting vias, and only one power connecting viaare presented in FIG.for illustrative purposes, however, it should be noted that the numbers of the signal connecting vias, the ground connecting vias, and the power connecting viamay be selected or designated based on the demand and the design layout; the disclosure is not limited thereto.

As shown in, in some embodiments, the signal connecting viasare electrically connected to the interconnection structurethrough physically contacting the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layersand a respective one of the contact pads, the ground connecting viasare electrically connected to the interconnection structurethrough physically contacting the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layersand a respective one of the contact pads, and the power connecting viais electrically connected to the interconnection structure through physically contacting the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layersand a respective one of the contact pads. However, the disclosure is not limited thereto. In some alternative embodiments, the contact padsmay be omitted.

In some embodiments, the signal connecting vias, the ground connecting vias, and the power connecting viamay include copper pillars, copper alloy pillars or other suitable metal pillars, and may be formed by an electroplating process or the like. In one embodiment, the materials of the signal connecting vias, the ground connecting vias, and the power connecting viamay be the same. In an alternative embodiment, the materials of the signal connecting vias, the ground connecting vias, and the power connecting viamay be different. In some embodiments, in the plane view of the package structurealong the stacking direction of the semiconductor die, the interconnection structure, the contact padsand connecting vias, the signal connecting vias, the ground connecting vias, and the power connecting viamay be in a circle-shape (see the bottom view depicted in), an ellipse-shape, a triangle-shape, a rectangle-shape, or the like. In one embodiment, the shapes of the signal connecting vias, the ground connecting vias, and the power connecting viamay be the same. In an alternative embodiment, the shapes of the signal connecting vias, the ground connecting vias, and the power connecting viamay be the different from one another, and the disclosure is not limited thereto.

Referring to, an insulating encapsulationis formed over the carrier C (e.g., on the insulating layer IN) to encapsulate the integrated circuit componentA and the conductive pillars CP. In other words, the integrated circuit componentA and the conductive pillars CP are covered by and embedded in the insulating encapsulation. That is, the integrated circuit componentA and the conductive pillars CP are not accessibly exposed by the insulating encapsulation. In some embodiments, the insulating encapsulationis a molding compound formed by a molding process, and the material of the insulating encapsulationmay include epoxy or other suitable resins. For example, the insulating encapsulationmay be epoxy resin containing chemical filler(s).

Referring toand, in some embodiments, the insulating encapsulationis planarized until a top surface Sof the integrated circuit componentA (e.g., top surfaces of the signal connecting vias, the ground connecting vias, the power connecting via, and the passivation layer) and top surfaces Sof the conductive pillars CP are exposed. After the insulating encapsulationis planarized, a planarized insulating encapsulation′ is formed over the carrier C (e.g., on the insulating layer IN). That is, the signal connecting vias, the ground connecting viasand the power connecting viaof the integrated circuit componentA and the conductive pillars CP are accessibly exposed by the insulating encapsulation′. During the planarized process of the insulating encapsulation(shown in), the conductive pillars CP are also planarized. In some embodiments, as shown in, during the planarized process of the insulating encapsulation, a portion of the passivation layerand portions of the signal connecting vias, the ground connecting vias, and the power connecting viamay be planarized, also. The planarized insulating encapsulation′ may be formed by mechanical grinding or chemical mechanical polishing (CMP), for example. After the planarizing process, a cleaning step may be optionally performed, for example to clean and remove the residue generated from the planarizing step. However, the disclosure is not limited thereto, and the planarizing step may be performed through any other suitable method.

In some embodiments, as shown in, the planarized insulating encapsulation′ physically contacts a sidewall Sof the integrated circuit componentA and sidewalls Sof the conductive pillars CP. In other words, the integrated circuit componentA and the conductive pillars CP are mostly embedded in the planarized insulating encapsulation′ with only the top surface Sof the integrated circuit componentA and the top surface Sof the conductive pillars CP being accessibly exposed. In certain embodiments, the top surfaces of the signal connecting vias, the ground connecting vias, and the power connecting viaof the integrated circuit componentA and the top surfaces Sof the conductive pillars CP are substantially levelled with a top surfaceT′ of the planarized insulating encapsulation′. In other words, the top surfaces of the signal connecting vias, the ground connecting vias, and the power connecting viaof the integrated circuit componentA, the top surfaces Sof the conductive pillars CP, and the top surfaceT′ of the planarized insulating encapsulation′ are substantially coplanar with each other.

Referring to, in some embodiments, after the planarized insulating encapsulation′ is formed, a redistribution structureis formed on the planarized insulating encapsulation′. In some embodiments, the redistribution structureis formed on the top surfaceT′ of the planarized insulating encapsulation′, the top surfaces Sof the conductive pillars CP, and the top surfaces of the signal connecting vias, the ground connecting vias, and the power connecting via. In certain embodiments, the redistribution structureis fabricated to electrically connect with one or more connectors underneath. Here, the afore-said connectors may be the signal connecting vias, the ground connecting vias, and the power connecting viaof the integrated circuit componentA and the conductive pillars CP embedded in the planarized insulating encapsulation′, for example. In other words, the redistribution structureis electrically connected to the top surfaces Sof the conductive pillars CP, and the top surfaces of the signal connecting vias, the ground connecting vias, and the power connecting via.

Continued on, in some embodiments, the redistribution structureincludes a plurality of inter-dielectric layersand a plurality of patterned redistribution conductive layersstacked alternately. In certain embodiments, the patterned redistribution conductive layersare sandwiched between the inter-dielectric layers, where a top surface of a topmost layer of the patterned redistribution conductive layersis exposed by a topmost layer of the inter-dielectric layersand physically connected to with one or more overlying connectors (e.g. later-formed conductive terminal(s) or semiconductor device(s) such as passive element(s)), and a bottommost layer of the patterned redistribution conductive layersexposed by a bottommost layer of the inter-dielectric layerare electrically connected to with one or more underlying connectors (e.g. the signal connecting vias, the ground connecting viasand the power connecting viaof the integrated circuit componentA and the conductive pillars CP embedded in the planarized insulating encapsulation′). As shown in, in some embodiments, the top surfaces of the signal connecting vias, the ground connecting viasand the power connecting viaof the integrated circuit componentA and the top surfaces Sof the conductive pillars CP are in direct contact with the redistribution structure(e.g. the bottommost layer of the patterned redistribution conductive layersexposed by the bottommost layer of the inter-dielectric layer). In such embodiments, the top surfaces of the signal connecting vias, the ground connecting viasand the power connecting viaof the integrated circuit componentA and the top surfaces Sof the conductive pillars CP are in physical contact with the bottommost layer of the patterned redistribution conductive layers. In some embodiments, as shown in, the top surfaces of the signal connecting vias, the ground connecting viasand the power connecting viaof the integrated circuit componentA and the top surfaces Sof the conductive pillars CP are partially covered by the bottommost inter-dielectric layer. The numbers of the inter-dielectric layersand of the patterned redistribution conductive layersare not limited according to the disclosure.

In certain embodiments, the topmost patterned redistribution conductive layermay include a plurality of pads. In such embodiments, the above-mentioned pads may include a plurality of under-ball metallurgy (UBM) patternsfor ball mount and/or a plurality of connection padsfor mounting of passive components. The numbers of the under-ball metallurgy patternsand the number of the connection padsare not limited according to the disclosure.

As shown in, in some embodiments, after the redistribution structureis formed, a plurality of conductive ballsare placed on the under-ball metallurgy patterns, and at least one passive componentis mounted on the connection pads. The numbers of the conductive ballsand the passive componentare not limited according to the disclosure, and may be selected based on the demand. In some embodiments, the conductive ballsmay be placed on the under-ball metallurgy patternsthrough ball placement process, and the passive componentsmay be mounted on the connection padsthrough soldering process. In some embodiments, through the redistribution structureand the connection pads, the passive componentis electrically connected to the integrated circuit componentA. In some embodiments, through the redistribution structureand the connection pads, the passive componentis electrically connected to the conductive pillars CP. In some embodiments, through the redistribution structureand the metallurgy patterns, some of the conductive ballsare electrically connected to the integrated circuit componentA. In some embodiments, through the redistribution structureand the metallurgy patterns, some of the conductive ballsare electrically connected to the passive component. In some embodiments, through the redistribution structureand the metallurgy patterns, some of the conductive ballsare electrically connected to the conductive pillars CP. In some embodiments, through the redistribution structure, the metallurgy patternsand the conductive pillars CP, some of the conductive ballsare electrically connected to the redistribution structure. In certain embodiments, some of the conductive ballsmay be electrically floated or grounded, the disclosure is not limited thereto. As shown in, for example, through the redistribution structureand the conductive pillars CP, the integrated circuit componentA is electrically connected to the redistribution structure. For certain embodiments, through the redistribution structure, the conductive pillars CP, and the metallurgy patterns/the connection pads, the conductive balls/the passive componentmay be electrically connected to the redistribution structure.

Referring toand, in some embodiments, after the redistribution structure, the conductive ballsand the passive componentare formed, the insulating layer IN is de-bonded from the de-bonding layer DB carried by the carrier C, such that the insulating layer IN is separated from the carrier C. In embodiments where the de-bonding layer DB is the LTHC release layer, an UV laser irradiation may be utilized to facilitate peeling of the insulating layer IN from the carrier C. In certain embodiments, the insulating layer IN is exposed, as show in. In an alternative embodiment, the insulating layer IN may be removed from the redistribution structureafter debonding the carrier C and the de-bonding layer DB; the disclosure is not limited thereto.

In some embodiments, prior to debonding the de-bonding layer DB and the carrier C, the whole package structurealong with the carrier C may be flipped (turned upside down), where the conductive ballsand the passive componentare placed to a holding device (not shown) for securing the package structuresbefore debonding the carrier C and the de-bonding layer DB, and the carrier C is then debonded from the insulating layer IN. In some embodiments, the holding device may include a polymer film, and the conductive ballsand the passive componentare mounted into the polymer film. For example, the material of the polymer film may include a polymer film having sufficient elasticity to allow the conductive ballsand the passive componentbeing embedded therein. In certain embodiments, the holding device may be a parafilm or a film made of other suitable soft polymer materials or the like. In an alternative embodiment, the holding device may be an adhesive tape, a carrier film or a suction pad. The disclosure is not limited thereto.

Referring to, in some embodiments, an encapsulantis formed on the insulating layer IN and over the redistribution structure(e.g. the metallization layer), where the encapsulantcovers the insulating layer IN. In some embodiments, the insulating layer IN is sandwiched between the encapsulantand the redistribution structure. As shown in, the encapsulantis formed on a surface of the insulating layer IN facing away from the redistribution structure. In some embodiments, prior to forming the encapsulant, the conducive ballsmay be, for example, transferred to a temporary carrier (not shown, such as a tape, etc.) or a holding device as mentioned above for steadily holding the conductive ballsto avoid any damages to the conductive elements due to subsequent process(s). In some embodiments, the encapsulantincludes, for example, epoxy resins or any other suitable type of molding materials, where the material of the encapsulanthas low permittivity (Dk) and low loss tangent (Df) properties. Depending on the frequency range of the high-speed applications, suitable materials of the encapsulant may be selected based on the required electrical properties of the package.

In some embodiments, the materials of the encapsulantand the insulating encapsulation′ have low permittivity (Dk) and low loss tangent (Df) properties. With such condition, the material of the encapsulantmay be different from the material of the insulating encapsulation′, the disclosure is not limited thereto. In an alternative embodiment, the material of the encapsulantmay be the same as the material of the insulating encapsulation′.

In some embodiments, as shown in, antenna elementsare formed on formed on the encapsulant, and over the insulating layer IN and the metallization layerof the redistribution structure. The encapsulantis located between the antenna elementsand the insulating layer IN. As shown in, the antenna elementsare formed on a surface of the encapsulantfacing away from the redistribution structure. In some embodiments, the antenna elementsare electrically coupled with the metallization layerof the redistribution structure, where the metallization layerof the redistribution structureoverlapped with the antenna elementsserves as a ground plate and a feed-line for the antenna elements. Due to the use of the material having the low permittivity (Dk) and low loss tangent (Df) properties for forming the encapsulant, higher gain of the antenna elementsis obtained. As shown in, the antenna elementsare electrically communicated with the integrated circuit componentA through the redistribution structure.

In some embodiments, the antenna elementsare formed by forming a metallization layer (not shown) by electroplating or deposition over the encapsulantand then patterning the metallization layer by photolithographic and etching processes. In an alternative embodiment, the antenna elementsare formed by forming a metallization layer (not shown) by plating process. In some embodiments, the material of the first metallization layer includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the antenna elementsare arranged in form of a matrix, such as the N×N array or N×M arrays (N, M>0, N may or may not be equal to M). In some embodiment, the antenna elementsmay include patch antennas. For example, the package structureincludes the antenna elementsarranged in form of an array, such as a 2×2 array, however, the disclosure is not limited thereto. The size of the array for antenna elementsmay be designated and selected based on the demand.

Continued on, in some embodiments, a protection layeris formed over the antenna elementsand the encapsulant. As shown in, the protection layercovers the antenna elementsand the exposed portions of the encapsulant, for example. In some embodiments, the material of the protection layermay include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof or the like, which may be formed by suitable fabrication techniques such as deposition, spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like. The disclosure is not limited thereto. In one embodiment, the materials of the protection layer, the dielectric layer IN, the inter-dielectric layerand/or the polymer dielectric layersmay be the same. In an alternative embodiment, the material of the protection layermay be different from the materials of the dielectric layer IN, the inter-dielectric layerand/or the polymer dielectric layers

In an alternative embodiment, the package structuremay further include one or more end-fire radiation antennas (not shown), and each of the end-fire radiation antennas is constituted by two of the conductive pillars CP and located aside of the integrated circuit componentA along edges of the package structure. In one embodiment, for the two the conductive pillars CP in each end-fire radiation antenna, one conductive pillar CP is electrically connected to a part of the redistribution structureor a part of the redistribution structure(one of which serves as a feed line of the end-fire radiation antenna); and the other conductive pillar CP, which is electrically connected to the other one of a part of the redistribution structureor a part of the redistribution structureand is electrically grounded, serves as a ground plate/line of the end-fire radiation antenna. For example, the end-fire radiation antennas may be a dipole antennas with horizontal polarization or vertical polarization, the disclosure is not limited thereto.

In some embodiments, a dicing process is performed to cut the wafer having a plurality of package structuresinto individual and separated package structures. In one embodiment, the dicing process is a wafer dicing process including mechanical blade sawing or laser cutting. Up to here, the manufacture of the package structureis completed.

In an alternative embodiment, an additional package (not shown) may be provided. In certain embodiments, the additional package may be stacked over and electrically connected to the integrated circuit componentA depicted inthrough the conductive balls, such that a package-on-package (POP) structure is fabricated. However, the disclosure is not limited thereto. In another alternative embodiment, a semiconductor circuit board (not shown) may be provided and electrically connected to the integrated circuit componentA depicted inthrough the conductive balls, where the semiconductor circuit board may be a printed circuit board.

Referring toandtogether, in certain embodiments, one signal connecting viaand a respective one contact padimmediately there-below and connecting thereto are together referred as a signal terminal of the integrated circuit componentA for electrically connecting the integrated circuit componentA and other components included in the package structure(for example, for an electrical connection between two integrated circuit components, between an integrated circuit component and a redistribution structure, etc.), where the respective one contact padis referred as a signal contact pad. As shown in, the signal terminals each including one signal connecting viaand the respective contact padare electrically connected to the interconnection structureby physically contacting the top surface of the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layers, for example. However, the disclosure is not limited thereto; and in an alternative embodiment, the signal terminals may exclude the respective contact pad. In one embodiment, some of the signal terminals may include the respective contact pad, and rest of the signal terminals may exclude the respective contact pad.

In some embodiments, one ground connecting viasand a respective one contact padimmediately there-below and connecting thereto are together referred as a ground terminal of the integrated circuit componentA for electrically grounding the integrated circuit componentA (for example, for an electrical connection between an integrated circuit component and an external component being electrically grounded), where the respective one contact padis referred as a ground contact pad. As shown in, the ground terminals each including one power ground pillarsand the respective contact padare electrically connected to the interconnection structureby physically contacting the top surface of the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layers, for example. However, the disclosure is not limited thereto; and in an alternative embodiment, the ground terminals may exclude the respective contact pad. In one embodiment, some of the ground terminals may include the respective contact pad, and rest of the ground terminals may exclude the respective contact pad.

In some embodiments, one power connecting viaand a respective one contact padimmediately there-below and connecting thereto are together referred as a power terminal of the integrated circuit componentA for electrical connecting the integrated circuit componentA to a power source (for example, for an electrical connection between an integrated circuit component and an external component providing an electric power), where the respective one contact padis referred as a power contact pad. As shown in, the power terminal including one power connecting viaand the respective contact padis electrically connected to the interconnection structureby physically contacting the top surface of the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layers, for example. However, the disclosure is not limited thereto; and in an alternative embodiment, the power terminal(s) may exclude the respective contact pad. In one embodiment, some of the power terminals may include the respective contact pad, and rest of the power terminals may exclude the respective contact pad.

There are only two signal terminals, two ground terminals and one power terminal illustrated into; however, the disclosure is not limited thereto. The numbers of the signal terminals, the ground terminals, and the power terminals are not limited to the disclosure, and may be selected and designated based on the demand and the design layout. In the disclosure, in some embodiments, the ground terminals are also considered as a type of the power terminal.

In some embodiments, as shown inand, a size Rof the signal connecting viasis less than a size Rof the power connecting via, the size Rof the signal connecting viasis less than the size Rof the ground connecting vias, and the size Rof the ground connecting viasis substantially equal to a size Rof the power connecting via, however the disclosure is not limited thereto. In one embodiment, the size Rof the signal connecting viasis less than the size Rof the power connecting via, the size Rof the signal connecting viasis substantially equal to the size Rof the ground connecting vias, and the size Rof the ground connecting viasis less than to the size Rof the power connecting via. In an alternative embodiment, the size Rof the signal connecting viasis less than the size Rof the power connecting via, the size Rof the signal connecting viasis less than the size Rof the ground connecting vias, and the size Rof the ground connecting viasis less than a size Rof the power connecting via.

Due to the size differences between the signal connecting vias, the ground connecting vias, and the power connecting via, the contact padscorresponding to the signal connecting vias, the ground connecting vias, and the power connecting viaalso have different sizes. In one embodiment, as shown in, a size of the contact padscorresponding to the signal connecting viasis less than a size of the contact padscorresponding to the power connecting via, the size of the contact padscorresponding to the signal connecting viasis less than a size of the contact padscorresponding to the ground connecting vias, and the size of the contact padscorresponding to the ground connecting viasis less than or substantially equal to the size of the contact padscorresponding to the power connecting via. In an alternative embodiment, the size of the contact padscorresponding to the signal connecting viasis less than the size of the contact padscorresponding to the power connecting via, the size of the contact padscorresponding to the signal connecting viasis less than or substantially equal to the size of the contact padscorresponding to the ground connecting vias, and the size of the contact padscorresponding to the ground connecting viasis less than the size of the contact padscorresponding to the power connecting via.

In certain embodiments, similarly, due to the size differences between the signal connecting vias, the ground connecting vias, and the power connecting via, a size of the exposed top surface of the topmost layer of the patterned conductive layerscorresponding to the contact padsrespectively and immediately underlying the signal connecting vias, the ground connecting vias, and the power connecting viaalso have different sizes, which has a size relationship there-between similar to the respective contact padsand thus is not repeated herein. Due to the above configuration, the power loss and/or the reflected power of the package structureare reduced, thereby protecting active circuits of the package structureand achieving a low power consumption. In addition, due to the size Rof the signal connecting viasis less than the size Rof the power connecting via, an overall area of the package structureis reduced.

Additionally, as shown inand, portions of the bottommost layer of the patterned redistribution conductive layersexposed by the bottommost layer of the inter-dielectric layerare respectively mechanically and electrically connected to the top surfaces of the signal terminals (e.g. the top surfaces of the signal connecting vias) and the top surfaces of the power terminal (e.g. the top surfaces of the power connecting via), which serve as conductive lines for signal transmission or for power supply to the integrated circuit componentA, while other portions of the bottommost layer of the patterned redistribution conductive layersexposed by the bottommost layer of the inter-dielectric layerare mechanically and electrically connected to the top surfaces of the ground terminals (e.g. the top surfaces of the ground connecting vias), which serve as the ground plate for the integrated circuit componentA. As shown in, in some embodiments, the portions of the bottommost layer of the patterned redistribution conductive layersconnecting to the signal terminals is separated from the other portions of the bottommost layer of the patterned redistribution conductive layersconnecting to the ground terminal by a slit ST. In one embodiment, the slit STmay include a constant width. In an alternative embodiment, the slit STmay include a non-constant width. In certain embodiments, the portions of the bottommost layer of the patterned redistribution conductive layersconnecting to the power terminal is separated from the other portions of the bottommost layer of the patterned redistribution conductive layersconnecting to the ground terminal by a slit ST. In one embodiment, the slit STmay include a constant width. In an alternative embodiment, the slit STmay include a non-constant width. With such slits STand ST, short circuit occurred in operating the package structureis further prevented.

is a schematic cross sectional view illustrating a package structure in accordance with some exemplary embodiments of the present disclosure. Referring toandtogether, the package structuredepicted inand the package structuredepicted inare similar; such that the elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements and the relationship thereof (e.g. the relative positioning configuration and electrical connection) will not be repeated herein. Referring toandtogether, the difference is that, for the package structuredepicted in, the package structureincludes an integrated circuit componentB, where the contact padsare omitted. As shown in, the signal connecting vias, the ground connecting vias, and the power connecting viaare electrically connected to the topmost layer of different and separated portions of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layersby direct contact (e.g. mechanical or physical contact). That is, for example, each of the signal terminals include one signal connecting viawithout the presence of the signal contact pad, each of the ground terminals include one ground connecting viawithout the presence of the ground contact pad, and the power terminals include one power connecting viawithout the presence of the power contact pad. With such configuration, the total manufacture cost is reduced.

is a schematic cross sectional view illustrating a package structure in accordance with some exemplary embodiments of the present disclosure.is a schematic bottom view illustrating a relative position between a metallization layer of an interconnection structure, connecting pads, connecting vias, and a metallization layer of a redistribution structure of a package structure in accordance with some exemplary embodiments of the present disclosure, whereis an enlarged schematic bottom view showing the positioning configuration of an interconnection structure (e.g. a topmost metallization layer), connecting pads, connecting vias, and a redistribution structure (e.g. a bottommost metallization layer) of the package structuredepicted in(indicated by a dotted box Y). Referring toandtogether, the package structuredepicted inand the package structuredepicted inare similar; such that the elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements and the relationship thereof (e.g. the relative positioning configuration and electrical connection) will not be repeated herein. Referring toandtogether, the difference is that, for the package structuredepicted in, the package structureincludes an integrated circuit componentC, where the size Rof the signal connecting viasis less than the size Rof the power connecting via, the size Rof the signal connecting viasis substantially equal to the size Rof the ground connecting vias, and the size Rof the ground connecting viasis less than to the size Rof the power connecting via. With such configuration, the package structureachieves better impedance match and lower power loss.

is a schematic cross sectional view illustrating a package structure in accordance with some exemplary embodiments of the present disclosure. Referring toandtogether, the package structuredepicted inand the package structuredepicted inare similar; such that the elements similar to or substantially the same as the elements described above will use the same reference numbers, and certain details or descriptions of the same elements and the relationship thereof (e.g. the relative positioning configuration and electrical connection) will not be repeated herein. Referring toandtogether, the difference is that, for the package structuredepicted in, the package structureincludes an integrated circuit componentD, where the contact padsare omitted. As shown in, the signal connecting vias, the ground connecting viasand the power connecting viaare electrically connected to the topmost layer of the patterned conductive layersexposed by the topmost layer of the inter-dielectric layersby direct contact (e.g. mechanical or physical contact). That is, for example, each of the signal terminals include one signal connecting viawithout the presence of the signal contact pad, each of the ground terminals include one ground connecting viawithout the presence of the ground contact pad, and the power terminals include one power connecting viawithout the presence of the power contact pad. With such configuration, the total manufacture cost is reduced.