Voltage reference circuit and a power management unit

The present application claims the benefit of and priority to EP Patent Application Serial No. 22168722.1, filed Apr. 19, 2022, the entire contents of which is incorporated herein by reference.

The present description relates to a voltage reference circuit which is configured to generate a reference voltage. The present description further relates to a power management unit comprising the voltage reference circuit.

Voltage reference circuits are used for providing a reliable reference voltage, which may further be used to control electronic circuits. For instance, a power management unit typically uses a voltage reference circuit in order to provide a reliable reference voltage, which can be used to generate direct current (DC) voltages and currents for biasing or supplying to an electronic circuit.

The reference voltage output by the voltage reference circuit should provide a stable voltage level which is not affected or minimally affected by parameter variations, such as temperature variations or variations in supply voltage to the reference voltage circuit.

In addition, the voltage reference circuit should be able to consume very small power levels. In particular, the voltage reference circuit may be used in small devices, such as Internet of Things (IoT) devices that may be almost exclusively in a sleep mode and only awake for brief moments of time. Thus, power consumption of such devices is mainly based on the power consumed during sleep mode. The voltage reference circuit may however be always-on and therefore the power consumption of the voltage reference circuit may be of huge importance.

Voltage reference circuits operating in a subthreshold region of transistors may provide a low power consumption. However, the reference voltages output by such voltage reference circuits may be quite low. Therefore, it may be desired to provide a scalable output voltage.

In Lee et al: “-”, IEEE Journal of Solid-State Circuits, Vol. 52, No. 5, 2017, pp. 1443-1449, a voltage reference circuit is described for providing a relatively large output reference voltage. The voltage reference circuit has four stacked p-type metal-oxide-semiconductor (pMOS) transistors. However, each stacked pMOS transistor provides an increase of reference voltage while producing additional noise and consuming additional power. Hence, the output reference voltage is very sensitive to variations in supply voltage to the voltage reference circuit.

An objective of the present description is to provide a voltage reference circuit with a possibility to provide a relatively high output reference voltage with a low power consumption and an insensitivity to parameter variations, such as variations in supply voltage and/or temperature.

This and other objectives are at least partly met by the invention as defined in the independent claims. Preferred embodiments are set out in the dependent claims.

According to a first aspect, there is provided a voltage reference circuit comprising: a first transistor comprising a gate terminal, a source terminal, and a drain terminal; a second transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a first voltage is provided at a first node between the first transistor and the second transistor; a first regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the first regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a second voltage is provided at a second node between the second transistor and the first regulating transistor, and wherein the first regulating transistor is connected to the first node for compensating changes in the first voltage at the first node to maintain a stable first voltage level; and a second regulating transistor comprising a gate terminal, a source terminal, and a drain terminal, wherein the second regulating transistor is connected between the supply voltage and the second transistor in a stacked connection with the first regulating transistor, wherein a third voltage is provided at a third node between the first regulating transistor and the second regulating transistor, and wherein the second regulating transistor is connected to the second node for compensating changes in the second voltage at the second node to maintain a stable second voltage level; wherein the voltage reference circuit is configured to output at least one of the first voltage, the second voltage, or the third voltage as a reference voltage.

According to the first aspect, a first regulating transistor and a second regulating transistor are added to a voltage reference circuit having a first transistor and a second transistor. The first regulating transistor and the second regulating transistor are configured to provide compensation for any changes in a voltage level at the first node and second node, respectively. This implies that the regulating transistors are configured to ensure that a stable reference voltage may be output such that even though the regulating transistors may slightly add to power consumption of the voltage reference circuit, the regulating transistors are useful in enabling output of a reference voltage that is insensitive to parameter variations, such as temperature variations or variations in supply voltage to the reference voltage circuit.

Further, since the regulating transistors are arranged in a stacked connection with the first and second transistors, the second voltage at the second node is larger than the first voltage at the first node (as there are two transistors stacked between ground and second node compared to only the first transistor being arranged between ground and the first node). Similarly, the third voltage at the third node is larger than the second voltage at the second node. Thus, the voltage reference circuit enables scaling of a reference voltage compared to using only the first and the second transistor in the voltage reference circuit.

The voltage reference circuit may be used for outputting any one of the first voltage, the second voltage, or the third voltage as the reference voltage. The first voltage has a very low sensitivity to parameter variations, since the first voltage level is affected by two rounds of regulation, via the first regulating transistor and the second regulating transistor. The second voltage is larger than the first voltage and is also insensitive to parameter variations, thanks to the regulation provided by the second regulating transistor. The third voltage is even larger than the second voltage but may not be as insensitive to parameter variations.

Thus, if it is desired that the output reference voltage should have very low sensitivity to parameter variations, the voltage reference circuit may be set up to output the first voltage as the reference voltage. If it is desired that a relatively large reference voltage is to be provided with still low sensitivity to parameter variations, the voltage reference circuit may be set up to output the second voltage as the reference voltage. If it is desired that a large reference voltage is provided, the voltage reference circuit may be set up to output the third voltage as the reference voltage.

The voltage reference circuit may thus be utilized in different manners depending on desired properties of the reference voltage. Also, the voltage reference circuit may be configured to output more than one reference voltage. Thus, the voltage reference circuit may provide more than one level of reference voltage.

The definition that transistors are arranged in a stacked connection should be understood such that the transistors are connected in series for providing a common direction of current through the transistors in the voltage reference circuit. Thus, a current between drain and source through one transistor may continue between drain and source of the other transistor in the stacked connection. In other words, if the transistors are of same type, the transistors may be connected with drain of one transistor in the stacked connection connected to source of the other transistor in the stacked connection. If the transistors are of opposite type, the transistors may be connected with source of one transistor connected with source of the other transistor in the stacked connection.

Further, the transistors being arranged in stacked connection between two terminals (e.g., first transistor and second transistor are arranged in stacked connection between a terminal connected to ground and a terminal connected to supply voltage) implies that drain or source of one transistor is connected to one of the two terminals and drain or source of the other transistor is connected to the other of the two terminals.

As used herein, the term “connected” should be construed as comprising directly connected, such that no components are arranged between the terminals/devices that are connected unless stated otherwise. The stacked connection of transistors being described in relation to the supply voltage does however not necessarily mean that the transistor is directly connected to the supply voltage. Rather, further transistors may be stacked between the supply voltage and the transistors of the described stacked connection. For instance, at least the second regulating transistor is arranged between the supply voltage and the first regulating transistor. Similarly, additional regulating transistor(s) may be arranged between the supply voltage and the second regulating transistor and/or may be arranged between the first regulating transistor and the second regulating transistor. This also implies that the third node need not be directly connected to the first regulating transistor and the second regulating transistor. Rather, the third node may be arranged between any two regulating transistors in a stack if the voltage reference circuit comprises more than two regulating transistors. This may also imply that the third voltage at the third node may in fact be regulated by being connected to an additional regulating transistor for compensating changes in the third voltage.

The first regulating transistor is connected in a stacked connection with the second transistor, the second transistor being between the first regulating transistor and the first node. The first regulating transistor is further connected to the first node for compensating changes in the first voltage. The first regulating transistor may thus receive feedback from the first node such that any changes in the first voltage may affect the regulating transistor and may be compensated for by the first regulating transistor via the second transistor back to the first node. Thus, the first regulating transistor may be connected to the first node by the gate terminal of the first regulating transistor being connected to the first node or by a bulk terminal (if available) of the first regulating transistor being connected to the first node. Similarly, the second regulating transistor may be connected to the second node by the gate terminal of the second regulating transistor being connected to the second node or by a bulk terminal (if available) of the second regulating transistor being connected to the second node.

According to an embodiment, the voltage reference circuit further comprises at least one additional regulating transistor, wherein each of the at least one additional regulating transistor is connected to another regulating transistor in a same manner as the second regulating transistor is connected to the first regulating transistor.

This may be used for further scaling a reference voltage output by the voltage reference circuit. It may also or alternatively be used for providing further rounds of regulation of the voltage levels.

Thus, the first regulating transistor, the second regulating transistor and the additional regulating transistors form a stack between the supply voltage and the second transistor. Also, an additional node is provided between each pair of regulating transistors in the stack. The voltage at such additional node may be output as additional reference voltage. Further, the additional node is also connected to the regulating transistor arranged immediately above the pair of regulating transistors in the stack for compensating changes in the voltage at the additional node.

For example, if the voltage reference circuit comprises a third regulating transistor, the third regulating transistor is connected between the supply voltage and the first regulating transistor in a stacked connection with the second regulating transistor. The first, second, and third regulating transistors thus form a stack between the second transistor and the supply voltage. Further, the third node is between the pair of the first regulating transistor and the second regulating transistor, and the third node is also connected to the third regulating transistor arranged immediately above the pair of the first and second regulating transistors in the stack for compensating changes in the voltage at the third node.

According to an embodiment, the first transistor, the second transistor, the first regulating transistor, and the second regulating transistor are all n-type metal-oxide-semiconductor (nMOS) transistors, and wherein a drain terminal of the first transistor is connected to a source terminal of the second transistor, a drain terminal of the second transistor is connected to a source terminal of the first regulating transistor and a drain terminal of the first regulating transistor is connected to a source terminal of the second regulating transistor, and wherein the first node is connected to the drain terminal of the first transistor and the source terminal of the second transistor, the second node is connected to the drain terminal of the second transistor and the source terminal of the first regulating transistor, and the third node is connected to the drain terminal of the first regulating transistor and the source terminal of the second regulating transistor.

It should however be realized that the first transistor may be a pMOS transistor instead in combination the second transistor and the regulating transistors being nMOS transistors. In such case, a source terminal of the first transistor may be connected to the source terminal of the second transistor and the first node may be connected to the source terminal of the first transistor.

The drain terminal of the second transistor may thus be connected to the source terminal of the first regulating transistor. Further, the source terminal of the second transistor is connected to the first node, which is further connected to, for example, the gate terminal of the first regulating transistor (it should be realized that the first node may alternatively be connected to a bulk terminal of the first regulating transistor). This implies that the drain-to-source voltage of the second transistor (V) is equal to a negative of the gate-to-source voltage of the first regulating transistor (V), i.e., V=−V. Thus, any fluctuation in parameters, such as change in temperature or supply voltage, causing Vto change will result in the change being sensed by the gate-to-source voltage of the first regulating transistor Vand being directly fed back to change Vin an opposite direction. Thus, drain current of the second transistor will change to bring the first voltage at the first node back to an original value. Hence, a stable first voltage level is maintained.

It should be realized that at least the second voltage at the second node may be regulated in a corresponding manner using the second regulating transistor such that a stable second voltage level is also maintained.

According to an embodiment, an aspect ratio of the first regulating transistor equals an aspect ratio of the second transistor.

This may imply that the circuit is easy to manufacture as the transistors may be identical.

Further, the behavior of the second transistor and the first regulating transistor may be identical based on having the same aspect ratios. With equal drain currents flowing through the second transistor and the first regulating transistor, voltage levels may be easily controlled when the aspect ratio is equal. Also, when the second transistor and the first regulating transistor have the same aspect ratio, the second voltage at the second node may be two times larger than the first voltage at the first node. This implies that the voltage level is substantially increased between the first node and the second node.

The aspect ratio may be defined as a width of a channel of the transistor divided by a length of the channel.

When additional regulating transistors are present such that the stack of regulating transistors is formed between the supply voltage and the second transistor, all of the regulating transistors may have the same aspect ratio as the second transistor. This may facilitate control of voltage levels of the voltage reference circuit and also it may ensure that the voltage level is scaled by an equal amount between adjacent nodes in the voltage reference circuit (difference between third and second voltage is equal to difference between second and first voltage, and so on).

The topmost regulating transistor in the stack of regulating transistors, which is directly connected to the supply voltage, may have a different aspect ratio than the other regulating transistors in the stack. The topmost regulating transistor may be sized slightly differently to compensate for non-idealities in the voltage reference circuit. If there are only two regulating transistors, the second regulating transistor may thus be differently sized compared to the first regulating transistor.

According to an embodiment, the voltage reference circuit is configured to output a reference voltage from a node having a largest voltage and being regulated by a regulating transistor.

When a node is regulated by a regulating transistor, the voltage level output at the node will be maintained at a stable level. Thus, by outputting the reference voltage from the node having the largest voltage and being regulated, a large reference voltage is provided while also a stable level of the reference voltage is provided.

If the voltage reference circuit comprises only the first and the second regulating transistors, the third node is not regulated by any regulating transistor (because the third node is not connected to any regulating transistor for compensating changes in the third voltage). Thus, in such case, the voltage reference circuit outputting a reference voltage from a node having a largest voltage and being regulated by a regulating transistor would be configured to output the reference voltage from the second node.

A top node between the topmost regulating transistor in the stack and the regulating transistor directly connected to the topmost regulating transistor will not be regulated. Thus, even though this top node provides a larger voltage than the node having largest regulated voltage, the voltage reference circuit may preferably not use this top node for providing the reference voltage since the voltage level at this top node may be sensitive to parameter variations. However, it should be realized that the voltage level at the top node may still be relatively insensitive to parameter variations and that in some embodiments it may still be useful for output of the reference voltage.

The node between the pair of regulating transistors closest to the topmost regulating transistor will be the node having the largest voltage and being regulated by a regulating transistor (being regulated by the topmost regulating transistor).

According to another embodiment, the voltage reference circuit is configured to output a reference voltage from the first node.

Even though the first voltage at the first node is smaller than the voltages at other nodes (second node, third node, etc.), it may still be desired in some embodiments that the voltage reference circuit outputs the first voltage as the reference voltage. The first voltage may be very well regulated based on a multitude of regulating transistors affecting the voltage level at the first node. This implies that the first voltage may be very insensitive to parameter variations. Thus, if having a reference voltage which is stable is of utmost importance, the first node may be used for output of the reference voltage.

According to an embodiment, the voltage reference circuit is configured to output more than one reference voltage.

Thus, the voltage reference circuit may output voltage from more than one of the first to third nodes (and also from additional nodes). This may be useful when several different levels of voltages are needed in an electronic circuit.

Further, the voltage level is scaled by an equal amount between adjacent nodes in the voltage reference circuit (difference between third and second voltage is equal to difference between second and first voltage, and so on). Thus, when a plurality of reference voltages is output, each of the reference voltages may be defined by an integer number times the first voltage.

For instance, the voltage reference circuit may provide reference voltages that may be used by a successive approximation register analog-to-digital converter, in which a sampled value is compared to a plurality of different levels in order to digitize the sampled value.

According to an embodiment, each of the first transistor, the second transistor, the first regulating transistor and the second regulating transistor further comprises a bulk terminal, and wherein the first node is connected to the bulk terminal of the first regulating transistor, and the second node is connected to the bulk terminal of the second regulating transistor.

This may facilitate implementation of the voltage reference circuit in technology in which bulk terminal of transistors is available, such as in fully-depleted silicon-on-insulator (FD-SOI) technology.

Also, it should be realized that the first terminal need not use a bulk terminal. Thus, even though the second transistor, the first regulating transistor and the second regulating transistor may comprise a bulk terminal, the first terminal need not do so.

It should be realized that although conventional complementary metal-oxide-semiconductor (CMOS) technology may not provide a bulk terminal providing an extra gate terminal for individually controlling transistors, the voltage reference circuit may be implemented in CMOS technology. For instance, the second transistor, the first regulating transistor, and the second regulating transistor may be implemented as nMOS transistors associated with deep n-wells for providing bulk terminals of the nMOS transistors.

Thanks to the first node being connected to the bulk terminal of the first regulating transistor, the first regulating transistor receives feedback from the first node on its bulk terminal. This implies that any change in the first voltage affects the bulk terminal of the first regulating transistor such that the first voltage can be maintained at a stable, unchanged first voltage level. In the same way, the second regulating transistor receives feedback from the second node on its bulk terminal such that the second voltage can be maintained at a stable, unchanged second voltage level.

By connecting the first and second nodes to bulk terminals of the first and second regulating transistors, respectively, body effect of the regulating transistors is utilized for maintaining stable voltage levels. This implies that losses due to body effects in scaling of the voltage between different nodes may be avoided.