Memory system and control method

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-109957, filed Jul. 4, 2023, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a memory system that includes a non-volatile memory, and a control method of controlling the memory system.

In recent years, memory systems that include non-volatile memories have widely been in widespread use. As one of such memory systems, a solid state drive (SSD) including an NAND-type flash memory has been known.

In these days, it is demanded to achieve a memory system that is helpful to effective use of a storage space of a non-volatile memory, and is effective in protecting user data stored in the memory system.

An aspect that an embodiment of the present invention intends to achieve is to provide a memory system and a control method that are helpful to effective use of a storage space of a non-volatile memory, and is effective in protecting user data.

Various embodiments will be described hereinafter with reference to the accompanying drawings.

In general, according to one embodiment, a memory system connectable to a host, includes a non-volatile memory and a controller having circuitry configured to manage a plurality of namespaces, and control the non-volatile memory, the namespaces being used by the host in order to access the memory system. The circuitry compresses a write data item received from the host, encrypts the compressed data, using an encryption key, determines a compression unit that is a unit of compressing the write data item, for each of the namespaces, determines a first compression unit in response to reception of a write command designating a namespace identifier of a write-destination namespace from the host, the first compression unit being calculated based on first namespace setting information indicating setting of the write-destination namespace, corresponding to the write-destination namespace, and having a size satisfying a constraint that an encryption key for encrypting data to be written into the write-destination namespace is not switched in the first compression unit and compresses data specified by the write command according to the first compression unit.

Hereinafter, embodiments are described with reference to the drawings.

is a block diagram showing a configuration example of an information processing systemthat includes a memory systemaccording to a first embodiment. The information processing systemincludes a host, and the memory system. The hostand the memory systemare connectable to each other via a bus.

The hostis an information processing apparatus. The hostis, for example, a personal computer, a server computer, or a mobile terminal. The hostaccesses the memory system. Specifically, the hosttransmits (or more generally, as used herein, conveys), to the memory system, a write command that is a command for writing data. Furthermore, the hosttransmits, to the memory system, a read command that is a command for reading data.

The memory systemis a storage device connectable to the host. The memory systemis achieved by a solid state drive (SSD). The memory systemincludes a non-volatile memory. The memory systemwrites data into the non-volatile memory. Furthermore, the memory systemreads data from the non-volatile memory.

Communication between the memory systemand the hostis executed via the bus. The busis a transmission path that connects the hostand the memory systemto each other. The busis, for example, a PCI Express™ (PCIe™) bus. The hostand the memory systemtransmit and receive data, input/output (I/O) commands, and their responses, via the PCIe bus. The I/O command is a command for writing data into the non-volatile memory, or reading data from the non-volatile memory. The I/O command is, for example, a write command or a read command.

For example, the NVM Express™ (NVMe™) standard can be used as a logical interface standard for connecting the hostand the memory systemto each other. According to the interface of the NVMe standard, transmission and reception of a command and its response are executed between the hostand the memory systemusing a pair of queues that includes at least one submission queue (SQ) and a completion queue (CQ) associated with this submission queue (SQ). The pair of queues is called a submission queue/completion queue pair (SQ/CQ pair). The hostissues a command by storing the command in the submission queue (SQ), and processes a completion response stored in the completion queue (CQ), thus verifying whether the process for the issued command has been completed or not. The memory systemfetches the command stored in the submission queue (SQ) to thus receive the command from the host, and stores the completion response corresponding to the command having been processed, in the completion queue (CQ) to thus notify the hostthat the process for the command has been completed.

Next, the configuration of the hostis described.

The hostincludes a processor, and a memory. The processorand the memoryare connected to each other via an internal bus.

The processoris, for example, a CPU. The processorexecutes software (host software) loaded from the memory system, or another storage device connected to the host, into the memory. The host software includes, for example, an operating system, a file system, and an application program.

The memoryis, for example, a volatile memory. The memoryis also called a main memory, a system memory, or a host memory. The memoryis, for example, a dynamic random access memory (DRAM). Part of the memory area of the memoryis used to store the SQ/CQ pair. Another part of the memory area of the memoryis used as a data buffer. The data buffer stores write data to be written into the memory system, or read data transferred from the memory system.

Next, an internal configuration of the memory systemis described. The memory systemincludes a controller, and a non-volatile memory. The memory systemmay further include a random access memory, e.g., a dynamic random access memory (DRAM).

The controlleris a memory controller. The controlleris, for example, a control circuit, such as a system-on-a-chip (SoC). The controlleris electrically connected to the non-volatile memory. The controllerprocesses I/O commands received from the host, thereby respectively executing a data reading process for reading data from the non-volatile memory, and a data writing process for writing data into the non-volatile memory. For example, the Toggle NAND Flash Interface, or the Open NAND Flash Interface (ONFI) is used as a physical interface that connects the controllerand the non-volatile memoryto each other. A function of each component of the controllercan be achieved by dedicated hardware, a processor for executing a program, or a combination of them.

An example of the non-volatile memoryis, for example, an NAND-type flash memory. The non-volatile memorymay be a flash memory having a two-dimensional structure, or a flash memory having a three-dimensional structure. The non-volatile memoryincludes, for example, a plurality of memory chips. The memory chips are also called memory dice. The memory chips are respectively achieved as NAND-type flash memory dice. Hereinafter, the memory chip is called the NAND chip.shows a case where the non-volatile memoryincludes 32 NAND chips #0 to #31.

A DRAMis a volatile memory. Part of the memory area of the DRAMis used to store management data used by the controller, for example.

Next, an internal configuration of the controlleris described. The controllerincludes a host interface (host I/F), a CPU, an encryption key management circuit, an error-correcting code (ECC) processing circuit, a DRAM interface (DRAM I/F), a compression circuit, a decompression circuit, an encryption circuit, a decryption circuit, a buffer memory, and a non-volatile memory interface (non-volatile memory I/F). These host interface, CPU, encryption key management circuit, ECC processing circuit, DRAM interface, compression circuit, decompression circuit, encryption circuit, decryption circuit, buffer memory, and non-volatile memory interfaceare connected to each other via an internal bus.

The host interfaceis a communication interface circuit that executes communication with the host. The host interfacereceives (fetches) various commands, such as a write command and a read command, from the host. The host interfacethen transmits, to the host, a response (e.g., completion response) corresponding to a command processed by the controller.

The write command is a command that requests the memory systemto write user data (write data item) into the non-volatile memory. The write command designates, for example, a namespace identifier for identifying a write-destination namespace, a write-destination logical address (start LBA) in the write-destination namespace, the size of write data item (number of LBAs) associated with the write command, and a data pointer indicating the position in the memoryin which the write data item is stored. The write-destination namespace is a namespace in which the write data item is to be written. The write-destination logical address is an initial logical address where the write data item is to be written.

The read command is a command that requests the memory systemto read user data (read-target data) from the non-volatile memory. The read command designates, for example, a namespace identifier for identifying the namespace, a logical address (start LBA) in the namespace, the size of the read-target data (number of LBAs), and a data pointer indicating the position in the memorywhere the read-target data is to be transferred.

The CPUis a processor. The CPUperforms various processes by executing control programs (firmware) stored in the non-volatile memoryor a ROM, not shown.

The CPUserves as, for example, a flash translation layer (FTL), and performs management of data stored in the non-volatile memory, and management of blocks included in the non-volatile memory. The management of data stored in the non-volatile memoryincludes, for example, management of mapping information. The CPUmanages the mapping information using a logical/physical address conversion table (L2P table). The mapping information is information indicating mapping between the logical addresses, and the respective physical addresses of the non-volatile memory. The logical address is an address used by the hostto access the memory system. For example, a logical block address (LBA) is used as the logical address. The LBA is a logical address used to refer to data called a logical block. The size of the logical block that can be designated by the LBA is, for example, 512 bytes, 4 KiB, 8 KiB, 16 KiB or the like. The physical address is an address indicating the physical memory position in the non-volatile memory.

The CPUcreates and manages a plurality of namespaces. Each of the namespaces is a set of logical addresses. The plurality of namespaces are used to make a single memory system operate as if it were a plurality of memory systems. Each of the namespaces is used by the hostto access the memory system. The namespaces are identified respectively by namespace identifiers. The namespace identifier is an identifier used by the hostto designate a namespace to be accessed.

The management of the blocks included in the non-volatile memoryencompasses management of bad blocks included in the non-volatile memory, wear levelling, and garbage collection.

The encryption key management circuitis a circuit that manages encryption keys. The encryption key is a key used to encrypt and decrypt a write data item. The encryption key management circuitmanages one or more encryption keys, for each namespace, for example. The details of the encryption key management circuitare described later with reference to.

The ECC processing circuitexecutes an error correction coding process when data is written into the non-volatile memory. The error correction coding process is a process of adding an error-correcting code (ECC), as a redundancy code, to data to be written into the non-volatile memory. When data is read from the non-volatile memory, the ECC processing circuitexecutes an error correction decoding process. The error correction decoding process is a process of using the ECC added to the data read from the non-volatile memory, and detecting and correcting an error of the data.

The DRAM interfaceis a circuit that controls DRAM. The DRAM interfacestores data in the DRAM. The DRAM interfacereads the data stored in the DRAM.

The compression circuitis a circuit that compresses the write data item associated with the write command received from the host. The compression circuitcompresses the write data item using a lossless compression algorithm. Hereinafter, data obtained by compressing the write data item is called compressed data. Examples of the lossless compression algorithm include, for instance, dictionary encoding, entropy encoding, a combination of dictionary encoding and entropy encoding, etc.

The compressed data has a smaller size than the write data item having not been compressed yet does. The larger the size of the write data item compressed at one time by the compression circuitis, the smaller the ratio of the size of the compressed data to the size of the write data item is. That is, the larger the size of the write data item compressed at one time is, the higher the efficiency at which the compression circuitcan compress the write data item is. This is because the amount of information that can be referred to in the compression process for the write data item increases as the size of the write data item compressed at one time increases.

The size of the write data item compressed at one time by the compression circuitis called a compression unit. That is, the compression unit is a unit of compressing the write data item.

The decompression circuitis a circuit that generates uncompressed data by decompressing the compressed data.

The encryption circuitis a circuit that encrypts the compressed data. Hereinafter, data encrypted by the encryption circuitis called encrypted data. The encryption circuitencrypts compressed data output from the compression circuit, using an encryption key managed by the encryption key management circuit, thereby generating encrypted data to be written into the non-volatile memory. The generated encrypted data is subjected to the error correction coding process executed by the ECC processing circuit, and is subsequently written into the non-volatile memoryvia the non-volatile memory interface.

The decryption circuitis a circuit that decrypts the encrypted data. The decryption circuitdecrypts the encrypted data read from the non-volatile memory, using the encryption key managed by the encryption key management circuit. The encrypted data read from the non-volatile memoryis data obtained by encrypting compressed data. The encrypted data read from the non-volatile memoryis error-corrected by the ECC processing circuit, and is subsequently transferred from the ECC processing circuitto the decryption circuit. The decryption circuitgenerates decrypted compressed data by decrypting the encrypted data, and transfers the generated compressed data to the decompression circuit.

The buffer memoryis a volatile memory that temporarily holds data. Part of the memory area of the buffer memoryis used to temporarily store the write data item received from the host. Another part of the memory area of the buffer memoryis used to temporarily store data read from the non-volatile memory.

The non-volatile memory interfaceis a circuit that controls the non-volatile memory. The non-volatile memory interfaceis electrically connected to the plurality of NAND chips included in the non-volatile memory.

Each NAND chip can independently operate. Accordingly, the NAND chip functions as a unit allowing operation in parallel. The non-volatile memory interfaceis connected to channels ch, ch, . . . , and ch. The non-volatile memory interfaceis connected to one or more NAND chips via the channels ch, ch, . . . , and ch.exemplifies a case where four NAND chips are connected to each of the channels ch, ch, . . . , and ch. In this case, the non-volatile memory interfaceis connected to the NAND chips #0, #8, #16, and #24, via the channel ch. The non-volatile memory interfaceis connected to the NAND chips #1, #9, #17, and #25, via the channel ch. The non-volatile memory interfaceis then connected to the NAND chips #7, #15, #23, and #31, via the channel ch. The NAND chips #0, #1, . . . , and #7 are dealt with as a bank BNKby the controller. Likewise, the NAND chips #8, #9, . . . , and #15 are dealt with as a bank BNKby the controller. The NAND chips #16, #17, . . . , and #23 are dealt with as a bank BNKby the controller. The NAND chips #24, #25, . . . , and #31 are dealt with as a bank BNKby the controller. The bank is a unit of operating the NAND chips in parallel through interleaving operation.

In the configuration of the non-volatile memoryshown in, the controllercan write data in parallel in the NAND chips the number of which is 32 at the maximum (the number of parallel writes=32), through the eight channels and the interleaving operation among four banks. Note that each of the NAND chips #0 to #31 may have a multi-plane configuration that has a plurality of planes. For example, in a case where each of the NAND chips #0 to #31 includes two planes, the controllercan write data in parallel into the planes the number of which is 64 at the maximum (the number of parallel writes=64).

Next, a configuration of the NAND chip is described.is a block diagram showing a configuration example of each of the NAND chips included in the non-volatile memory.

The NAND chip #n is any NAND chip (n is an integer from 0 to 31) among the NAND chips #0 to #31. The NAND chip #n includes a memory cell array. The memory cell arrayincludes a plurality of blocks BLKto BLKq−1. Each of the blocks BLKto BLKq−1 includes a plurality of pages (here, pages Pto Pp−1). Each page includes a plurality of memory cells. Each of the blocks BLKto BLKq−1 is a unit of data erasing operation that erases data. Each of the pages Pto Pp−1 is unit of data writing operation and data reading operation.

is a diagram for illustrating a plurality of namespaces managed by the memory system.

shows a case where the controllermanages namespaces NS, NS, and NS. Each namespace is identified by a namespace identifier (NSID). Each namespace includes a set of consecutive logical addresses (LBAs). A logical address space corresponding to each namespace starts at LBA. Each namespace can be configured to have any size. The size of a certain namespace is represented by a value obtained by multiplying the number of LBAs included in the namespace by the data size per LBA included in the namespace. The data size per LBA is set separately for each namespace.

In, the namespace NSis a namespace identified by a namespace identifier NSID. The namespace NSincludes a plurality of LBAs consecutive from LBAto LBA(x−1).

The namespace NSis a namespace identified by a namespace identifier NSID. The namespace NSincludes a plurality of LBAs consecutive from LBAto LBA(y−1).

The namespace NSis a namespace identified by a namespace identifier NSID. The namespace NSincludes a plurality of LBAs consecutive from LBAto LBA(z−1).

Next, management of encryption keys is described.shows a configuration example of a locking table used in the memory systemaccording to the first embodiment.