Reverse recovery charge reduction circuit

This application claims priority to U.S. Provisional Application No. 63/183,286 filed on May 3, 2021, the contents of each of which are incorporated by reference herein.

Not applicable.

The present invention relates in general to power switching applications. In particular, the present invention relates to reducing or eliminating current and voltage transients and the negative effects of current and voltage transients in power switching applications.

Reverse recovery charge is a challenge in all power switching applications, for example, motor control, solenoid control, or power management. Reverse recovery charge is stored at the junction of the body diode of a switch in a power switching application when the body diode is being forward biased. This charge increases as the forward bias current increases. Ideally, when a forward biased diode is suddenly put into reverse bias there will be no current flow in the reverse bias. However, with reverse recovery charged stored, when the forward biased diode is suddenly put into the reverse bias there will be a reverse current flow which will be a function of the charge that was stored when operating in the forward bias. The current and voltage transients caused by this reverse recovery charge cause a number of problems in power switching applications.

In one embodiment, the present invention includes a method for reducing or eliminating current or voltage transients in a device comprising: providing the device, wherein the device comprises a transistor with a gate; and controlling the gate, wherein the gate is turned off to a non-zero value in a presence of a positive current flow and wherein the gate is turned on in a presence of a negative current flow; thereby reducing or eliminating current or voltage transients in the device. In one aspect, method further comprises selecting a threshold voltage of the transistor, a reverse-threshold voltage of the device, or both to optimize controlling the gate. In another aspect, the device comprises gallium nitride or gallium arsenide. In another aspect, the transistor incorporates a body diode and a backgate, and a reverse turn-on voltage of the device is less than a forward threshold voltage of the body diode; and further comprises applying a selected backgate bias voltage to the backgate to lower a reverse-threshold voltage. In another aspect, the transistor is formed in or on silicon, silicon carbide, gallium nitride, or gallium arsenide.

In another embodiment, the present invention includes a method for reducing or eliminating current or voltage transients in a switch comprising: providing the switch, wherein the switch comprises a transistor with a gate; and controlling the switch, wherein in a presence of a forward current, (1) a turn-off voltage of the switch is a bias voltage greater than zero and less than a threshold voltage of the transistor and (2) the turn-off voltage is applied to the gate to turn off the switch, preventing the forward current flow through the transistor; wherein in a presence of a reverse current, (1) a reverse turn-on voltage of the transistor is greater than a reverse-threshold voltage of the transistor and (2) a turn-on voltage is applied to the gate to turn on the switch, allowing a negative current flow through the transistor, thereby reducing or eliminating current or voltage transients. In one aspect, method further comprises selecting the threshold voltage, the reverse-threshold voltage, or both to optimize controlling the switch. In another aspect, the transistor is formed in or on gallium nitride or gallium arsenide. In another aspect, the transistor incorporates a body diode and a backgate, and the reverse turn-on voltage is less than a forward threshold voltage of the body diode; and further comprising applying a selected backgate bias voltage to the backgate to lower the reverse-threshold voltage. In another aspect, the transistor comprises silicon, silicon carbide, gallium nitride, or gallium arsenide.

In another embodiment, the present invention includes a method for reducing or eliminating current or voltage transients in a switch comprising: providing the switch, wherein the switch comprises a transistor with a gate; and controlling the switch, wherein in a presence of a forward current, (1) a turn-off voltage of the switch is a bias voltage greater than zero and less than a threshold voltage of the transistor and (2) the turn-off voltage is applied to the gate to turn off the switch, preventing the forward current flow through the transistor; wherein in a presence of a reverse current, (1) a reverse turn-on voltage of the transistor is greater than a reverse-threshold voltage of the transistor and (2) a turn-on voltage is applied to the gate to turn on the switch, allowing a negative current flow through the transistor, thereby reducing or eliminating current or voltage transients. In one aspect, the method further comprises selecting the threshold voltage, the reverse-threshold voltage, or both to optimize controlling the switch. In another aspect, the transistor is formed in or on gallium nitride or gallium arsenide. In another aspect, the transistor incorporates a body diode and a backgate, and the reverse turn-on voltage is less than a forward threshold voltage of the body diode; and further comprising applying a selected backgate bias voltage to the backgate to lower the reverse-threshold voltage. In another aspect, the transistor comprises silicon, silicon carbide, gallium nitride, or gallium arsenide.

In another embodiment, the present invention includes a switch comprising: a transistor comprising a gate; wherein in a presence of a forward current (1) a turn-off voltage of the switch is a bias voltage that is greater than zero and less than a threshold voltage of the transistor and (2) when the turn-off voltage is applied to the gate, the forward current will not flow through the transistor; and wherein in a presence of a reverse current, (1) a reverse turn-on voltage of the transistor is greater than a reverse-threshold voltage of the transistor and (2) a turn-on voltage is applied to the gate to turn on the switch, allowing a negative current flow through the transistor, thereby reducing or eliminating current or voltage transients, wherein current and voltage transients are reduced or eliminated. In one aspect, the switch further comprises selecting the threshold voltage, the reverse-threshold voltage, or both to optimize controlling the switch. In another aspect, the transistor comprises gallium nitride or gallium arsenide In another aspect, the transistor incorporates a body diode and a backgate and the reverse-threshold voltage is lowered when a selected backgate bias voltage is applied to the backgate, the reverse current will not flow through the body diode, a reverse recovery charge will not accumulate at the body diode, and the reverse turn-on voltage is less than a forward threshold voltage of the body diode. In another aspect, the transistor is formed in or on silicon, silicon carbide, gallium nitride, or gallium arsenide.

In another embodiment, the present invention includes a power converter comprising: a switch comprising: a transistor comprising a gate; wherein in a presence of a forward current (1) a turn-off voltage of the switch is a bias voltage that is greater than zero and less than a threshold voltage of the transistor and (2) when the turn-off voltage is applied to the gate, the forward current will not flow through the transistor; and wherein in a presence of a reverse current, (1) a reverse turn-on voltage of the transistor is greater than a reverse-threshold voltage of the transistor and (2) a turn-on voltage is applied to the gate to turn on the switch, allowing a negative current flow through the transistor, thereby reducing or eliminating current or voltage transients, wherein current and voltage transients are reduced or eliminated.

In another embodiment, the present invention includes a kit comprising: a switch comprising: a transistor comprising a gate; wherein in a presence of a forward current (1) a turn-off voltage of the switch is a bias voltage that is greater than zero and less than a threshold voltage of the transistor and (2) when the turn-off voltage is applied to the gate, the forward current will not flow through the transistor; and wherein in a presence of a reverse current, (1) a reverse turn-on voltage of the transistor is greater than a reverse-threshold voltage of the transistor and (2) a turn-on voltage is applied to the gate to turn on the switch, allowing a negative current flow through the transistor, thereby reducing or eliminating current or voltage transients, wherein current and voltage transients are reduced or eliminated.

Illustrative embodiments of the system of the present application are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

In the specification, reference may be made to the spatial relationships between various components and to the spatial orientation of various aspects of components as the devices are depicted in the attached drawings. However, as will be recognized by those skilled in the art after a complete reading of the present application, the devices, members, apparatuses, etc. described herein may be positioned in any desired orientation. Thus, the use of terms such as “above,” “below,” “upper,” “lower,” or other like terms to describe a spatial relationship between various components or to describe the spatial orientation of aspects of such components should be understood to describe a relative relationship between the components or a spatial orientation of aspects of such components, respectively, as the device described herein may be oriented in any desired direction.

Reverse recovery time is a challenge in all power switching applications, whether it is motor control, solenoid control, or power management. Reverse recovery charge is stored at the junction of the diode when it is being forward biased. (). The level of charge increases as the forward bias current increases. Ideally, when a forward biased diode is suddenly put into reverse bias there will be no current flow in the reverse bias. However, with reverse recovery charged stored, when the forward biased diode is suddenly put into the reverse bias there will be a reverse current flow, which will be a function of the charge that was stored when operating in the forward bias. If the transition time from forward bias to reverse bias is decreased the current peak from reverse recovery will increase. ().

shows a diodewith a threshold voltage of Vand a forward current flowng through it (as denoted by the arrow above the diode). Voltageis the behavior of a voltage across the diodeover time as the voltageis switched from a forward bias voltage Vto a reverse bias voltage V. Ideal current Iis the behavior of a current through the diodeas an ideal diode over time as the voltageis switched from the forward bias voltage Vto the reverse bias voltage V, with the ideal current Iflowing while the voltageis at Vand with the ideal current Inot flowing while the voltageis at V. Practical current Iis the behavior of a current through a realistic, practical diodeover time as the voltageis switched from the forward bias voltage Vto the reverse bias voltage V, with the practical current Iflowing while the voltageis at Vand oscillating and diminishing to zero current when the diodeis switched to the reverse bias voltage Vbecause a reverse recovery charge Qis stored at the junction of the diodewhile the practical current Iis flowing while the voltageis at the forward bias voltage Vand flows as a diminishing, oscillating transient current Ifor a short period after the switch from Vto V. As shown in, the peak of the transient practical current Iincreases as a transition time from Vto Vis decreased, with the practical current I, shown as a dashed line, having a relatively higher peak at a relatively short transition time and the practical current I, shown as a solid line, having a relatively lower peak at a relatively longer transition time.

shows a prior art power switching circuitsuch as that in a buck-switching regulator application, with a totem pole switch configuration including the high switch Mand the low switch M. The high switch Mand the low switch Mare each shown as an exemplary metal-oxide semiconducting field-effect transistor (MOSFET) with a body diode, the parasitic diode that is intrinsic to the MOSFETs of the high switch Mand of the low switch Mas shown in. More particularly, the power switching curcuitincludes the input for input power supply voltage V, the high switch M, the input for the high gate voltage V, the forward current I, the low switch M, the voltage source Vfor the low gate voltage V,, the reverse current I, the load inductor L, the load capacitor C, and the output for the output voltage V.

In the representative prior art power switching circuit, to improve efficiency, the low switch Mis on the ON state when the current Iis freewheeling through the load inductor Land the load capacitor C. When the output voltage Vdecreases, more energy must be provided from the inpur power supply by inputting the input power supply voltage V, by switching the high switch Mto the ON state. To prevent a shoot-through current from the high switch Mto the low switch M, the low switch Mmust be switched to the OFF state before the high switch Mlis switched to the ON state. The time period during which both the high switch Mand the low switch Mare in the OFF state is the deadtime. To switch the low switch Mto the OFF state, the voltage source Vis transitioned to 0 volts. During the deadtime that starts when the low switch Mis switched to the OFF state, a reverse recovery charge Qaccumulates at the forward bias junction of the body diode of the low switch M. When the high switch Mis switched to the ON state, ending the deadtime, the reverse recovery charge Qand the forward current Iflow through the high switch M. To minimize the peak and the dI/dt of the reverese recovery charge Qthat was accumulated in the body diode of the low switch M, the transition time from the OFF state to the ON state can be increased as shown for the practical current Iin, but at the cost of increased switching losses and a reduction in power efficiency.

shows the behavior over time of the low gate voltage V, shown as the low gate voltage Vcurve; the high gate voltage V, shown as the high gate voltage Vcurve; and the current Iand the current I, shown together as the current curve. The current Iflows as the low gate voltage is set to 0 V, beginning the deadtime. When the high gate voltage Vis set to switch the high switch Mto the ON state, the deadtime ends and the reverse recovery charge flows as the transient portionof the current curve.

shows the representative prior art power switching circuitwith the high switch M, the low switch M, the current I, the current I, the parasitic inductance L, the parasitic inductance L, the parasitic inductance L, and the output switch pin voltage Vbetween the parasitic inductance Land the parasitic inductance L. The product of (1) the sum Lof the parasitic inductances L, L, and Land (2) the dI/dt of the reverese recovery charge Qthat was accumulated in the body diode of the low switch Mtranslates to a parasitic inductance voltage transient. The high switch Mmust be able to withstand the peak of this parasitc inductance voltage transient, but as the breakdown voltage of the high switch Mis increased, the overall product of (1) the drain-to-source resistance Rof the high switch Min the ON state and (2) the area of the high switch Mincreases, and to keep efficiency lower, the size of the high switch Mmust be increased. These considerations require trade-offs to be made in the types and sizes of the high switch Mand the low switch M, management of board layout to minimize parasitics, and switching characteristics of the output of the representative prior art power switching circuit.

shows the behavior over time of the current I, shown as the current Icurve, and the drain-to source voltage of the high switch MV, shown as the voltage Vcurve. When the high switch Mis switched to the ON state, the deadtime ends, the reverse recovery charge Qflows as the transient portionof the current Icurve, and the drain-to source voltage of the high switch MVincreases, including the parasitic inductance voltage transient peak.

The solution to this problem is to eliminate or reduce the reverse recovery charge that can be stored. The elimination of reduction of the reverse recovery charge is achieved by gate controlling the turn-off voltage level of device M. As shown in, the gate of device Mis turned-off with a Vbias level. The Vbias is set to a voltage lower than the threshold voltage (Vt) of M. Therefore, if a positive voltage were placed at the drain, no current, Ix, will flow through Mfrom drain to source.

shows an embodiment of the present invention, the low switch Mof a power switching application. The low switch Mincludes a MOSFET with a body diode. The voltage source for the bias voltage Vis also shown and is connected to the input for the low switch gate voltage V. The current Iis also shown. The low switch Mpresents a solution to problems associated with the reverse recovery charge Qby gate controlling the turn-off voltage level of the low switch M. The gate of the low switch Mis switched to the OFF state with a bias voltage Vby setting the bias voltage Vto a voltage lower than the forward threshold voltage Vof the low switch M. If a positive voltage is placed at the drain of the low switch M, the current Iwill be zero, i.e., no current Iwill flow from the drain to the source of the low switch M.

shows the low switch M, with the voltage source for the bias voltage V, the gate-to-source voltage Vfor the low switch M, the reverse source voltage S, and the reverse drain voltage D, and the current I.also shows connected to the load inductor L, the load capacitor C, and the output for the output voltage V. In the recirculation mode of a power switching device of which the low switch Mis a component, the current Iwill flow as shown, and in the low switch M, the source and the drain reverse to become the reverse drain and the reverse source, respectively. The reverse drain voltage Dis shown grounded at 0 volts. The reverse threshold voltage of the low switch MVwill be less than the forward threshold voltage Vbecause the backgate biasing, i.e., the bias voltage applied to the body diode, for the forward and reverse modes of the low switch Mare at different voltages with respect to the source voltage in the forward mode and the reverse source voltage Sfor the reverse mode. With the reverse drain voltage Dgrounded at 0 volts, the reverse source voltage Swill be a negative voltage. To eliminate the accumulation of the reverse recovery charge Qas described herein, the reverse-drain-to-reverse-source voltage should not be greater than the forward bias voltage of the body diode. The forward bias voltage of the body diode may typically be +0.6 V. To assure that the body diode is not forward biased, the gate-to-source voltage Vminus the reverse threshold voltage Vmust be large enough to switch the low switch Mto the reverse-biased-ON state.shows a representative value for the reverse source voltage S=−0.6 V and for the grounded reverse drain voltage D=0 V when the forward bias voltage of the body diode is a typical +0.6 V. Thus, the reverse-drain-to-reverse-source voltage D−S=0 V−(−0.6 V)=+0.6 V. When the overall gate-to-reverse-source voltage V−S=V−(−0.6 V)=V+0.6 V is greater than the reverse threshold voltage V, the low switch Mis switched to the reverse-bias-ON state and the accumulation of of the reverse recovery charge is eliminated.

shows that the gate-to-source voltage Vcreates a resistance drive Rfor the low switch Min the reverse-bias-ON state. The product of (1) the resistance Rand (2) the current Imust be less than the forward bias voltage Vof the body diode of the low switch Mto eliminate the accumulation of the reverse recovery charge Q. However, even if the body diode does forward bias, only a fractional portion of the current Iwill be contributed to the reverse recovery charge Q, reducing the reverse recovery charge Qfor the low switch Mas compared to the accumulation of the reverse recovery charge Qfor a low switch Min which the turn-off voltage level is not gate controlled, such as the low switch Mof the representative prior art power switching circuit.

There are several ways that this technique can be implemented into a design.show a Driver Stage Mand Min series with diode Dwhich sets the Vbias voltage. In addition, a parallel clamping device, Mcan be placed to pull the gate to source voltage to zero when the drain voltage begins to rise. This also helps to mitigate the Mdevice from turning back on when the miller capacitance (Cm) from the drain to gate injects charge onto the gate during this voltage transient on the drain.

shows an embodiment of the present invention, the power switching curcuit, including the low switch M. In the power switching circuit, a driver stagethat includes the input for the driver stage input voltage V, the driver switch M, the driver switch M, and the driver diode D, and the driver diode voltage Vat the connection of the driver switch Mand driver diode D. The driver stageis used to set the bias voltage Vfor the low switch gate voltage V.

In the embodiment shown in, the parallel clamping device Mis shown. The parallel clamping device Mis used to pull the gate-to-source voltage Vto 0 V when the drain voltage of the low switch Mbegins to rise. This action helps to prevent the low switch Mfrom switching to the ON state when the parasitic capacitance known as the Miller capacitance Cfrom the drain to the gate of the low switch Minjects charge onto the gate of the low switch Mduring the rise of the voltage at the drain. The parallel clamping device Mmay be controlled from the driver stageby a delay circuit.

shows the behavior over time of the low switch gate voltage Vas the voltage curveand of the high switch gate voltage Vas the voltage curvefor the embodiment shown in. The low switch gate voltage Vbegins as the driver stage input voltage V, and then the low switch gate voltage Vis changed to the driver diode voltage V. After a time delay Δt introduced by the delay circuit, the low switch gate voltage Vis changed to 0 V. During the time delay delay Δt, the high switch gate voltage VgHis changed to switch the high switch M(not shown in) to the ON state. The parallel clamping device Mmay also be controlled by a combination of the driver stageand feedback monitoring of the drain voltage of the low switch M.

show a latter technique which provides immediate feedback when the drain voltage of Mbegins to rise, which prevents inadvertent turn-off of Mfrom the Cm capacitor.shows an embodiment in which the logic gatecontrols the gate of the parallel clamping device M, where the logic gateuses as input (1) the voltage at the gates of the driver switches Mand Mand (2) the output of the device. When the drain voltage of the low switch M, V, begins to rise, the parallel clamping device Mis switched to the ON state, and the low switch Mis prevented from switching to the ON state when the Miller capacitance Cminjects charge onto the gate of the low switch M.also shows the driver stage input voltage V, the high switch, the input for the high switch gate voltage V, and the high switch drain voltage V.

shows the behavior over time of the low switch gate voltage Vas the voltage curve, of the drain voltage of the low switch M, V, as voltage curve, and of the high switch gate voltage Vas voltage curve. The low switch gate voltage Vbegins at the driver stage input voltage V, then is changed to the driver diode voltage V. The drain voltage of the low switch M, V, begins at a voltage between 0 V and the representative voltage of −0.6 V and is changed to the representative voltage of −0.6 V when the low switch gate voltage Vis changed to the driver diode voltage V. Then the high switch gate voltage Vis changed to switch the high switchto the ON state and as the high switch gate voltage Vrises, drain voltage of the low switch M, V, rises. When drain voltage of the low switch M, V, reaches 0 V, and the parallel clamping device Mis switched to the ON state. Thus, the low switch Mis prevented from switching to the ON state when the Miller capacitance Cinjects charge onto the gate of the low switch M.

Additionally, for the embodiments shown in, other techniques can be used where the bias voltage Vfor the low switch gate voltage Vis a dynamically adjusted value that is compensated by feedback from a current sense amplifier from the low switch M. This allows for greatest gate-to-reverse-sourcevoltage drive in the reverse direction.

In addition, a feedback loop can be achieved from a tap-off FET from the low switch Mwhere a low-current diode voltage is monitored and the bias voltage Vfor the low switch gate voltage Vcan be adjusted. In addition, improvements can be made to the technique of optimizing the threshold voltage Vof the low switch M. By making the threshold voltage Vof the low switch M, the low switch Mcan have more drive strength per unit area in the reverse-bias mode.

shows an embodiment of the present invention in which a wide-bandgap low switch, such as a low switch that includes gallium nitride (Ga N), is used in a power switching circuit, such as a low switch that includes gallium nitride (Ga N).shows a wide-bandgap low switch with a low switch gate voltage V, a low switch drain voltage V, and a low switch source voltage V, and a high switchwith a high sswitch drain voltage Vand a high switch gate voltage V. Also shown is a loadincluding the load inductor Land the load capacitor C. During operation, when current flows from the low switch sourceto the low switch drainat the time during make-before-break, the gate-to-source voltage Vis placed at a mid-level voltage V. By using this embodiment, the drain-to-source voltage Vmaximum negative voltage can be minimized. Use of this embodiment aids in the reduction of noise generated.

compares the behaviors over time of voltages in a power switching circuit including the wide-bandgap low switch of(part “A” of) and in a prior art power switching circuit (part “B” of). Because the maximum drain-to-sorce voltage of the prior switch of part “B” is greater than the maximum drain-to-source voltage of the wide-bandgap switch of, the power loss in the prior art switch of part “B” is greater than power loss of the wide-bandgap switch of, an improvement over the prior art.

shows that the typical silicon or silicon carbide switch is actually a four-terminal device. In the switch, having the gate G, the drain D, the source S, and the backgate BG, the backgateis tied to the source S. The switchis equivalent to the switch, having the gate G, the drain D, the source S, and the body diode.

shows an embodiment of the present invention, a four-terminal switchincluding silicon or silicon carbide and having the gate G, the source S, the drain D, the backgate BG, a voltage source for the gate bias voltage V, and a voltage source for the backgate bias voltage V. Both the gate bias voltage Vand the backgate bias voltage Vcan be adjusted to further reduce the ON-state resistance of the switchwhen current flows from the source Sto the drain Dwhen the switch is in the reverse-bias mode. To achieve this, the gate-to-source voltage can be placed at a mid-level voltage and the backgte bias voltage Vcan also be placed at a mid-level voltage, which reduces the threshold voltage, increasing the drive and reducing the current of the switchwith the current flowing from the source Sto the drain Dwhen the switch is in the reverse-bias mode. Any combination of the gate bias voltage Vand the backgate bias voltage Vcan be used.

shows the behavior over time of the gate bias voltage V, shown as voltge curve, and the backgate bias voltage V, shown as voltage curve, for the switchwhen the gate bias voltage Vand the backgate bias voltage Vare changed at the same times.

shows the behavior over time of the gate bias voltage V, shown as voltage curve, and the backgate bias voltage V, shown as voltage curve, for the switch. This is another timing embodiment of, in which the backgate bias voltage Vis activated to a voltage backgate bias voltage Vprior to gate bias voltage Vtransitioning from a high state to a mid state. Additionally, the backgate bias voltage Vtransitions from a mid state to a low state after gate bias voltage Vtransitions from a mid state to a low state. By controlling the voltage of gate bias voltage Vand backgate bias voltage Vin this condition provides a stable shift in threshold voltage for the gate bias voltage Vwhen it transitions from a high state to a mid state and from mid state to low state, including zero (0V). It is also possible to maintain backgate bias voltage Vin a non-zero state, thus it does not have to dynamically switch.

The approach taught herein can also be used with Silicon Carbide applications (SiC), Gallium Nitride, or Gallium Arsenide. Any combination of bias voltage and threshold voltage can be set either positive or negative in value that meets the requirements of off-state in the forward direction and on-state in the negative direction.

The approach taught herein can also be used in any combination of configurations, such as high-side drive, low-side drive, high- and low-side, or one or more FETs in any combination.

The approach taught herein can also be used in any combination of current or voltage switching or current and voltage switching, such as power regulation, one or more switches for line termination, DC motor drivers, induction motor drivers, transducer drivers, solid-state fuse switches, battery management, AC-to-DC power conversion, DC-to-AC power conversion, or power correction.

Any combination of bias voltage and threshold voltage can be set either positive or negative in value that meets the requirements of off-state in the forward direction and on-state in the negative direction.

Any combination of transitions from on voltage to bias voltage that meets the requirements of on- to off-state in the forward direction and on-state in the negative direction is included in the present invention. The transitions can also be either step functions, linear graded, or non-linear graded transitions.

It will be understood that particular embodiments described herein are shown by way of illustration and not as limitations of the invention. The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.

All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”) or “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In embodiments of any of the compositions and methods provided herein, “comprising” may be replaced with “consisting essentially of” or “consisting of.” As used herein, the phrase “consisting essentially of” requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step, or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process(s) steps, or limitation(s)) only.

The term “or combinations thereof” as used herein refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof” is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.

As used herein, words of approximation such as, without limitation, “about,” “substantial” or “substantially” refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skill in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as “about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

All of the devices and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the devices and/or methods of this invention have been described in terms of particular embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the invention as defined by the appended claims.

Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosure. Accordingly, the protection sought herein is as set forth in the claims below.