A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
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Complete technical specification and implementation details from the patent document.
This application claims the benefit of priority to Japanese Patent Application No. 2022-103295 filed on Jun. 28, 2022. The entire contents of the application are hereby incorporated herein by reference.
The present invention relates to a rectifier.
US2007-0145474 discloses a drain/source common field effect transistor. US2011-0216566 discloses a MOS transistor having a source or a drain that is diode-connected to a gate.
An embodiment provides a rectifier including a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
An embodiment provides a rectifier including a transistor of a drain/source common field effect type of a p-channel, the transistor having a gate fixed at a zero potential, a first drain source that functions as an anode of a rectifier stage, a second drain source that functions as a cathode of the rectifier stage, and a back gate electrically connected to the first drain source.
An embodiment provides a rectifier including a transistor of a drain/source common field effect type of an n-channel, the transistor having a gate, a first drain source that is electrically connected to the gate and that functions as an anode of a rectifier stage, a second drain source that functions as a cathode of the rectifier stage, and a back gate fixed at a zero potential.
The aforementioned or other objects, features, and effects will be clarified by the following description of embodiments given below with reference to the accompanying drawings.
An embodiment provides a rectifier having a novel configuration.
An embodiment provides a rectifier including a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
An embodiment provides a rectifier including a transistor of a drain/source common field effect type of a p-channel, the transistor having a gate fixed at a zero potential, a first drain source that functions as an anode of a rectifier stage, a second drain source that functions as a cathode of the rectifier stage, and a back gate electrically connected to the first drain source.
An embodiment provides a rectifier including a transistor of a drain/source common field effect type of an n-channel, the transistor having a gate, a first drain source that is electrically connected to the gate and that functions as an anode of a rectifier stage, a second drain source that functions as a cathode of the rectifier stage, and a back gate fixed at a zero potential.
An embodiment will be hereinafter described in detail with reference to the accompanying drawings. The accompanying drawing is a schematic view, and is not a precisely-depicted view, and its reduced scale or the like does not necessarily coincide with those of the other accompanying drawings. Additionally, the same reference sign is assigned to a mutually-equivalent constituent among the accompanying drawings, and a duplicative description of this constituent is omitted or simplified. A description given before being omitted or simplified is applied to the configuration a description of which has been omitted or simplified.
When the phrase “substantially equal” or the like is used in this description, this phrase includes a numerical value (form) equal to a numerical value (form) of a comparable object, and, in addition, includes a numerical error (form error) within the range of ±10% based on the numerical value of the comparable object (form). The term “first,” “second,” “third” or the like is used in the embodiment, and each of these terms is a symbol given to the name of each constituent for clarifying the descriptive order, and is not given with the aim of limiting the name of each constituent.
The term “rectifier” according to this description is a concept including a rectifier circuit, a rectifier instrument, a rectifier module, etc., and may be referred to as a “rectifier circuit,” a “semiconductor rectifier circuit,” a “semiconductor rectifier,” a “semiconductor rectifier instrument,” a “semiconductor device,” a “semiconductor module,” or the like if necessary.
is a circuit diagram showing an electrical configuration of a rectifier LA according to a first embodiment.is a circuit diagram showing a concrete electrical configuration of the rectifier LA shown in. Referring to, the rectifier LA includes a rectifier stage R, an anode end A, and a cathode end K. The rectifier stage R may be referred to as a “rectifier portion,” a “diode stage,” or a “diode portion.” The rectifier stage R has an anode and a cathode. The anode end A is an application end of an anode potential, and is electrically connected to the anode of the rectifier stage R. The cathode end K is an application end of a cathode potential, and is electrically connected to the cathode of the rectifier stage R.
Referring to, the rectifier stage R includes a first transistor Trof a drain/source common field effect type and a second transistor Trof the drain/source common field effect type. In this embodiment, the first transistor Tris a p-channel type, and the second transistor Tris an n-channel type. Hereinafter, a fundamental configuration of each of the first and second transistors Trand Trwill be first described, and then a configuration of the rectifier stage R will be described.
The first transistor Trmay be an Si transistor formed in an Si (silicon) monocrystal, or may be a wide bandgap semiconductor transistor formed in a monocrystal of a wide bandgap semiconductor. The wide bandgap semiconductor is a semiconductor having a bandgap larger than the bandgap of Si. The first transistor Trmay be an SiC transistor formed in an SiC (silicon carbide) monocrystal as an example of the wide bandgap semiconductor.
The first transistor Trhas a first gate G, a first drain source DS, a second drain source DS, a first back gate BG, and a first diode pair DP. Each of the first drain source DSand the second drain source DSintegrally includes a source and a drain.
The first gate Ghas a first gate threshold voltage Vgth. The first gate threshold voltage Vgthmay exceed 0 V and not more than 1.0 V. The first gate threshold voltage Vgthmay have a value that belongs to any one of the ranges of beyond 0 V and not more than 0.1 V, not less than 0.1 V and not more than 0.2 V, not less than 0.2 V and not more than 0.3 V, not less than 0.3 V and not more than V, not less than 0.4 V and not more than 0.5 V, not less than 0.5 V and not more than 0.6 V, not less than 0.6 V and not more than 0.7 V, not less than 0.7 V and not more than V, not less than 0.8 V and not more than 0.9 V, and not less than 0.9 V and not more than 1.0 V. Preferably, the first gate threshold voltage Vgthis 0.5 V or less.
The first diode pair DPincludes a first body diode Dand a second body diode Dthat are reverse bias connected so as to be a cathode common, and is electrically connected to the first drain source DSand to the second drain source DS. The first body diode Dis a pn junction diode, and the second body diode Dis a pn junction diode.
The first body diode Dincludes an anode that is electrically connected to the first drain source DSand a cathode that forms a node with respect to the second body diode D. The second body diode Dincludes an anode that is electrically connected to the second drain source DSand a cathode that is electrically connected to the cathode of the first body diode D.
The first diode pair DPhas a first breakdown voltage VB. The first breakdown voltage VBis limited to the breakdown voltage of either the first body diode Dor the second body diode Dby means of a voltage application direction with respect to the first diode pair DP.
The first breakdown voltage VBmay be not less than 5 V and not more than 3000 V. The first breakdown voltage VBmay have a value that belongs to any one of the ranges of not less than 5 V and not more than 50 V, not less than 50 V and not more than 100 V, not less than 100 V and not more than 250 V, not less than 250 V and not more than 500 V, not less than 500 V and not more than 750 V, not less than 750 V and not more than 1000 V, not less than 1000 V and not more than 1250 V, not less than 1250 V and not more than 1500 V, not less than 1500 V and not more than 1750 V, not less than 1750 V and not more than 2000 V, not less than 2000 V and not more than 2250 V, not less than 2250 V and not more than 2500 V, not less than 2500 V and not more than 2750 V, and not less than 2750 V and not more than 3000 V.
When a voltage equal to or more than the first gate threshold voltage Vgthis applied to the first gate Gand when a predetermined drain-source voltage is applied between the first drain source DSand the second drain source DS, a drain-source current flows between the first drain source DSand the second drain source DSthrough a first channel CHof the first transistor Tr. The direction of the drain-source current is to be reversed by the positive/negative of the drain-source voltage. In other words, the first transistor Tris a bidirectional device that is capable of passing a drain-source current in both directions of the first drain source DSand the second drain source DS.
When a voltage less than the first gate threshold voltage Vgthis applied to the first gate Gand when a drain-source voltage equal to or more than the first breakdown voltage VBis applied between the first drain source DSand the second drain source DS, a breakdown current flows between the first drain source DSand the second drain source DSthrough the first diode pair DP.
The characteristic (inclination) of the drain-source current is adjusted by a first on-resistance Ronof the first transistor Tr. The first transistor Trmay have the first on-resistance Ronof, for example, not less than 50 mΩ and not more than 200 mΩ per unit area (1 square millimeter).
The first on-resistance Ronmay have a value that belongs to any one of the ranges of not less than 50 mΩ and not more than 75 mS), not less than 75 mΩ and not more than 100 mΩ, not less than 100 mΩ and not more than 125 mS), not less than 125 mΩ and not more than 150 mS), not less than 150 mΩ and not more than 175 mS), and not less than 175 mS) and not more than 200 mc). Preferably, the first on-resistance Ronis 150 mΩ or less.
The second transistor Trmay be an Si transistor formed in an Si monocrystal, or may be a wide bandgap semiconductor transistor formed in a monocrystal of a wide bandgap semiconductor. The second transistor Trmay be an SiC transistor formed in an SiC monocrystal as an example of the wide bandgap semiconductor.
The second transistor Trhas a second gate G, a third drain source DS, a fourth drain source DS, a second back gate BG, and a second diode pair DP. Each of the third drain source DSand the fourth drain source DSintegrally includes a source and a drain.
The second gate Ghas a second gate threshold voltage Vgth. The second gate threshold voltage Vgthmay be substantially equal to the first gate threshold voltage Vgth, or may be less than the first gate threshold voltage Vgth, or may be larger than the first gate threshold voltage Vgth. Preferably, the second gate threshold voltage Vgthis equal to or more than the first gate threshold voltage Vgth. The second gate threshold voltage Vgthis less than the first breakdown voltage VBof the first diode pair DP.
The second gate threshold voltage Vgthmay exceed 0 V and not more than 1.0 V. The second gate threshold voltage Vgthmay have a value that belongs to any one of the ranges of beyond 0 V and not more than 0.1 V, not less than 0.1 V and not more than 0.2 V, not less than 0.2 V and not more than 0.3 V, not less than 0.3 V and not more than 0.4 V, not less than 0.4 V and not more than 0.5 V, not less than 0.5 V and not more than 0.6 V, not less than 0.6 V and not more than 0.7 V, not less than 0.7 V and not more than 0.8 V, not less than 0.8 V and not more than 0.9 V, and not less than 0.9 V and not more than 1.0 V. Preferably, the second gate threshold voltage Vgthis equal to or less than 0.5 V.
The second diode pair DPincludes a third body diode Dand a fourth body diode Dthat are reverse bias connected so as to be an anode common, and is electrically connected to the third drain source DSand to the fourth body diode D. The third body diode Dis a pn junction diode, and the fourth body diode Dis a pn junction diode.
The third body diode Dincludes an anode that forms a node with respect to the fourth body diode Dand a cathode that is electrically connected to the third drain source DS. The fourth body diode Dincludes an anode that is electrically connected to the anode of the third body diode Dand a cathode that is electrically connected to the fourth drain source DS.
The second diode pair DPhas a second breakdown voltage VB. The second breakdown voltage VBis limited to the breakdown voltage of either the third body diode Dor the fourth body diode Dby means of a voltage application direction with respect to the second diode pair DP. The second breakdown voltage VBmay be substantially equal to the first breakdown voltage VB, or may be less than the first breakdown voltage VB, or may be larger than the first breakdown voltage VB.
The second breakdown voltage VBmay be not less than 5 V and not more than 2000 V. The second breakdown voltage VBmay have a value that belongs to any one of the ranges of not less than 5 V and not more than 50 V, not less than 50 V and not more than 100 V, not less than 100 V and not more than 250 V, not less than 250 V and not more than 500 V, not less than 500 V and not more than 750 V, not less than 750 V and not more than 1000 V, not less than 1000 V and not more than 1250 V, not less than 1250 V and not more than 1500 V, not less than 1500 V and not more than 1750 V, not less than 1750 V and not more than 2000 V, not less than 2000 V and not more than 2250 V, not less than 2250 V and not more than 2500 V, not less than 2500 V and not more than 2750 V, and not less than 2750 V and not more than 3000 V.
When a voltage equal to or more than the second gate threshold voltage Vgthis applied to the second gate Gand when a predetermined drain-source voltage is applied between the third drain source DSand the fourth drain source DS, a drain-source current flows between the third drain source DSand the fourth drain source DSthrough a second channel CHof the second transistor Tr. The direction of the drain-source current is to be reversed by the positive/negative of the drain-source voltage. In other words, the second transistor Tris a bidirectional device that is capable of passing a drain-source current in both directions of the third drain source DSand the fourth drain source DS.
When a voltage less than the second gate threshold voltage Vgthis applied to the second gate Gand when a drain-source voltage equal to or more than the second breakdown voltage VBis applied between the third drain source DSand the fourth drain source DS, a breakdown current flows between the third drain source DSand the fourth drain source DSthrough the second diode pair DP.
The characteristic (inclination) of the drain-source current is adjusted by a second on-resistance Ronof the second transistor Tr. The second transistor Trmay have the second on-resistance Ronof, for example, not less than 50 mΩ and not more than 200 mΩ per unit area (1 square millimeter).
The second on-resistance Ronmay have a value that belongs to any one of the ranges of not less than 50 mΩ and not more than 75 mS), not less than 75 mΩ and not more than 100 mΩ, not less than 100 mΩ and not more than 125 mS), not less than 125 mΩ and not more than 150 mS), not less than 150 mΩ and not more than 175 mS), and not less than 175 mS) and not more than 200 mc). Preferably, the second on-resistance Ronis 150 mΩ or less.
The rectifier stage R is configured by allowing the second transistor Trto be diode-connected to the first transistor Trso that the first transistor Trperforms a diode operation. In detail, the second transistor Tris provided as a bias circuit that enables the first transistor Trto perform a diode operation by means of a bias voltage, hence configuring the rectifier stage R together with the first transistor Tr.
In more detail, the second gate Gis electrically connected to the second drain source DS, the third drain source DSis electrically connected to the first drain source DSand to the first back gate BG, the fourth drain source DSis electrically connected to the first gate G, and the second back gate BGis electrically connected to the first drain source DSand to the first back gate BG.
In other words, the first back gate BGis electrically connected to the first drain source DSon the first transistor Trside, and the second back gate BGis electrically connected to the third drain source DSon the second transistor Trside. Hence, the first drain source DS, the first back gate BG, the third drain source DS, and the second back gate BGare fixed at the same potential. Also, the first gate Gand the fourth drain source DSare fixed at the same potential. Also, the second drain source DSand the second gate Gare fixed at the same potential.
The fourth drain source DSconfigures a short circuit with the first gate G, and does not form a voltage drop between the first gate Gand the fourth drain source DS. In other words, the first gate Gand the fourth drain source DSare fixed at a zero potential (same potential). The first gate Gand the fourth drain source DSare fixed at a zero potential both at ON and at OFF of the rectifier stage R (the first transistor Tr).
The first drain source DSis electrically connected to the anode end A, and the second drain source DSis electrically connected to the cathode end K. In this description and in the accompanying drawings, the anode end A and the first drain source DSare represented separately from each other, and the cathode end K and the second drain source DSare represented separately from each other. However, the anode end A may be regarded as being configured by the first drain source DS, and the cathode end K may be regarded as being configured by the second drain source DS.
is a circuit diagram showing a forward operation of the rectifier LA shown in.is a circuit diagram showing a reverse operation of the rectifier LA shown in. Referring toand, a forward current IF flows to the first transistor Trin the forward operation, and a reverse current IR flows to the first transistor Trin the reverse operation.
In detail, in the forward operation, a forward potential VF based on the second drain source DSis applied to the first drain source DS, and the forward current IF flows from the first drain source DStoward the second drain source DSwith reference to. In, a circuit operation is shown when a reference potential Vref (for example, ground potential) is applied to the second drain source DSand when the forward potential VF is applied to the first drain source DS. A forward voltage will be hereinafter referred to at times as the “forward voltage VF.”
In the forward operation, the first drain source DS, the first back gate BG, the third drain source DS, and the second back gate BGare fixed at the forward potential VF. The second drain source DSand the second gate Gare fixed at the reference potential Vref. The first gate Gand the fourth drain source DSare fixed at a zero potential without forming a voltage drop.
In the first transistor Tr, the first gate Gis fixed at a zero potential, and the first back gate BGis fixed at the forward potential VF. Therefore, the first transistor Trreaches an OFF state when the forward voltage VF is less than the first gate threshold voltage Vgthof the first gate G, and the first transistor Trreaches an ON state when the forward voltage VF is equal to or more than the first gate threshold voltage Vgth. When the first transistor Trreaches an ON state, the forward current IF flows from the first drain source DStoward the second drain source DSthrough the first channel CHof the first transistor Tr.
In the second transistor Tr, the second gate Gis fixed at the reference potential Vref, and the second back gate BGis fixed at the forward potential VF. Therefore, the second transistor Trreaches an OFF state. The second transistor Trdoes not form a current path between the first drain source DSand the second drain source DS, and therefore the forward current IF does not flow through the second transistor Tr.
Thus, in the forward operation, the first transistor Tris controlled to be an ON state, and the second transistor Tris controlled to be an OFF state by means of a bias effect caused by the second transistor Tr. In this state, the forward current IF flows between the first drain source DSand the second drain source DSthrough the first channel CHof the first transistor Tr.
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April 14, 2026
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