Metal capping layer for reducing gate resistance in semiconductor devices

This Non-Provisional application claims priority to U.S. Provisional Application Ser. No. 63/219,914, filed Jul. 9, 2021, and titled “Metal Capping Layer for Reducing Gate Resistance in Semiconductor Devices,” the entire disclosure of which is incorporated herein by reference.

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing, and for these advancements to be realized, similar developments in IC processing and manufacturing are needed.

Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, there are challenges associated with forming low-resistance metal gate structures at reduced length scales, such as in nanosheet field-effective transistors (NS FETs; also referred to as gate-all-around, or GAA, FETs). For at least this reason, improvements in this area are desired.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one feature's relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as three-dimensional fin-like FETs (FinFETs), nanosheet (NS; also referred to as gate-all-around, or GAA) FETs, in memory and/or standard logic cells of an IC structure. Generally, an NS FET includes a plurality of vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) in a channel region of the FET. The present disclosure includes multiple embodiments. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

Advancement in fabrication of semiconductor devices has introduced many challenges. In one such example, the scaling down of various device features reduces volume available for gap-filling during the formation of a metal gate structure (or metal gate stack), which may result in higher gate resistance (R). While methods of reducing gate resistance in NS FETs and FinFETs have been generally adequate, they have not been entirely satisfactory in all aspects.

Referring tocollectively, flowcharts of methodsandof forming a semiconductor structure (hereafter simply referred to as the structure)is illustrated according to various aspects of the present disclosure. Methodsandare merely examples and are not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after methodand/or method, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the methodand/or.

The structuremay be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random-access memory (SRAM) and/or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as NS FETs, FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other transistors. In the present embodiments, the structureincludes one or more NS FETs. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations. Additional features can be added to the structure, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the structure.

At operation, referring to, methodforms the structurethat includes multiple active three-dimensional device regionsand(hereafter referred to as finsand) protruding from a semiconductor substrate(hereafter referred to as the substrate). The structuremay include additional fins protruding from the substrateand parallel to the finsand

The substratemay include an elemental (single element) semiconductor, such as silicon (Si), germanium (Ge), and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substratemay be a single-layer material having a uniform composition. Alternatively, the substratemay include multiple material layers having similar or different compositions suitable for IC device manufacturing.

In some embodiments, referring to, each of the finsandincludes a multi-layer structure (ML) of alternating non-channel layers (or sacrificial layers)and channel layersstacked vertically over protruding portions of the substrate, as well as a hard mask layerover the ML. In the present embodiments, the non-channel layersare sacrificial layers configured to be removed at a subsequent processing step, thereby providing openings between the channel layersfor forming a metal gate stack therein. Each channel layermay include a semiconductor material such as, for example, Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while each non-channel layerhas a composition different from that of the channel layer. In one such example, the channel layermay include elemental Si and the non-channel layermay include SiGe. In another example, the channel layermay include elemental Si and the non-channel layermay include elemental Ge. In some examples, each of the finsandmay include a total of three to ten pairs of alternating non-channel layersand channel layers. Other configurations may also be applicable depending upon specific design requirements.

In the present embodiments, the hard mask layeris a sacrificial layer configured to facilitate the formation of a gate isolation feature (discussed in detail below) and subsequently be removed from the structure. As such, a thickness of the hard mask layermay be adjusted based on the desired thickness of the gate isolation feature. In some embodiments, the thickness of the hard mask layeris greater than a thickness of the non-channel layersand the channel layers. The hard mask layermay include any suitable material, such as a semiconductor material, so long as its composition is different from that of the subsequently-formed gate isolation feature and the channel layerdisposed thereunder to allow selective removal by an etching process. In some embodiments, the hard mask layerhas a composition similar to or the same as that of the non-channel layersand includes, for example, SiGe.

In the present embodiments, forming the ML includes alternatingly growing the non-channel layersand the channel layersin a series of epitaxy processes. The epitaxy processes may be implemented by chemical vapor deposition (CVD) techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure (LP-CVD), and/or plasma-enhanced CVD (PE-CVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxy process may use gaseous and/or liquid precursors containing a suitable material (e.g., Ge for the non-channel layers), which interact with the composition of the underlying substrate, e.g., the substrate. In some examples, the non-channel layersand the channel layersmay be formed into nanosheets, nanowires, or nanorods. A sheet (or wire) release process may then be implemented to remove the non-channel layersto form openings between the channel layers, and a metal gate stack is subsequently formed in the openings, thereby providing an NS FET. For embodiments in which the hard mask layerhas the same composition as the non-channel layers, the hard mask layermay also be formed by a similar epitaxy process as discussed herein.

In some embodiments, as depicted in, each of the finsandincludes a single semiconductor layer, i.e., having a uniform composition along a height of the fin, that protrudes from the substrate. The present disclosure is not limited by the configuration of the finsand. For embodiments in which the ML is employed, subsequent operationis applied to the finsandbefore forming a dummy gate structure at operation. For embodiments in which the finsandeach include a uniform composition, operationmay be omitted and the dummy gate structure may be formed over the finsandfollowing operation.

In the present embodiments, the finsandare fabricated from the ML (and the hard mask layerdisposed thereover) and/or the substrateusing a series of photolithography and etching processes. For example, the photolithography process may include forming a photoresist layer overlying the structure, exposing the photoresist layer to a pattern, performing post-exposure bake processes, and developing the exposed photoresist layer to form a patterned masking element (not depicted). The ML and/or the substrateare then etched using the patterned masking element as an etch mask, thereby leaving the finsandprotruding from the substrate. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof. The patterned masking element is subsequently removed from the structureusing any suitable process, such as ashing and/or resist stripping.

Numerous other embodiments of methods to form the finsandmay be suitable. For example, the finsandmay be patterned using double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrateand patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the finsand

Subsequently, methodat operationforms isolation featuresbetween the finsand, where a top surface of the isolation featuresis below the bottommost non-channel layer. The isolation featuresmay include silicon oxide (SiO and/or SiO), tetraethylorthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), a low-k dielectric material (having a dielectric constant less than that of silicon oxide, which is about 3.9), other suitable materials, or combinations thereof. The isolation featuresmay include shallow trench isolation (STI) features. In some embodiments, the isolation featuresare formed by filling trenches that separate the finsandwith a dielectric material described above by any suitable method, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. The dielectric material may subsequently be planarized by a chemical-mechanical planarization/polishing (CMP) process and selectively etched back to form the isolation features. The isolation featuresmay include a single-layer structure or a multi-layer structure.

At operation, referring to, methodforms cladding layersalong sidewalls of the finsandand over the isolation features. In the present embodiments, the cladding layersand the non-channel layersare sacrificial layers configured to be replaced with a metal gate stack in a channel region of the fin. In the present embodiments, the cladding layershave the same composition as the non-channel layersand include SiGe. In some embodiments, the cladding layersare grown epitaxially by a suitable method discussed above with respect to forming the ML. In some embodiments, the cladding layersare deposited conformally, rather than grown epitaxially, over surfaces of the structureas a blanket amorphous layer. In some examples, the cladding layersmay be formed to a thickness of about 5 nm to about 10 nm. Subsequently, methodperforms an etching process to selectively remove portions of the cladding layer, thereby exposing portions of the isolation featuresand a top surface of the hard mask layer. The etching process may include a dry etching process, a wet etching process, a reactive ion etching (RIE) process, or combinations thereof.

Referring to, methodat operationforms a dielectric helmetover the isolation features. In the present embodiments, forming the dielectric helmetincludes first forming a dielectric structureover the isolation features. The dielectric structureis configured to isolate adjacent finsandand to provide a substrate over which a dielectric helmetis formed before forming the dummy gate structure. The dielectric structuremay include any suitable material, such as SiO and/or SiO, silicon nitride (SiN), silicon carbide (SiC), oxygen-containing silicon nitride (SiON), oxygen-containing silicon carbide (SiOC), carbon-containing silicon nitride (SiCN), FSG, a low-k dielectric material, other suitable materials, or combinations thereof. The dielectric structuremay include a single-layer structure or a multi-layer structure as depicted herein, where the dielectric structureincludes a sub-layerdisposed over a sub-layer. In some embodiments, the dielectric structureand the isolation featuresdiffer in composition. The dielectric structure(or each sub-layer thereof) may be deposited by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof, and subsequently planarized by one or more CMP processes, such that a top surface of the dielectric structureis substantially co-planar with a top surface of the hard mask layer.

Subsequently, methodforms the dielectric helmetover the dielectric structure. The dielectric helmetmay include SiN, SiC, SiON, SiOC, SiCN, AlO, SiO and/or SiO, a high-k dielectric material (having a k value greater than that of silicon oxide, which is about 3.9), other suitable materials, or combinations thereof. In the present embodiments, the dielectric helmetincludes a high-k dielectric material for enhancing the etching resistance of the dielectric helmetduring the subsequent processing steps. The dielectric helmetmay include a single-layer structure or a multi-layer structure. In some embodiments, a dielectric constant of the dielectric helmetis greater than that of the dielectric structureand the isolation features. In some embodiments, portions of the dielectric helmetare configured to truncate a metal gate stack into multiple portions. In this regard, the dielectric helmetmay be patterned to form one or more gate isolation features (or a gate cut feature) that are self-aligned with the underlying dielectric structureand between finsand

Methodmay form the dielectric helmetby first recessing a top portion of the dielectric structureto form trenches, such that a top surface of the recessed dielectric structureis substantially co-planar with the topmost channel layer. The etching process may include any suitable process, such as a dry etching process, a wet etching process, an RIE process, other suitable processes, or combinations thereof. Then, methodproceeds to depositing one or more dielectric materials in the trenches and performing a CMP process to form the dielectric helmet. The one or more dielectric materials may be deposited by any suitable method, such as CVD, FCVD, ALD, other suitable methods, or combinations thereof. Subsequently, methodremoves the hard mask layerfrom the structureto expose the topmost channel layerof the ML. As such, the dielectric helmetprotrude from top surfaces of the finsand. In the present embodiments, methodselectively removes the hard mask layerwithout removing, or substantially removing, the dielectric helmetand the topmost channel layerof the ML.

Referring to, methodat operationforms a dummy (or placeholder) gate structureover the finsandvia a series of photolithography and etching processes, where the dummy gate structureis subsequently replaced with a metal gate structure. The dummy gate structuremay include a dummy gate electrode (not depicted separately) disposed over an optional dummy gate dielectric layer and/or an interfacial layer (not depicted separately). The dummy gate electrode may include polysilicon (poly-Si), the dummy gate dielectric layer may include a suitable dielectric material (e.g., SiO and/or SiO, SiON, etc.), and the interfacial layer may include an oxide material (e.g., SiO and/or SiO2). Other materials may also be applicable for the present embodiments. Various layers of the dummy gate structuremay be formed by methods such as thermal oxidation, chemical oxidation, CVD, ALD, physical vapor deposition (PVD), plating, other suitable methods, or combinations thereof.

Referring to, methodforms top gate spacerson sidewalls of the dummy gate structure. The top gate spacersmay include a single-layer structure or a multi-layer structure and may include SiO and/or SiO, SiN, SiC, SiON, SiOC, SiCN, air, a low-k dielectric material, a high-k dielectric material (e.g., hafnium oxide (HfO), lanthanum oxide (LaO), etc.), other suitable materials, or combinations thereof. Each spacer layer of the top gate spacersmay be formed by first depositing a dielectric layer over the dummy gate structurevia a suitable deposition method (e.g., CVD and/or ALD) and subsequently removing portions of the dielectric layer in an anisotropic (e.g., directional) etching process (e.g., a dry etching process), leaving the top gate spacerson the sidewalls of each dummy gate structure.

Referring to, methodat operationforms epitaxial source/drain (S/D) featuresin the finsandand adjacent to the dummy gate structure. In the present embodiments, methodforms the epitaxial S/D featuresby first forming S/D recesses (not depicted) in the S/D regions of the finsand, forming inner gate spacerson sidewalls of the non-channel layersthat are exposed in the S/D recesses, and forming epitaxial S/D featuresin the S/D recesses.

In the present embodiments, methodforms the S/D recesses by implementing an etching process that selectively removes portions of the finsandin the S/D regions. In some embodiments, the etching process is a dry etching process employing a suitable etchant capable of removing the channel layers(e.g., Si) and the non-channel layers(e.g., SiGe) of the ML. A cleaning process may subsequently be performed to clean the S/D recesses with a hydrofluoric acid (HF) solution or other suitable solution.

The inner gate spacersmay be a single-layer structure or a multi-layer structure and may include silicon oxide, SiN, SiCN, SiOC, SiON, SiOCN, a low-k dielectric material, air, a high-k dielectric material (e.g., HfO, LaO, etc.), other suitable dielectric material, or combination thereof. In some embodiments, the inner gate spacershave a composition different from that of the top gate spacers. Forming the inner gate spacersmay include selectively removing portions of the non-channel layersexposed in the S/D recesses without removing, or substantially removing, portions of the channel layersto form trenches (not depicted). The non-channel layersmay be etched by a dry etching process. Subsequently, one or more dielectric layers are formed in the trenches, followed by one or more etching processes to remove (i.e., etch back) excess dielectric layer(s) deposited on surfaces of the channel layers, thereby forming the inner gate spacers. The one or more dielectric layers may be deposited by any suitable method, such as ALD, CVD, physical vapor deposition (PVD), other suitable methods, or combinations thereof.

Each of the epitaxial S/D featuresmay be suitable for forming a p-type MOS (PMOS) device (i.e., including a p-type epitaxial material) or, alternatively, an n-type MOS (NMOS) device (i.e., including an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi SiGe) each doped with a p-type dopant such as boron, germanium, indium, gallium, other p-type dopants, or combinations thereof. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC) each doped with an n-type dopant such as arsenic, phosphorus, other n-type dopants, or combinations thereof. In some embodiments, one or more epitaxy growth processes are performed to grow an epitaxial material in each S/D recess and over the inner gate spacers. For example, methodmay implement an epitaxy growth process similar to that discussed above with respect to forming the ML. In some embodiments, the epitaxial material is doped in-situ by adding a dopant to a source material during the epitaxial growth process. In some embodiments, the epitaxial material is doped by an ion implantation process after performing the deposition process. In some embodiments, an annealing process is subsequently performed to activate the dopants in the epitaxial S/D features.

Thereafter, referring to, methodat operationreplaces the dummy gate structurewith the metal gate structure. Methodfirst forms an etch-stop layer (ESL)over the structureto protect the underlying components, such as the epitaxial S/D features, during subsequent fabrication processes. The ESLmay include any suitable dielectric material, such as SiN, SiCN, AlO, other suitable materials, or combinations thereof, and may be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof. In the present embodiments, the ESLprovides etching selectivity with respect to its surrounding dielectric components to ensure protection against inadvertent damage to these components. Methodthen forms an interlayer dielectric (ILD) layerover the ESLto fill the space between portions of the dummy gate structure. The ILD layermay include SiO and/or SiO, a low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof, and may be formed by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. Methodsubsequently performs one or more CMP process to expose top surfaces of the dummy gate structure.

In some embodiments, before replacing the dummy gate structure, methodat operationfirst patterns the dielectric helmetsuch that at least a portion of the dielectric helmetremain as gate isolation features for separating the subsequently-formed metal gate structure while remaining portions of the dielectric helmetare removed from the structure. In some embodiments, methodpatterns the dielectric helmetby forming a patterned masking element (not depicted) to expose portions of the dummy gate structureengaged with portions of the dielectric helmetto be removed. The patterned masking element includes at least a photoresist layer capable of being patterned by a series of photolithography and etching processes discussed in detail above with respect to patterning the finsand. Thereafter, methodremoves portions of the dummy gate structureexposed by the patterned masking element to expose portions of the dielectric helmetin an etching process (e.g., a dry etching process). After implementing the etching process, the patterned masking element is removed from the structureby any suitable method, such as resist stripping and/or plasma ashing. The exposed portions of the dielectric helmetare then selectively removed with respect to the dummy gate structurein a suitable etching process (e.g., a dry etching process) to form the patterned dielectric helmet. In some embodiments, operationis optional and the dielectric helmetis patterned at a subsequent operation. In some embodiments, referring to, the depicted portions of the dielectric helmetare removed from the structure.

Subsequently, methodperforms an etching process to remove the dummy gate structure(or remaining portions thereof after patterning the dielectric helmet), thereby forming gate trenches (not depicted) between the top gate spacers. The etching process may be a dry etching process, a wet etching process, an RIE process, other suitable processes, or combinations thereof. For embodiments in which the finsandeach include the ML, methodthen removes the cladding layersto form vertical openings (not depicted) along the sidewalls of the channel layersand removes the non-channel layersto form horizontal openings (not depicted) interleaved with the channel layers. In some embodiments, methodimplements separate etching processes to remove the cladding layersand the non-channel layer. For example, methodmay perform a first etching process to remove the cladding layers, resulting in vertical openings along the sidewalls of each of the finsand, and then perform a second etching process to remove the non-channel layers, resulting in horizontal openings interleaved with the channel layers. For embodiments in which the non-channel layersand the cladding layershave the same composition (e.g., SiGe), the first and the second etching processes may be implemented using the same etchant, such as a fluorine-containing etchant including hydrofluoric acid (HF), F, other fluorine-containing etchants (e.g., CF, CHF, CHF, etc.), or combinations thereof. For embodiments in which each finandincludes a single semiconductor layer, the process of removing the cladding layersand the non-channel layerare omitted.

Still referring to, methodthen forms the metal gate structurein the gate trenches, the vertical openings (if present), and the horizontal openings (if present). Accordingly, for embodiments in which the finsandeach include the ML, portions of each of the metal gate structurewrap around (or interleaved with) each channel layerand extend along the sidewalls of the finsand

In the present embodiments, still referring to, the metal gate structureincludes a gate dielectric layerand a metal gate electrodedisposed over the gate dielectric layer. The gate dielectric layermay include a high-k dielectric material, such as HfO, LaO, other suitable materials, or combinations thereof. The metal gate electrodeincludes a work function metal (WFM) layer (not depicted separately) and a bulk conductive layer (not depicted separately) disposed over the WFM layer. The WFM layer may include a p-type or an n-type WFM, such as TiN, TaN, WN, ZrSi, MoSi, TaSi, NiSi, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable work function metals, or combinations thereof. The bulk conductive layer may include Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, other suitable materials, or combinations thereof. In some embodiments, the metal gate electrodeincludes an Al-containing WFM, such as TaAl, TaAlC, TiAlN, other Al-containing WFMs, or combinations thereof. In some embodiments, the metal gate electrodedoes not include a bulk conductive layer due to the reduced gate dimension (e.g., gate length) resulting from increased device density. In other words, the WFM layer(s) may completely fill the gate trenches and the openings before forming the bulk conductive layer.

The metal gate structuremay further include other material layers (may not be depicted), such as an interfacial layerdisposed on surfaces of the channel layers, a capping layer, a barrier layer, other suitable layers, or combinations thereof. Various layers of the metal gate structuremay be formed by various methods including, for example, ALD, CVD, PVD, plating, other suitable methods, or combinations thereof. After forming the bulk conductive layer, one or more CMP processes are performed to remove excessive material formed on top surface of the ILD layer, thereby planarizing the structure.

Thereafter, methodat operationforms a metal capping layerover the metal gate structure. In the present embodiments, the metal capping layeris formed by implementing methoddepicted in.

Referring to, methodat operationrecesses the metal gate structureto form a trenchin an etching process. The etching processmay be a dry etching process, a wet etching process, an RIE process, other suitable processes, or combinations thereof, and employ one or more etchant capable of removing various layers of the metal gate structurewithout removing, or substantially removing, the surrounding dielectric components, such as the top gate spacers, the ESL, and the ILD layer. In some embodiments, the etching processresults in a substantially flat top surface in the recessed metal gate structure, such as that depicted in. In some embodiments, the etching processresults in a depressed (i.e., a concave or curved upward) top surface in the recessed metal gate structure, as depicted in an enlarged view of a portion of the structureenclosed in the dashed circle in. This may be caused by the fact that the etching rate of the gate dielectric layeris slightly lower than that of the various layers of the metal gate electrode. In addition, the deposition of various layers of the metal gate electrode, e.g., the WFM layers, may result in a seam (similar to seamdepicted in) within the layers, which may also contribute to the different etching rates within the metal gate structure. In the present embodiments, the depth of the trenchis controlled by adjusting etching parameters such as etching duration of the etching process.

In some embodiments, referring to, a ratio of a height Hof a remaining portion of the metal gate structureto a total height Hof the metal gate structurebefore performing the etching processis at least about 0.3. In some examples, the ratio may be about 0.3 to about 0.5. In some embodiments, a difference Hbetween the height Hand H, which also defines the depth of the trench, is different from the height H, i.e., the height Hmay be greater or less than the height H. In some embodiments, the height His substantially the same as the height H. In some examples, the height Hmay be at least about 6 nm and the height Hmay be about 14 nm to about 18 nm. In further examples, the height Hmay be at least about 2 nm and no greater than about 12 nm. Other dimensions of the metal gate structuremay also be applicable in the present embodiments. Nevertheless, if the height His too small, there may not be enough space for the subsequent deposition of glue layer (e.g., glue layer) and a metal capping layer (e.g., metal capping layer). On the other hand, an upper limit of the height Hwould only be dictated by the height Hand the minimum height Hof the remaining portion of the metal gate structure.

At operation, referring to, methodforms a glue layer (or an adhesion layer)over the structurein a deposition process. In the present embodiments, the glue layerincludes a nitrogen-containing material, such as TiN, TaN, or a combination thereof. In the present embodiments, the glue layeris deposited conformally over the structure such that it is formed along sidewall and bottom surfaces of the trenchas well as a top surface of the ILD layer. In some embodiments, the deposition processis an ALD process. In some embodiments, the glue layeris formed to a thickness of about 1 nm to about 1.5 nm.

Subsequently, methodmay proceed to operationto form the metal capping layeror alternatively, to operationsandto form the metal capping layer.

In some embodiments, referring to, methodat operationperforms a deposition processto form the metal capping layerover the glue layer, thereby filling the trenchand forming a portion of the metal capping layerover the top surface of the ILD layer. In the present embodiments, the metal capping layerincludes a conductive material configured to reduce resistance of the metal gate structure. In some embodiments, the metal capping layerincludes a low-resistance metal, such as W. In some embodiments, the metal capping layerhas a composition that is the same as the bulk conductive layer included in the metal gate structure. In some embodiments, the metal capping layerhas a composition that is different from the bulk conductive layer included in the metal gate structure. Other low-resistance metals that may be contemplated in the present disclosure include Rh, Ir, Ru, Co, Cu, Ag, other suitable metals, or combinations thereof. In some embodiments, the metal capping layerincludes a metal that has lower resistance than the metal included in the bulk conductive layer of the metal gate structure.

In the present embodiments, the deposition processgrows the metal capping layerover an entirety of the glue layer, including the bottom and sidewall surfaces of the trench, thus completely filling the trench. In this regard, the deposition processis not a selective deposition process that grows the metal capping layerin a bottom-up configuration. In some embodiments, the portion of the metal capping layerformed in the trenchis defined by a thickness H, which is a difference between the height H() and the thickness of the glue layer. In some embodiments, the thickness of the glue layeris at least about 1 nm to prevent peeling between the metal capping layerand the metal gate structure. In some embodiments, the metal capping layeris defined by a thickness (i.e., the height H) that is greater than the thickness of the glue layer. In some embodiments, the thickness His at least about 1 nm and less than about 11 nm. Furthermore, still referring to, the deposition processmay result in the formation of a seamdisposed within a portion of the metal capping layerabove the top surface of the ILD layer, which is subsequently removed by a planarization process.

In the present embodiments, the deposition processis an ALD process that employs tungsten hexafluoride (WF) as a precursor gas in the following Reaction I:BH+2WF→2W+2BF+6HF  (Reaction I),where BHis a reducing gas and argon (Ar) is a carrier (or purging) gas for the reaction. In some embodiments, a different reducing gas, such as SiH, is used in the reduction of WFto form W in the metal capping layerin the following Reaction II:SiH+2WF→2W+SiHF+6HF  (Reaction II).In the present embodiments, both Reactions I and II are spontaneous reactions that provide W in metallic form. In some embodiments, hydrogen gas (H) is optionally used in addition to BHor SiHas a reducing gas to increase the rate of Reaction I or Reaction II, respectively. It is noted, however, that using Halone would not complete either Reaction I or Reaction II as provided herein. Both Reactions I and II may be implemented where the temperature of the precursor gas is at room temperature (e.g., about 20° C. to about 25° C.), the processing temperature is about 275° C. to about 300° C., and the processing pressure is about 5 Torr to about 30 Torr. Other deposition parameters may also be applicable in the present embodiments.

illustrates an example schematic of an ALD process applicable in the present embodiments. To form the metal capping layerthat contains W, alternating pulses of the precursor gas (e.g., WF) and reducing gas (e.g., BHor SiHwith optional H) are applied to the structurein an ALD chamber to initiate the reaction (e.g., Reaction I or Reaction II) for forming W, followed by application of a purging gas (e.g., Ar) to remove any reaction by-product (e.g., BF, HF, and/or SiHF). One cycle of deposition is completed after each set of alternating pulses of the precursor gas and the reducing gas is applied. Additional cycles may be repeated to increase a thickness (e.g., the thickness H) of the metal capping layer. In other words, the thickness of the metal capping layerincreases with increasing number of deposition cycles. For example, referring to, at a fixed processing temperature, increasing the number of deposition cycle from Nto N, increases the thickness of the metal capping layerfrom Hto H. In addition, the thickness of the metal capping layeralso increases with increasing processing temperature. This may be demonstrated by the upward trend of each curve corresponding to the cycle numbers Nand N, respectively, as a function of temperature. However, within the range between a temperature Tl and a temperature T, e.g., between about 275° C. and about 300° C., the change in thickness as a function of temperature is negligible, indicating that such is a suitable range of processing temperature for implementing the deposition process. In some examples, a cycle number Nof 4 corresponds to a thickness Hof about 2 nm and a cycle number Nof 10 corresponds to a thickness Hof about 8 nm. Other cycle numbers and thicknesses may also be applicable for the present embodiments.

Thereafter, referring again to, methodproceeds from operationto operationby performing a planarization processto remove portions of the glue layerand the metal capping layerformed over the top surface of the ILD layer(i.e., along the depicted dotted line), thereby completing the formation of the metal capping layer. Referring to, the planarization processresults in at least a portion of the metal capping layerto be planar with the ILD layer. In the present embodiments, the planarization processis a CMP process.

In some embodiments, referring to, methodproceeds from operationto operationby performing a deposition processto form a first portionof the metal capping layerin a deposition process. In the present embodiments, the first portionhas the same composition as the metal capping layerdiscussed in detail above with respect to. For example, the first portionincludes a conductive material such as W. In the present embodiments, the deposition processis an ALD process similar to the deposition process. In this regard, the deposition processmay employ Reaction I or Reaction II to form the first portionas discussed in detail above. However, the deposition processdiffers from the deposition processin that the deposition processis configured to form the first portionas a seed layer, which only partially, rather than completely, fills the trench. In other words, the first portionhas a thickness that is less than the thickness Hdefined above. In some embodiments, the first portionis formed to a thickness Hthat is greater than the thickness of the glue layer. In some examples, the thickness Hmay be about 2 nm to about 3 nm. Accordingly, the duration of the deposition processis controlled to be less than the duration of the deposition processto ensure that the first portionpartially fills the trench.

Subsequently, referring to, methodat operationforms a second portionover the first portionin a deposition process, thereby forming the metal capping layerto completely fill the trench. In some embodiments, the second portionis formed to a thickness that is greater than the thickness H. In the present embodiments, the deposition processis a CVD process that employs tungsten hexafluoride (WF) as a precursor gas in the following Reaction III:3H+WF→W+6HF  (Reaction III),where His the reducing gas and Ar is the carrier gas. Reaction III may be implemented where the temperature of the precursor gas is at room temperature (e.g., about 20° C. to about 25° C.), the processing temperature is about 275° C. to about 300° C., and the processing pressure is about 250 Torr to about 300 Torr. It is noted that the processing pressure of Reactions I and II is less than that of Reaction III due to the fact that the ALD process is generally a self-limiting process and thus does not require as high of a processing pressure than the CVD process. Other deposition parameters may also be applicable in the present embodiments. Similar to Reactions I and II, the reaction by-produce of Reaction III, i.e., HF, is removed from the deposition chamber by the purging gas Ar. Different from Reactions I and II, Hmay be used as the lone reducing gas for Reaction III to ensure that the deposition processproceeds in a suitable rate.

In some embodiments, the rate of Reaction III is less than that of Reactions I and II. However, because the ALD process proceeds in a layer-by-layer manner, the overall duration of forming the metal capping layerby Reaction I or Reaction II may be longer than that by Reaction III. In this regard, for a relatively deeper trench, it may reduce the overall duration of deposition to implement a combination of the deposition processesand(at operationsand) rather than to implement the deposition process(at operation) alone. In some examples, if the depth Hof the trenchis greater than about 3 nm, implementing the combination of the deposition processesandmay require less time than implementing the deposition processalone. It is noted, however, that any of the Reactions I, II, and III, or combinations thereof, is applicable in the present embodiments and that the composition and structure of the resulting metal capping layerdoes not vary with the specific deposition process(es) employed.

Thereafter, methodproceeds from operationto operationby performing a planarization processto remove portions of the glue layer, the first portion, and the second portionformed over the top surface of the ILD layer, thereby completing the formation of the metal capping layer. The planarization processmay be a CMP process similar to the planarization processin that the planarization processmay implement similar CMP slurries as the planarization processand result in at least a portion of the metal capping layerto be planar with the ILD layeras depicted in.

each depict an embodiment of a portion of the structureenclosed in dashed circle as shown in. In some embodiments, referring to, due to the top surface of the trenchhaving a concave profile (see), i.e., curved upward, a bottom surface of the metal capping layer(and the glue layer) conforms to such concave profile. In the present embodiments, the concave profile is defined by an angle α with respect to a horizontal reference line, where the angle α is greater than about 0 degree to about 50 degrees. In some embodiments, referring to, the angle α is approximately 0 degree, i.e., the bottom surface of the glue layeris substantially flat.

In some embodiments, Referring to, a top surface of the metal capping layeris curved downward, i.e., having a convex profile, where a highest point of the top surface is substantially planar with the top surface of the top gate spacersand the ILD layer, as indicated by a horizontal dashed line. The convex profile may be defined by an angle β with respect to the horizontal reference line, where the angle β may be similar to the angle α, i.e., greater than about 0 degree to about 50 degrees. The curved top surface may result from a slurry implemented during the planarization processorreacting with sidewall portions to a greater extent than with a center portion of the metal capping layer, causing more of the metal capping layerto be removed near its interface with the glue layer. In some instances, referring to, the selective removal may cause void (or air gap)that penetrate along the interface and expose upper portions of the sidewalls of the metal capping layer. In some embodiments, the extent of the selective removal by the planarization processoris controlled by adjusting various parameters of the CMP process including, for example, composition of the slurry. In some embodiments, referring to, the top surface of the metal capping layeris substantially planar with the top surface of the top gate spacersand the ILD layer.