Semiconductor package including interposors and electronic system

This application claims benefit of priority to Korean Patent Application No. 10-2022-0082615, filed on Jul. 5, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

A semiconductor package may include a plurality of interposers and an electronic system including the same.

Recently, semiconductor packages using an interposer and including a plurality of semiconductor chips have been developed in accordance with demand for high performance and high integration of semiconductor packages.

Example embodiments provide a semiconductor package having improved performance, while including a plurality of interposers and a plurality of semiconductor chip structures.

Example embodiments provide an electronic system including the semiconductor package.

According to example embodiments, an electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.

According to example embodiments, an electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a controller semiconductor chip on the first and second interposers, and a memory semiconductor chip on the first and second interposers and spaced apart from the controller semiconductor chip. The controller semiconductor chip is configured to communicate data with the memory semiconductor chip through the first signal paths of the first interposer, and the memory semiconductor chip is configured to receive a command and an address signal from the controller semiconductor chip through the second signal paths of the second interposer.

According to example embodiments, a semiconductor package includes a package substrate, a first interposer on the package substrate and including first signal paths, a second interposer on the package substrate, spaced apart from the first interposer, and including second signal paths, a first semiconductor chip structure on the first and second interposers, and at least one second semiconductor chip structure on the first and second interposers, electrically connected to the first semiconductor chip structure through the first signal paths, and electrically connected to the first semiconductor chip structure through the second signal paths. The number of the first signal paths is different from the number of the second signal paths.

The present inventive concept will be understood through the following examples in conjunction with the accompanying drawings. However, the present inventive concept is not limited to the embodiments described herein and may be embodied in other forms. In some embodiments, when it is mentioned that certain elements or lines are connected to a target region, it may include not only direct connection but also indirect connection via other elements. In addition, a connection relationship between regions and lines described with reference to the drawings in some embodiments is only shown for an effective description of the technical content, and some embodiments may further include other regions and other lines not shown in the drawings.

An electronic system according to some embodiments of the present inventive concept will be described with reference to.is a diagram schematically illustrating an electronic system according to some embodiments of the present inventive concept.

Referring to, an electronic systemaccording to some embodiments may include a plurality of interposers INT and a plurality of semiconductor chip structures CH on the plurality of interposers INT.

The plurality of interposers INT may include a first interposer INT_and a second interposer INT_spaced apart from each other.

The first interposer INT_may include first signal paths SI_H.

The second interposer INT_may include second signal paths SI_L.

The first interposer INT_may further include first power/ground paths PWadjacent the first signal paths SI_H. The first power/ground paths PW may include first power paths PWa and first ground paths PWb.

The second interposer INT_may further include second power/ground paths PWadjacent the second signal paths SI_L. The second power/ground paths PWmay include second power paths PWc and second ground paths PWd.

The number of the first signal paths SI_H may be greater than the number of the second signal paths SI_L. For example, the number of the first signal paths SI_H may be about 1.5 times to about 1.8 times greater than the number of the second signal paths SI_L.

The plurality of semiconductor chip structures CH may include a first semiconductor chip structure CH_and a second semiconductor chip structure CH_that are spaced apart from each other.

The first semiconductor chip structure CH_may be on the first and second interposers INT_and INT_. The second semiconductor chip structure CH_may be on the first and second interposers INT_and INT_.

The electronic systemmay further include a package substrate. The plurality of interposers INT may be mounted on the package substrate. The plurality of semiconductor chip structures CH may be mounted on the plurality of interposers INT.

The first semiconductor chip structure CH_may include at least one first semiconductor chip. The second semiconductor chip structure CH_may include at least one second semiconductor chip.

The at least one first semiconductor chip of the first semiconductor chip structure CH_and the at least one second semiconductor chip of the second semiconductor chip structure CH_may include circuit regions capable of communicating at different rates. For example, the first semiconductor chip structure CH_may include a first circuit region CRand a second circuit region CR, and the second semiconductor chip structure CH_may include a third circuit region CRconfigured to communicate with the first circuit region CRand a fourth circuit region CRconfigured communicate with the second circuit region CR.

The third circuit region CRmay be configured to communicate with the first circuit region CRat a first rate through the first signal paths SI_H of the first interposer INT_. The fourth circuit region CRmay be configured to communicate with the second circuit region CRat a second rate slower than the first rate through the second signal paths SI_L of the second interposer INT_.

The first signal paths SI_H may be referred to as ‘fast signal paths’, and the second signal paths SI_L may be referred to as ‘slow signal paths’.

The first semiconductor chip structure CH_may further include a first interface region IF. As shown in, the second semiconductor chip structure CH_may further include a second interface region IF.

In another embodiment, the second interface region IFof the second semiconductor chip structure CH_may be omitted.

The first semiconductor chip structure CH_may include a first semiconductor chip, and the second semiconductor chip structure CH_may include a second semiconductor chip including circuit regions configured to communicate with the first semiconductor chip at different rates. For example, the first semiconductor chip structure CH_may include a controller semiconductor chip, and the second semiconductor chip structure CH_may include at least one memory semiconductor chip. For example, the second semiconductor chip structure CH_may include a volatile memory semiconductor chip, such as a DRAM or a nonvolatile memory semiconductor chip, such as a flash memory.

The first semiconductor chip structure CH_, that is, the controller semiconductor chip, may be configured to communicate data with the second semiconductor chip structure CH_, that is, the memory semiconductor chip, through the first signal paths SI_H of the first interposer INT_at a high speed, and the second semiconductor chip structure CH_may receive command and address signals from the controller semiconductor chip CH_through the second signal paths SI_L of the second interposer INT_at a low speed. For example, the first circuit region CRof the controller semiconductor chip CHmay be configured to communicate data with the third circuit region CRof the memory semiconductor chip CH_at a first rate through the first signal paths SI_H of the first interposer INT_, and the fourth circuit region CRof the memory semiconductor chip CH_may receive command and address signals from the second circuit region CRof the controller semiconductor chip CH_at a second rate slower than the first rate through the second signal paths SI_L of the second interposer INT_.

The electronic systemmay further include an electronic deviceelectrically connected to the semiconductor packageby a system bus.

The electronic devicemay be a host, and may control general operations of the electronic system. For example, a host interface between the electronic deviceand the first semiconductor chip structure CH_may include various protocols for exchanging data between the electronic deviceand the first semiconductor chip structure CH_. For example, the first semiconductor chip structure CH_may communicate with the electronic deviceor the outside through at least one of a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol, etc.

The electronic systemmay be one of various components of a system, such as an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage constituting a data center, a device that may transmit and receive information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of the various components constituting a computing system.

Next, an example of the semiconductor packagewill be described with reference to.is a top view schematically illustrating the semiconductor packageof the electronic systemof, andis a cross-sectional view schematically illustrating a region taken along line I-I′ ofto describe an example of the semiconductor packageof the electronic systemof,is a cross-sectional view schematically illustrating a region taken along line II-IF ofto describe an example of the semiconductor packageof the electronic systemof, andis a cross-sectional view schematically illustrating a region taken along lines and IV-IV′ ofto describe an example of the semiconductor packageof the electronic systemof.

Referring totogether with, a semiconductor package according to an example embodiment may include the package substrate, the plurality of interposers INT, and a plurality of chip structures CH as described above with reference to.

In example embodiments, the package substratemay include a substrate body, lower padsbelow the substrate body, connection patternsbelow the lower padsand electrically connected to the lower pads, upper padson the substrate body, and an inner interconnectionelectrically connecting the lower padsto the upper padsin the substrate body. The connection patternsmay be solder balls including a solder material, such as SnAg or SaAgCu. The package substratemay be a printed circuit board.

In example embodiments, the plurality of interposers INT may include a first interposerand a second interposermounted on the package substrateand spaced apart from each other. The first interposermay be the first interposer INT_of, and the second interposermay be the second interposer INT_of.

In example embodiments, each of the plurality of interposers INT may be a silicon interposer.

The first interposermay include the first signal paths SI_H and the first power/ground paths PWdescribed above with reference to. The first interposermay further include a first substrate, a first lower insulating layer, a first upper insulating layer, first lower pads, first connection structures comprising a first interconnection structureand a first insulating structure, first conductive bumps, and first through-electrode structures. The first substratemay be formed of, for example, any one of a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the first substrateis a silicon substrate, the first interposermay be referred to as a silicon interposer. When the first substrateis an organic substrate, the first interposermay be referred to as a panel interposer.

The first lower insulating layermay cover a lower surface of the first substrate. The first lower padsmay be below the first lower insulating layer. The first upper insulating layermay cover an upper surface of the first substrate

Each of the first through-electrode structuresmay include a through-electrodepassing through the first substrate, the first lower insulating layer, and the first upper insulating layerand an insulating spacercovering a side surface of the through-electrode.

The first connection structures may include a first insulating structureon the first upper insulating layerand a first interconnection structureat least partially positioned in the first insulating structure

The first interconnection structuremay be electrically connected to the first through-electrode structures. At least a portion of the first interconnection structuremay be on the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW. At least a portion of the first interconnection structuremay be formed of the same conductive material as that of the first signal paths SI_H and the first power/ground paths PW. The first signal paths SI_H and the first power/ground paths PWmay be in the first insulating structure

At least a portion of the first interconnection structuremay be on substantially the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW.

The first through-electrode structuresand the first interconnection structuremay be a first interface path electrically connected to the first interface region IF.

The first interconnection structuremay have a single-layer structure or a multilayer structure.

When the first interconnection structurehas a multilayer structure, the first interconnection structuremay include first lower padselectrically connected to the through-electrodesof the first through-electrode structures, first upper padson the first insulating structure, first interconnection linesin the first insulating structure, first lower viasbetween the first interconnection linesand the first lower pads, and first upper viasbetween the first interconnection linesand the first upper pads

The first signal paths SI_H and the first power/ground paths PWmay include line portions on substantially the same vertical level as that of the first interconnection lines, via portions on substantially the same vertical level as that of the first upper vias, and pad portions on substantially the same vertical level as that of the first upper pads

The second interposermay include the second signal paths SI_L and the second power/ground paths PWdescribed above with reference to. The second signal paths SI_L may be on substantially the same vertical level as that of the first signal paths SI_H. The second interposermay further include a second substrate, a second lower insulating layer, a second upper insulating layer, second lower pads, second connection structures comprising a second interconnection structureand a second insulating structure, second conductive bumps, and second through-electrode structures. The second substratemay be formed of the same material as that of the first substrate. The second lower insulating layermay cover a lower surface of the second substrate. The second lower padsmay be below the second lower insulating layer. The second upper insulating layermay cover an upper surface of the second substrate

Each of the second through-electrode structuresmay include a through-electrodepassing through the second substrate, the second lower insulating layer, and the second upper insulating layerand an insulating spacercovering a side surface of the through-electrode.

The second connection structures may include a second insulating structureon the second upper insulating layerand a second interconnection structureat least partially positioned in the second insulating structure

At least a portion of the second interconnection structuremay be on substantially the same vertical level as the second signal paths SI_L and the second power/ground paths PW.