Transistor with a primary gate wrapping a floating secondary gate

This invention was made with government support under contract number HQ0727790700 and awarded by the United States Defense Microelectronics Activity (DMEA). The government has certain rights in the invention.

The present disclosure relates to transistors, and, more particularly, to embodiments of a semiconductor structure including a transistor and to embodiments of a method of forming the structure.

Factors considered in modern integrated circuit (IC) design include, but are not limited to, performance improvement, size scaling, and power consumption. Oftentimes, however, there is a tradeoff between these factors. For example, with device size scaling, transistors, such as high electron mobility transistors (HEMTs), can suffer from performance degradation.

Disclosed herein are embodiments of a structure. The structure can include a substrate and a transistor on the substrate. The transistor can include a barrier layer. The transistor can further include both a primary gate and a secondary gate. The secondary gate can be on the barrier layer and can have opposing sidewalls. The primary gate can have first portions, which are on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively.

In some of the disclosed embodiments, the structure can include a substrate and a transistor on the substrate. The transistor can include a barrier layer. The transistor can also include a primary gate and a secondary gate. The secondary gate can be on the barrier layer. It can have opposing sidewalls, opposing end walls and a top surface. Additionally, the secondary gate can include a P-type III-V semiconductor layer and can be floating. The primary gate can include a gate dielectric layer, which is immediately adjacent to the barrier layer and which extends over and is immediately adjacent to the opposing sidewalls, the opposing end walls, and the top surface of the secondary gate, and a gate conductor layer, which is on the gate dielectric layer. The primary gate can have: first portions, which are on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate; a second portion, which is on the top surface of the secondary gate; and third portions, which are on the barrier layer and positioned laterally adjacent to the opposing end walls, respectively, of the secondary gate.

Also disclosed herein are method embodiments for forming a semiconductor structure. The method embodiments can include providing a substrate and forming a transistor on the substrate. forming the transistor can include forming a secondary gate on a barrier layer and forming a primary gate adjacent to the secondary gate. Specifically, the primary gate can be formed so as to at least have first portions on the barrier layer and positioned laterally adjacent to the opposing sidewalls, respectively, of the secondary gate.

As mentioned above, HEMTs, including d-mode and e-mode HEMTs, have emerged as a leading technology for RF and mmWave wireless applications. Those skilled in the art will recognize that conventional HEMTs are d-mode devices. A d-mode HEMT refers to a HEMT that is normally in an ON-state (i.e., conductive) and only switches to an OFF-state (i.e., becomes non-conductive) when a voltage is applied to the gate of the HEMT. This normally ON-state is due to a zero-bias two-dimensional electron gas (2DEG) below the gate and, particularly, between the barrier and channel layers of the HEMT. Pinch-off refers to the point at which application of a gate voltage (Vg) to the gate of the d-mode HEMT stops charge carrier flow and thereby stops current flow through the channel layer between source/drain terminals. An e-mode HEMT refers to HEMT that is normally in an OFF-state (i.e., non-conductive) and only switches to an ON-state (i.e., becomes conductive) when a voltage is applied to the gate. The gate of a d-mode HEMT can be modified to form an e-mode HEMT. One technique for modifying is to insert a P-type III-V semiconductor layer (e.g., a magnesium (Mg)-doped gallium nitride (GaN) layer or some other suitable P-type III-V semiconductor layer) into the gate (e.g., above the barrier layer and below any gate metal) in order to suppress the zero-bias 2DEG. Unfortunately, with device size scaling HEMT devices can suffer from performance degradation. For example, with a reduction in gate pitch, d-mode HEMTs can suffer from pinch-off control issues and, thus, increased gate leakage.

In view of the foregoing, disclosed herein are embodiments of a semiconductor structure including a d-mode HEMT configured for improved pinch-off control. Specifically, the d-mode HEMT can include a channel layer and a barrier layer on the channel layer. The d-mode HEMT can further include source and drain terminals that extend through the barrier layer toward or to the channel layer and a multi-gate structure on the barrier layer positioned laterally between the source and drain terminals. The multi-gate structure can include a primary gate and, particularly, a d-mode gate that wraps over a secondary gate and, particularly, an e-mode gate. The secondary gate can include a P-type III-V semiconductor layer and be left floating. The primary gate can include essentially vertically-oriented portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate and an essentially horizontally-oriented portion on the top surface of the secondary gate. Optionally, the primary gate can also include additional essentially vertically-oriented portions positioned laterally adjacent to opposing end walls of the secondary gate. In either case, with this wrap-around multi-gate configuration, better pinch-off control is possible. Also disclosed herein are method embodiments for forming the disclosed semiconductor structures.

is a cross-section diagram of a semiconductor structureoriented along the length of a d-mode HEMTincluded therein and having a multi-gate structure.andare cross-section diagrams of the semiconductor structurealong the width of the d-mode HEMTincluded therein and illustrating alternative configurations, respectively, for the multi-gate structure, as discussed in greater detail below.

More particularly, referring toandor, alternatively,and, the semiconductor structurecan include a semiconductor substrate. The semiconductor substratecan be, for example, a silicon (Si) or Si-based substrate (e.g., a silicon carbide (SiC) substrate), a sapphire substrate, a III-V semiconductor substrate (e.g., a GaN substrate or some other suitable III-V semiconductor substrate) or any other type of semiconductor substrate suitable for forming a III-V semiconductor device thereon.

The semiconductor structurecan further include multiple epitaxially grown semiconductor layers on the semiconductor substrate. These semiconductor layers can include, for example: an optional buffer layer (not specifically shown) on the top surface of the semiconductor substrate; a channel layeron the buffer layer (or substrate); and a barrier layeron the channel layer. These epitaxial grown semiconductor layers can be, for example, III-V semiconductor layers. Those skilled in the art will recognize that a III-V semiconductor refers to a compound obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Specifically, the optional buffer layer can be employed to facilitate growth of the channel layerand to provide for lattice constants of the substratebelow and the channel layerabove. The buffer layer can be doped or undoped. Optionally, the buffer layer can be carbon-doped. The barrier layercan have a band gap that is wider than the bandgap of the channel layer. Those skilled in the art will recognize that the barrier and channel materials can be selected so that a heterojunction is formed at the interface between the two layers, thereby resulting in the formation of a two-dimensional electron gas (2DEG) in the channel layer. This 2DEG in the channel layercan provide the conductive pathway for the drifting of charges between the source and the drain.

In some embodiments, the buffer layer could be a carbon-doped gallium nitride (C—GaN) buffer layer or a buffer layer of any other material suitable for use as a buffer layer of a HEMT. The channel layercould be a GaN layer or a III-V semiconductor channel layer made of any other III-V semiconductor compound suitable for use as a channel layer in a HEMT. The barrier layercould be an aluminum gallium nitride (AlGaN) barrier layer or a barrier layer of any other material suitable for use as a barrier layer in a HEMT. For purposes of illustration, the figures and the description above depict the epitaxially grown semiconductor layers (e.g., the buffer layer (not shown); the channel layer; and the barrier layer) as being single layered structures (i.e., comprising one layer of buffer material, one layer of channel material and one layer of barrier material). However, it should be understood that, alternatively, any one or more of the epitaxially grown layers could be multi-layered structures (e.g., comprising multiple sub-layers of different buffer materials, multiple sub-layers of different III-V semiconductor channel materials and/or multiple sub-layers of different barrier materials).

The semiconductor structurecan further include a d-mode HEMTincluding portions of the barrier and channel layers, as discussed in greater detail below, and the d-mode HEMTcan have a multi-gate structure, including both a primary gateand a secondary gate, on the barrier layer.

The secondary gatecan be an e-mode gate. That is, the secondary gatecan include a monocrystalline P-type III-V semiconductor layer that has been patterned into an essentially rectangular shaped semiconductor body so that it has a bottom surface adjacent to the barrier layer, a top surface.opposite the bottom surface, opposing sidewalls., and opposing end walls.. This semiconductor body can extend laterally across an active device region of the HEMT. The P-type III-V semiconductor layer of the secondary gatecan, for example, be a Mg-doped GaN layer or any other suitable P-type III-V semiconductor layer. Additionally, the secondary gatecan be a floating gate and, more particularly, can be a non-contacted gate such that it is not biasable.

The primary gatecan be a d-mode gate that is on the barrier layerand that further wraps over the secondary gate. Specifically, the primary gatecan include a relatively thin, conformal, gate dielectric layerabove and immediately adjacent to the barrier layerand further extending over and immediately adjacent to the secondary gate. The primary gatecan also include a gate conductor layeron the gate dielectric layer. In all embodiments, the gate dielectric layercan be immediately adjacent to the opposing sidewalls.and top surface.of the secondary gateand the gate conductor layercan be on the gate dielectric layeropposite the opposing sidewalls.and the top surface.. Thus, in all embodiments, the primary gatehas first portions.(and, particularly, essentially vertically-oriented portions) on the barrier layerand positioned laterally adjacent to the opposing sidewalls.of the secondary gateand a second portion.(and, particularly, an essentially horizontally-oriented portion) on the top surface.of the secondary gate. In other words, the secondary gateis positioned laterally between the first portions.of the primary gateand below the second portion.(as shown in). In some embodiments, the gate dielectric and conductor layers-can also wrap around the opposing end walls of the secondary gatesuch that the primary gatealso includes third portions.(and, particularly, additional essentially vertically-oriented portions) on the barrier layerand positioned laterally adjacent to the opposing end walls.of the secondary gate, as shown in. In other embodiments, the primary gatecan be patterned so that the opposing end walls.of the secondary gateare devoid of the gate dielectric and conductor materials, as shown in.

In any case, in the primary gate, the gate dielectric layerof the primary gatecan include one or more layers of gate dielectric material(s). The gate dielectric material could be, for example, a high dielectric constant (K) dielectric material. Those skilled in the art will recognize that a high-K dielectric material is a dielectric material having a K value that is greater than that of silicon dioxide (SiO). Such high-K dielectric materials include, but are not limited to, hafnium (Hf)-based dielectric materials (e.g., hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium aluminum oxide, etc.) and various other dielectric materials ((e.g., aluminum oxide (AlO), tantalum oxide (TaO), zirconium oxide (ZrO), etc.). Alternatively, the gate dielectric material could be any other dielectric material suitable for use as a gate dielectric layer in a HEMT (e.g., SiO, etc.). Additionally, in the primary gate, the gate conductor layerof the primary gatecan include one or more layers of gate conductor material(s). The gate conductor material could, for example, be a metallic gate conductor material. That is, it could include one or more metal(s) or metal alloy(s) including, but not limited to, gold (Au), titanium (Ti), titanium nitride (TiN), nickel-gold (Ni—Au), or titanium-platinum-gold (Ti/Pt/Au).

A relatively thin conformal dielectric layercan cover the primary gateand extend laterally over the barrier layeron either side of the primary gate. The dielectric layercan, for example, be an etch stop layer, such as a silicon nitride layer or a layer of some other suitable etch stop material. As illustrated in, in an embodiment where the opposing end walls.of the secondary gateare devoid of the gate dielectric and conductor materials of the primary gate, this conformal dielectric layercan also be positioned laterally immediately adjacent to and can cover the opposing end walls.of the secondary gate.

As shown in, the d-mode HEMTcan also include can include source and drain terminals-with the multi-gate structure (including the primary and secondary gates) being positioned laterally between the source and drain terminals-. More specifically, the source and drain terminals-can be on opposing sides of the primary gatesuch that they are adjacent (but physically separated from) the first portions., respectively, thereof. The source and drain terminals-can be separated from the multi-gate structure by essentially the same separation distances, as illustrated, or by different separation distances (e.g., the drain terminalcould be separated from the gate by a greater separation distance than the source terminalfor increased breakdown voltage). The source and drain terminals-can, for example, include ohmic contact source and drain terminals in source/drain openings that extend through the dielectric layerand into the barrier layertoward or to the channel layer. That is, the source/drain openings can extend through the dielectric layer and at least partially through the barrier layer toward the channel layer. In some embodiments, the source and drain terminals can be essentially T-shaped, each with a lower section in a source/drain opening and an upper section on and wider than the lower section (e.g., extending laterally onto the dielectric layer), as illustrated. Such ohmic contact source and drain terminals can include one or more layers of metal or metal alloys (e.g., such ohmic contact source and drain terminals include, but are not limited to, multi-layer structures of Ti/Al/TiN, Ti/Al/Ti/Au or Mo/Al/Mo/Au). It should be noted that the source and drain terminal configurations are provided above for illustration purposes and are not intended to be limiting. Alternatively, any other suitable source and drain terminal configuration for a HEMT could be employed.

Optionally, in order to block a current path between the source and drain terminals-around the ends of the multi-gate structure, the semiconductor structurecan further include isolation regionslocated adjacent the ends of the multi-gate structure, as illustrated inor, alternatively,. For example, in an embodiment where the primary gateincludes third portions.positioned laterally adjacent to the opposing end walls.of the secondary gate, as shown in, the isolation regionscan be below and wider than the opposing end walls.of the secondary gate, can extend vertically through the barrier layerinto and, optionally, completely through the channel layer, and can further extend laterally beyond the third portions.of the primary gate. In other embodiments where the primary gatedoesn't include the third portions.at the opposing end walls.of the secondary gate, as shown in, the isolation regionscan be below and wider than the opposing end walls.of the secondary gate, can extend vertically through the barrier layerinto and, optionally, completely through the channel layer, and can further extend laterally some distance beyond the opposing end walls of the secondary gate. In any case, the isolation regionscan be semiconductor material areas that contain and, particularly, that have been doped with a dopant, such as argon (Ar), to eliminate charge build up and thereby block any potential current path(s) between the source and drain terminals-that would otherwise bypass the portion of the channel layer below the multi-gate structure by wrapping around the end(s) of the multi-gate structure. As discussed in greater detail below with regard to the method embodiments, such isolation regions can be formed using a dopant implantation process and, thus, are also referred to herein as dopant implant isolation regions. It should be noted that, alternatively, these isolation regionscan have any other suitable configuration for blocking current paths between the source and drain terminals-around the multi-gate structure.

As illustrated inand inor, alternatively, in, the semiconductor structurecan further include one or more layers of middle of the line (MOL) dielectric materialover the d-mode HEMT. For example, the MOL dielectric materialcan, optionally, include a relatively thin, conformal, dielectric layer. This dielectric layer could be another etch stop layer (e.g., another silicon nitride layer). The MOL dielectric materialcan also include a blanket layer of interlayer dielectric (ILD) material. The ILD material can be, for example, SiO, doped silicon glass (e.g., phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)), or any other suitable ILD material. Additionally, the semiconductor structurecan further include MOL contacts that extend through the MOL dielectric material to the HEMT terminals (e.g., see the MOL contactto the primary gateand the MOL contactsto the source and drain terminals-). Since, as mentioned above, the secondary gateof the d-mode HEMTcan be left floating, no MOL contacts extend to the secondary gate.

Also disclosed herein are method embodiments for forming a semiconductor structure, such as the semiconductor structureofandor, alternatively,and, described in detail above.

The method embodiments can include forming a stack of epitaxially grown semiconductor layers on a semiconductor substrate, as illustrated in. The semiconductor substratecan be, for example, a Si or Si-based substrate (e.g., a SiC substrate), a sapphire substrate, a III-V semiconductor substrate (e.g., a GaN substrate or some other suitable III-V semiconductor substrate) or any other semiconductor substrate suitable for forming a III-V semiconductor device thereon. The multiple epitaxially grown semiconductor layers can include, for example: an optional buffer layer (not specifically shown) on the top surface of the semiconductor substrate; a channel layeron the buffer layer (or substrate); and a barrier layeron the channel layer. These epitaxial grown semiconductor layers can be, for example, III-V semiconductor layers. Those skilled in the art will recognize that a III-V semiconductor refers to a compound obtained by combining group III elements, such as Al, Ga, or In, with group V elements, such as N, P, As or Sb) (e.g., GaN, InP, GaAs, or GaP).

In some embodiments, the buffer layer could be a C—GaN buffer layer or a buffer layer of any other material suitable for use as a buffer layer of a HEMT. The channel layercould be a GaN layer or a III-V semiconductor channel layer made of any other III-V semiconductor compound suitable for use as a channel layer in a HEMT. The barrier layercould be an AlGaN barrier layer or a barrier layer of any other material suitable for use as a barrier layer in a HEMT. For purposes of illustration, the figures and the description above depict the epitaxially grown semiconductor layers (e.g., the buffer layer (not shown); the channel layer; and the barrier layer) as being single layered structures (i.e., comprising one layer of buffer material, one layer of channel material and one layer of barrier material). However, it should be understood that, alternatively, any one or more of the epitaxially grown layers could be multi-layered structures (e.g., comprising multiple sub-layers of different buffer materials, multiple sub-layers of different III-V semiconductor channel materials and/or multiple sub-layers of different barrier materials).

The method embodiments can further include forming a secondary gateon the barrier layer(seeand). For example, a monocrystalline III-V semiconductor layer can be formed (e.g., epitaxially grown) on the barrier layer(see). This III-V semiconductor layer can either be in situ doped or subsequently implanted so that it has P-type conductivity. In some embodiments, the P-type III-V semiconductor layer can be a MG-doped GaN layer. Subsequently, an essentially rectangular-shaped P-type III-V semiconductor body for the secondary gatecan be formed from the P-type III-V semiconductor layer (e.g., using conventional lithographic patterning and etch techniques) such that it traverses a designated active device region for the d-mode HEMT (e.g., see). The resulting secondary gatecan have a bottom surface immediately adjacent to the barrier layer, a top surface.opposite the bottom surface, opposing sidewalls., and opposing end walls..

Optionally, the method embodiments can further include, following formation of the secondary gate, forming isolation regions(e.g., implant isolation regions), as illustrated in. Specifically, a mask(e.g., a hardmask layer, such as a silicon nitride (SiN) hardmask layer) can be formed over the partially completed structure and lithographically patterned and etched so as to form openingsin the maskthat expose only areas of the barrier layerthat extend laterally beyond the opposing end walls.of the secondary gate. Then, a dopant implantation process can be performed to implant a dopant, such as Ar, into areas of the barrier layerand further into and, optionally, through areas of the channel layeraligned below the openings, thereby forming the isolation regions. The maskcan then be removed.

The method embodiments can further include forming a primary gate. For example, a gate dielectric layer, including one or more layers of gate dielectric material(s), can be formed (e.g., deposited) over the partially completed semiconductor structure (see). The gate dielectric material could be, for example, a high-K dielectric material. As discussed above, high-K dielectric materials can include, but are not limited to, Hf-based dielectric materials and various other dielectric materials (e.g., AlO, TaO, ZrO, etc.). Alternatively, the gate dielectric material could be any other dielectric material suitable for use as a gate dielectric layer in a HEMT (e.g., SiO, etc.). Additionally, a gate conductor layer, including one or more layers of gate conductor material(s), can be formed (e.g., deposited) on the gate dielectric layer, thereby forming a gate stack (see). The gate conductor material could, for example, be a metallic gate conductor material. That is, it could include one or more metal(s) or metal alloy(s) including, but not limited to, Au, Ti, TiN, Ni—Au, or Ti/Pt/Au. Techniques for forming (e.g., depositing) such gate dielectric and gate conductor materials are well known in the art and, thus, the details have been omitted in order to allow the reader to focus on the salient aspects of the disclosed embodiments.

The primary gatecan then be formed from this gate stack (e.g., using conventional lithographic patterning and etch techniques). For example, another mask(e.g., another hardmask layer, such as a silicon nitride hardmask layer) can be formed over the partially completed structure and lithographically patterned and etched so as to define the shape of the primary gate and exposing areas of the gate conductor material that are to be removed. As illustrated in, the maskcan be patterned and etched so that it is aligned above and longer than the gate length of the secondary gate(as measured in the XX direction) and, thus, so that it extends beyond the opposing sidewalls.of the secondary gate. As illustrated in, in some embodiments (e.g., during formation of the semiconductor structurewith the cross-section shown in), the maskcan also be wider than the gate width of the secondary gate(as measured in the YY direction) and, thus, can extend laterally beyond the opposing end walls.of the secondary gate. Alternatively, as illustrated in, in other embodiments (e.g., during formation of the semiconductor structurewith the cross-section shown in), the maskcan be the same width as or narrower than the gate width of the secondary gate(as measured in the YY direction) and, thus, does not extend beyond the opposing end walls.of the secondary gate. An anisotropic etch process can then be performed to remove the exposed portions of the gate conductor layerand, optionally, the gate dielectric layerbelow to complete the primary gate(seeandor, alternatively,and). As illustrated, depending on the size of the mask, the opposing end walls of the secondary gate may remain covered (see) or may be exposed (see).

Following completion of the primary gate, a relatively thin conformal dielectric layer(e.g., a conformal etch stop layer, such as a conformal SiN etch stop layer or a conformal layer of some other suitable etch stop material) can be formed over the partially completed structure (seeandor, alternatively,). It should be noted that if the primary gateincludes third portion.adjacent to the opposing end walls.of the secondary gate(e.g., as shown in), then the conformal dielectric layerwill be physically separated from the secondary gateon all sides (e.g., as shown in); whereas, if the gate conductor and dielectric materials are completely removed from the opposing end walls of the secondary gate(e.g., as shown in), then the conformal dielectric layerwill be immediately adjacent to and cover the opposing end walls.(e.g., as shown in).

Additional processing to complete the HEMTcan include formation of source and drain terminals-. In some embodiments, formation of the source and drain terminals-can include forming source and drain openings (e.g., using lithographic patterning and etch processes). The source and drain openings can be formed so that they are parallel to and on opposing sides of the multi-gate structure (e.g., separated from the multi-gate structure by the same separation distance or by different separation distances). The source and drain openings can be formed so that they that extend through the dielectric layerand into the barrier layertoward or to the channel layer. One or more layers of metal or metal alloys can then be deposited over the partially completed structure so as to fill the openings. These layers can be selected to form ohmic contact source and drain terminals and can include, for example, Ti/Al/TiN, Ti/Al/Ti/Au or Mo/Al/Mo/Au. The stack of metal or metal alloy layers can then be patterned (e.g., lithographically patterned and etched) to form the discrete source and drain terminals-(e.g., T-shaped source and drain terminals). Alternatively, any other suitable technique for forming source and drain terminals could be employed.

Then, as illustrated inandor, alternatively,and, using conventional MOL processing techniques, one or more layers of MOL dielectric material(e.g., an etch stop layer, a blanket ILD material, etc., as discussed in greater detail above with regard to the structure embodiments) can be formed over the partially completed structure and MOL contacts can be formed. The MOL contacts can specifically be formed so that they extend essentially vertically through the MOL dielectric material to the HEMT terminals (e.g., see the MOL contactto the primary gateand the MOL contactsto the source and drain terminals-). However, as mentioned above, in the disclosed embodiments, the secondary gateof the d-mode HEMTcan be left floating. Thus, as illustrated, no MOL contacts are formed to the secondary gate.

It should be understood that in the structures and method described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region. Furthermore, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, it is more conductive (less resistive) than the other semiconductor region or layer; whereas, when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, it is less conductive (more resistive) than that other semiconductor region or layer.

It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises,” “comprising,” “includes” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “under,” “below,” “underlying,” “over,” “overlying,” “parallel,” “perpendicular,” etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching,” “in direct contact,” “abutting,” “directly adjacent to,” “immediately adjacent to,” etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The descriptions of the various disclosed embodiments have been presented for purposes of illustration but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.