Metrology target simulation

This application claims priority of EP application 20215517.2 which was filed on Dec. 18, 2020 and which is incorporated herein in its entirety by reference.

The present invention relates to metrology target simulation. In particular, the present invention relates to a computer implemented method of simulating an electromagnetic response of a metrology target having a multi-layer structure.

A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus may, for example, project a pattern (also often referred to as “design layout” or “design”) at a patterning device (e.g., a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate (e.g., a wafer).

To project a pattern on a substrate a lithographic apparatus may use electromagnetic radiation. The wavelength of this radiation determines the minimum size of features which can be formed on the substrate. Typical wavelengths currently in use are 365 nm (i-line), 248 nm, 193 nm and 13.5 nm. A lithographic apparatus, which uses extreme ultraviolet (EUV) radiation, having a wavelength within the range 4-20 nm, for example 6.7 nm or 13.5 nm, may be used to form smaller features on a substrate than a lithographic apparatus which uses, for example, radiation with a wavelength of 193 nm.

Low-klithography may be used to process features with dimensions smaller than the classical resolution limit of a lithographic apparatus. In such process, the resolution formula may be expressed as CD=k×λ/NA, where, is the wavelength of radiation employed, NA is the numerical aperture of the projection optics in the lithographic apparatus, CD is the “critical dimension” (generally the smallest feature size printed, but in this case half-pitch) and kis an empirical resolution factor. In general, the smaller kthe more difficult it becomes to reproduce the pattern on the substrate that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps may be applied to the lithographic projection apparatus and/or design layout. These include, for example, but not limited to, optimization of NA, customized illumination schemes, use of phase shifting patterning devices, various optimization of the design layout such as optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET). Alternatively, tight control loops for controlling a stability of the lithographic apparatus may be used to improve reproduction of the pattern at low k1.

Semiconductor-based devices may be produced by fabricating a series of layers on a substrate (e.g., a wafer), some or all of the layers including various structures. The relative position of these structures within a single layer and with respect to structures in other layers plays a key role in the performance of the devices. Overlay error relates to the misalignment between various structures. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below it and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Overlay measurements are performed via metrology targets that are printed together with layers of the wafer. Images of the metrology targets are captured via an imaging tool and are analyzed to determine both X-overlay and Y-overlay measurements.

Known techniques exist to simulate an electromagnetic response of a metrology target in software before fabricating them onto a substrate. This simulation enables a designer to determine one or more parameters associated with the electromagnetic response of the metrology target and make changes to the design of the metrology target to optimize the one or more parameters.

Known techniques for simulating an electromagnetic response of a metrology target are typically applied to metrology targets comprising a multi-layer structure comprising an upper grating and a lower grating, wherein the grating lines of the upper grating and the lower grating have the same pitch. This involves rigorously simulating the electromagnetic response of the metrology target using Maxwell solvers, e.g. using Rigorous Coupled-Wave Analysis (RCWA), for various parameters of light incident on the metrology target and for different critical dimensions (CD) and pitches of the metrology target.

The inventor has identified that when the grating lines of the upper grating and the lower grating are not equal, i.e. have different pitches, the computational complexity of the simulation increases such that using known Maxwell solving techniques take a much greater length of time making the use of known Maxwell solving techniques for such a metrology target design impractical or sometimes even impossible.

According to one aspect of the present disclosure there is provided a computer implemented method of simulating an electromagnetic response of a metrology target having a multi-layer structure comprising a first grating and a second grating, wherein the second grating is below the first grating in the multi-layer structure, the method comprising: receiving a model representing the multi-layer structure, the model defining (i) the first grating as having a first predetermined number of grating lines within a pitch of the multi-layer structure, each of the first predetermined number of grating lines separated by a first pitch; and (ii) the second grating as having a second predetermined number of grating lines within the pitch of the multi-layer structure, each of the second predetermined number of grating lines separated by a second pitch; using the model and the first pitch to simulate the transmission and reflection properties of the first grating and generate a first scattering matrix associated with the first grating; using the model and the second pitch to simulate the transmission and reflection properties of the second grating and generate a second scattering matrix associated with the second grating; generating a scattering matrix defining the scattering and reflection properties of the multi-layer structure by combining the first scattering matrix and the second scattering matrix.

Embodiments of the present disclosure exploit “sparsity” in the Maxwell solver solution which is present when the first (upper) grating and the second (lower) grating are unequal, i.e. the first pitch and the second pitch are different. In particular, the computational resource needed to simulate the electromagnetic response of such a metrology target is minimized to thereby reduce the time taken to perform the simulation.

The method may comprise: using the model and the first pitch to simulate the transmission and reflection properties of the first grating to generate a first block-diagonal matrix associated with the first grating; and reordering the first block-diagonal matrix to generate the first scattering matrix associated with the first grating

The first block-diagonal matrix may comprise scattering matrices each defining the transmission and reflection properties of the first grating in response to simulating light being incident on an upper surface of the first grating at a respective angle of incidence and being incident on a lower surface of the first grating at a respective angle.

The first block-diagonal matrix may comprise the first predetermined number of scattering matrices.

The method may comprise: using the model and the second pitch to simulate the transmission and reflection properties of the second grating to generate a second block-diagonal matrix associated with the second grating; and reordering the second block-diagonal matrix to generate the second scattering matrix associated with the second grating.

The second block-diagonal matrix may comprise scattering matrices each defining the transmission and reflection properties of the second grating in response to simulating light being incident on an upper surface of the second grating at a respective angle of incidence.

The second block-diagonal matrix may comprise the second predetermined number of scattering matrices.

The first scattering matrix may comprise: (i) a first scattering matrix component defining the transmission properties of the first grating in response to simulating light being incident on an upper surface of the first grating, (ii) a second scattering matrix component defining the reflection properties of the first grating in response to simulating light being incident on an upper surface of the first grating, (iii) a third scattering matrix component defining the reflection properties of the first grating in response to simulating light being incident on a lower surface of the first grating, and (iv) a fourth scattering matrix component defining the transmission properties of the first grating in response to simulating light being incident on a lower surface of the first grating; wherein the second scattering matrix may comprise: (v) a fifth scattering matrix component defining the transmission properties of the second grating in response to simulating light being incident on an upper surface of the second grating, and (vi) a sixth scattering matrix component defining the reflection properties of the first grating in response to simulating light being incident on an upper surface of the second grating,

The combining of the first scattering matrix and the second scattering matrix may comprise performing a matrix inversion of a matrix obtained by subtracting the product of the third scattering matrix component and the sixth scattering matrix component from an identity matrix.

The combining the first scattering matrix and the second scattering matrix may comprise approximating a matrix inversion of a matrix obtained by subtracting the product of the third scattering matrix component and the sixth scattering matrix component from an identity matrix.

The approximating the matrix inversion may comprise using a geometric series or comprise using an iterative solver.

The scattering matrix defining the scattering and reflection properties of the multi-layer structure may be generated by the Redheffer product of the first scattering matrix and the second scattering matrix.

The method may further comprise determining one or more parameters associated with the electromagnetic response of the metrology target using the scattering matrix defining the transmission and reflection properties of the multi-layer structure.

In implementations, the first predetermined number of grating lines is greater than the second predetermined number of grating lines such that the first pitch is less than the second pitch.

In implementations, the first predetermined number of grating lines may be less than the second predetermined number of grating lines such that the first pitch is greater than the second pitch.

In implementations, the first predetermined number of grating lines are identical to each other, and the second predetermined number of grating lines are identical to each other.

According to one aspect of the present disclosure there is provided a computer implemented method of designing a metrology target for a semiconductor wafer, the metrology target having a multi-layer structure comprising a first grating and a second grating, wherein the second grating is below the first grating in the multi-layer structure, the method comprising: for each of a plurality of candidate metrology targets, performing the method of any preceding claim and determining one or more parameters associated with the electromagnetic response of the candidate metrology target using the scattering matrix of the candidate metrology target; identifying a candidate metrology target from said plurality of candidate metrology targets that optimizes said one or more parameters.

According to another aspect of the present disclosure there is provided a computing device comprising a processor and memory, the memory storing instructions which, when executed by the processor cause the computing device to perform the method steps described herein.

According to another aspect of the present disclosure there is provided a computer-readable storage medium comprising instructions which, when executed by a processor of a computing device cause the computing device to perform the method steps described herein.

The instructions may be provided on a carrier such as a disk, CD- or DVD-ROM, programmed memory such as read-only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier. Code (and/or data) to implement embodiments of the present disclosure may comprise source, object or executable code in a conventional programming language (interpreted or compiled) such as C, or assembly code, code for setting up or controlling an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array), or code for a hardware description language.

In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range of about 5-100 nm).

The term “reticle”, “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. The term “light valve” can also be used in this context. Besides the classic mask (transmissive or reflective, binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include a programmable mirror array and a programmable LCD array.

schematically depicts a lithographic apparatus LA. The lithographic apparatus LA includes an illumination system (also referred to as illuminator) IL configured to condition a radiation beam B (e.g., UV radiation, DUV radiation or EUV radiation), a mask support (e.g., a mask table) MT constructed to support a patterning device (e.g., a mask) MA and connected to a first positioner PM configured to accurately position the patterning device MA in accordance with certain parameters, a substrate support (e.g., a wafer table) WT constructed to hold a substrate (e.g., a resist coated wafer) W and connected to a second positioner PW configured to accurately position the substrate support in accordance with certain parameters, and a projection system (e.g., a refractive projection lens system) PS configured to project a pattern imparted to the radiation beam B by patterning device MA onto a target portion C (e.g., comprising one or more dies) of the substrate W.

In operation, the illumination system IL receives a radiation beam from a radiation source SO, e.g. via a beam delivery system BD. The illumination system IL may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, and/or other types of optical components, or any combination thereof, for directing, shaping, and/or controlling radiation. The illuminator IL may be used to condition the radiation beam B to have a desired spatial and angular intensity distribution in its cross section at a plane of the patterning device MA.

The term “projection system” PS used herein should be broadly interpreted as encompassing various types of projection system, including refractive, reflective, catadioptric, anamorphic, magnetic, electromagnetic and/or electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, and/or for other factors such as the use of an immersion liquid or the use of a vacuum. Any use of the term “projection lens” herein may be considered as synonymous with the more general term “projection system” PS.

The lithographic apparatus LA may be of a type wherein at least a portion of the substrate may be covered by a liquid having a relatively high refractive index, e.g., water, so as to fill a space between the projection system PS and the substrate W—which is also referred to as immersion lithography. More information on immersion techniques is given in U.S. Pat. No. 6,952,253, which is incorporated herein by reference.

The lithographic apparatus LA may also be of a type having two or more substrate supports WT (also named “dual stage”). In such “multiple stage” machine, the substrate supports WT may be used in parallel, and/or steps in preparation of a subsequent exposure of the substrate W may be carried out on the substrate W located on one of the substrate support WT while another substrate W on the other substrate support WT is being used for exposing a pattern on the other substrate W.

In addition to the substrate support WT, the lithographic apparatus LA may comprise a measurement stage. The measurement stage is arranged to hold a sensor and/or a cleaning device. The sensor may be arranged to measure a property of the projection system PS or a property of the radiation beam B. The measurement stage may hold multiple sensors. The cleaning device may be arranged to clean part of the lithographic apparatus, for example a part of the projection system PS or a part of a system that provides the immersion liquid. The measurement stage may move beneath the projection system PS when the substrate support WT is away from the projection system PS.

In operation, the radiation beam B is incident on the patterning device, e.g. mask, MA which is held on the mask support MT, and is patterned by the pattern (design layout) present on patterning device MA. Having traversed the mask MA, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W. With the aid of the second positioner PW and a position measurement system IF, the substrate support WT can be moved accurately, e.g., so as to position different target portions C in the path of the radiation beam B at a focused and aligned position. Similarly, the first positioner PM and possibly another position sensor (which is not explicitly depicted in) may be used to accurately position the patterning device MA with respect to the path of the radiation beam B. Patterning device MA and substrate W may be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2. Although the substrate alignment marks P1, P2 as illustrated occupy dedicated target portions, they may be located in spaces between target portions. Substrate alignment marks P1, P2 are known as scribe-lane alignment marks when these are located between the target portions C.

As shown inthe lithographic apparatus LA may form part of a lithographic cell LC, also sometimes referred to as a lithocell or (litho)cluster, which often also includes apparatus to perform pre- and post-exposure processes on a substrate W. Conventionally these include spin coaters SC to deposit resist layers, developers DE to develop exposed resist, chill plates CH and bake plates BK, e.g. for conditioning the temperature of substrates W e.g. for conditioning solvents in the resist layers. A substrate handler, or robot, RO picks up substrates W from input/output ports I/O1, I/O2, moves them between the different process apparatus and delivers the substrates W to the loading bay LB of the lithographic apparatus LA. The devices in the lithocell, which are often also collectively referred to as the track, are typically under the control of a track control unit TCU that in itself may be controlled by a supervisory control system SCS, which may also control the lithographic apparatus LA, e.g. via lithography control unit LACU.

In order for the substrates W exposed by the lithographic apparatus LA to be exposed correctly and consistently, it is desirable to inspect substrates to measure properties of patterned structures, such as overlay errors between subsequent layers, line thicknesses, critical dimensions (CD), etc. For this purpose, inspection tools (not shown) may be included in the lithocell LC. If errors are detected, adjustments, for example, may be made to exposures of subsequent substrates or to other processing steps that are to be performed on the substrates W, especially if the inspection is done before other substrates W of the same batch or lot are still to be exposed or processed.

An inspection apparatus, which may also be referred to as a metrology apparatus, is used to determine properties of the substrates W, and in particular, how properties of different substrates W vary or how properties associated with different layers of the same substrate W vary from layer to layer. The inspection apparatus may alternatively be constructed to identify defects on the substrate W and may, for example, be part of the lithocell LC, or may be integrated into the lithographic apparatus LA, or may even be a stand-alone device. The inspection apparatus may measure the properties on a latent image (image in a resist layer after the exposure), or on a semi-latent image (image in a resist layer after a post-exposure bake step PEB), or on a developed resist image (in which the exposed or unexposed parts of the resist have been removed), or even on an etched image (after a pattern transfer step such as etching).

Typically the patterning process in a lithographic apparatus LA is one of the most critical steps in the processing which requires high accuracy of dimensioning and placement of structures on the substrate W. To ensure this high accuracy, three systems may be combined in a so called “holistic” control environment as schematically depicted in. One of these systems is the lithographic apparatus LA which is (virtually) connected to a metrology tool MT (a second system) and to a computer system CL (a third system). The key of such “holistic” environment is to optimize the cooperation between these three systems to enhance the overall process window and provide tight control loops to ensure that the patterning performed by the lithographic apparatus LA stays within a process window. The process window defines a range of process parameters (e.g. dose, focus, overlay) within which a specific manufacturing process yields a defined result (e.g. a functional semiconductor device)—typically within which the process parameters in the lithographic process or patterning process are allowed to vary.

The computer system CL may use (part of) the design layout to be patterned to predict which resolution enhancement techniques to use and to perform computational lithography simulations and calculations to determine which mask layout and lithographic apparatus settings achieve the largest overall process window of the patterning process (depicted inby the double arrow in the first scale SC1). Typically, the resolution enhancement techniques are arranged to match the patterning possibilities of the lithographic apparatus LA. The computer system CL may also be used to detect where within the process window the lithographic apparatus LA is currently operating (e.g. using input from the metrology tool MT) to predict whether defects may be present due to e.g. sub-optimal processing (depicted inby the arrow pointing “0” in the second scale SC2).

The metrology tool MT may provide input to the computer system CL to enable accurate simulations and predictions, and may provide feedback to the lithographic apparatus LA to identify possible drifts, e.g. in a calibration status of the lithographic apparatus LA (depicted inby the multiple arrows in the third scale SC3).

A metrology target on the substrate W is used to determine the alignment of different layers of the same substrate W. Embodiments of the present disclosure relate to the software simulation of an electromagnetic response of a candidate metrology target as part of a design process for determining an optimal metrology target that is to be manufactured on a substrate W. The simulation method described herein is performed on a computing device. The computing devicemay be the same as, or a separate device to, the computer system CL.

illustrates a simplified view of the computing device. A shown in, the devicecomprises a central processing unit (“CPU”), to which is connected a memory. The functionality of the CPUdescribed herein may be implemented in code (software) stored on a memory (e.g. memory) comprising one or more storage media, and arranged for execution on a processor comprising on or more processing units. The storage media may be integrated into and/or separate from the CPU. The code is configured so as when fetched from the memory and executed on the processor to perform operations in line with embodiments discussed herein. Alternatively it is not excluded that some or all of the functionality of the CPUis implemented in dedicated hardware circuitry, or configurable hardware circuitry like an FPGA.

The computing devicecomprises an input deviceconfigured to enable a user to input data into a software program running on the CPUfor the simulation of an electromagnetic response of a candidate metrology target. The input devicemay comprise a mouse, keyboard, touchscreen, microphone etc. The computing devicefurther comprises an output deviceconfigured to output results of the simulation to the user. The output devicemay for example be a display (which may comprise a touchscreen) or a speaker.

schematically depicts a portionof a metrology target the electromagnetic response of which may be simulated by the software program running on the CPUin embodiments of the present disclosure.

As shown in, the portionof the metrology target comprises a top grating (also referred to herein as a first grating)on a first substrateand a bottom grating (also referred to herein as a second grating) on a second substrate, wherein the bottom grating is below the top grating. Whilst embodiments of the present disclosure are described with reference to the simulation of a metrology target comprising two gratings for simplicity, it will be appreciated that embodiments of the present disclosure extend to metrology targets having more than two layers of gratings.shows a gap between the first substrateand second substrate. It will be appreciated that the first substrate may extend down to the second substrate. Alternatively this gap may comprise one or more additional layers of material.