Flexible bit quantities for error correction code (ECC) values in a memory environment

This application is a continuation of and claims priority to U.S. Non-Provisional patent application Ser. No. 17/654,354, filed on 10 Mar. 2022, which in turn claims the benefit of U.S. Provisional Patent Application No. 63/162,139, filed 17 Mar. 2021, the disclosures of which are hereby incorporated by reference herein in their entireties.

Computers, smartphones, and other electronic devices rely on processors and memories. A processor executes code based on data to run applications and provide features to a user. The processor obtains the code and the data from a memory. The memory in an electronic device can include volatile memory (e.g., random access memory (RAM)) and nonvolatile memory (e.g., flash memory). Volatile memory can include static RAM (SRAM) and dynamic RAM (DRAM). Like the number of cores or speed of a processor, memory characteristics that vary by memory type can impact an electronic device's performance.

Memory demands in electronic devices continue to evolve and grow. For example, as manufacturers engineer processors to execute code faster, processors benefit from accessing memories more quickly. Applications on electronic devices may also operate on ever-larger data sets that require ever-larger memories. Further, manufacturers may seek physically smaller memories with smaller process technologies as the form factors of portable electronic devices continue to shrink. Accommodating these various demands is complicated by a growing demand to improve the accurate storing and retrieval of data by memories.

Overview

Processors and memory work in tandem to provide features on computers and other electronic devices, including smartphones. An electronic device can generally provide enhanced features, such as high-resolution graphics and artificial intelligence, as a processor-and-memory tandem operate faster. Advances in processors have often outpaced those in memory. As a result, memory can cause a bottleneck during execution due to the disparity in speed between processors and memory.

To counterbalance the faster operational speed of processors, computer engineers have developed several techniques to improve memory performance. One such technique involves accessing multiple memories in parallel. Manufacturers can design a memory device with multiple memory banks to enable parallel accessing. The memory device can access each memory bank in parallel with one or more other memory banks, multiplying the data-access rate. Consider that each memory bank of a four-banked memory device can read a byte of data substantially simultaneously. The four-banked memory device may then produce four bytes of data in the same time that a non-banked memory produces only one byte of data.

Access circuitry or logic associated with each memory bank can operate separately, at least in part, from the access circuitry of other memory banks to enable simultaneous data reading (e.g., extracting a byte of information from memory cells). As a result, the memory device may replicate access circuitry for each memory bank of multiple memory banks. Manufacturers of memory devices position the replicated access circuitry proximate to each memory bank to reduce data-reading latency. Co-locating access circuitry and memory banks, however, can constrain systems and techniques that are used for memory safety and reliability, including error correction and detection using error-correction-code (ECC) technology. This Overview further describes ECC technology after introducing example memory types.

There are multiple types of dynamic random-access memory (DRAM). As one example, low-power double data rate (DDR) memory, also referred to as LPDDR or mobile DDR, is a DDR synchronous DRAM (DDR SDRAM). LPDDR generally uses less power than other types of DDR SDRAM. In some applications, LPDDR memory may also operate at higher data rates than other DDR SDRAM types. Device manufacturers often use LPDDR memory in mobile devices, such as smartphones and tablet computers, to extend battery life. Cloud and web-services companies increasingly use LPDDR memory in server applications to reduce electricity usage and, therefore, lower operational costs across large data centers. Designing LPDDR for different use cases and applications, however, can be challenging.

Computer engineers can construct LPDDR memory with different data array topologies for different applications. Memory designs may improve power efficiency or area efficiency. Other design considerations may address the size and shape of the LPDDR memory. Some features supported by an LPDDR architecture, however, can restrict design flexibility by, for example, limiting available data array topologies, occupying additional die space, requiring additional on-die wiring or data paths, or requiring additional components or logic, such as additional or redundant ECC circuitry.

LPDDR memory may include various error-correction logic based on ECC techniques. For example, an ECC engine may generate an 8-bit ECC value for 128 bits of data, also referred to as a 128:8 ECC engine. The 128:8 ECC engine may be able to detect double-bit errors and correct single-bit errors. As another example, the error-correction logic may generate a 16-bit ECC value for a 256-bit data package and be capable of detecting larger bit errors or more reliably detecting double-bit errors. Using ECC technology can reduce the effects of data corruption and may improve memory and system performance. Generally, as the bit size of the ECC value increases, the error detection coverage in a memory device increases. Also, on-die error-correction logic can increase the reliability of DDR SDRAM, including LPDDR SDRAM.

Computer engineers can implement error-correction logic using ECC mechanisms with an ECC engine that determines ECC values on data portions (e.g., some quantity of bytes). As mobile devices become more powerful or provide more important services, memory reliability improvements become more critical to users, hardware designers, and application designers. Improved error correction capabilities, such as ECC values with larger bit sizes, can increase on-die error detection. This document describes techniques and systems to enable such more robust ECC data protection, including a configurable ECC logic shared among multiple memory banks of an LPDDR memory with a reduced die-area penalty while offering increased ECC protection.

As discussed above, multi-banked memory has evolved to include dedicated access circuitry per memory bank positioned proximate to each memory bank. The dedicated access circuitry may include sense amps, pre-charge circuits, column address circuitry, buffers, routing circuitry, and ECC circuitry. Engineers can include an ECC engine in the ECC circuitry for each respective memory bank in some approaches. Engineers may position one ECC “block” or contiguous die region between two memory banks in some chip layouts. The ECC block can include two ECC engines-one ECC engine per memory bank. With these approaches, an ECC engine is present for each memory bank, and each ECC engine uses 128:8 ECC technology to conserve die area. Compared to a 128:8 ECC engine, a 256:16 ECC engine can occupy significantly more die area (e.g., twice the die area). As a result, it may be impractical to provide 256:16 ECC engines positioned proximate to each memory bank of a memory array.

In other cases, a DDR architecture, protocol, or feature may adversely impact performance. For example, a masked-write command allows memory to write a group of bits (e.g., 64 bits) while masking some of the bits (e.g., 8 bits), which may be called the “masked bits.” The masked bits retain their previous value instead of being overwritten by the masked-write operation.

The internal read-modify-write operation can be considered an “atomic” operation formed of three operations. The operations may include reading existing data at a location and modifying the write data for the write command in light of the mask and the read data. As part of the read or modify operation, the memory may use ECC circuitry to detect or correct an error in the masked data. Placing an ECC engine near each memory bank can mitigate propagation delays for the data portion undergoing ECC processing. After the modifying, the internal read-modify-write operation writes the modified group of bits such that the masked data is unchanged. The atomic read-modify-write operation may also entail a second ECC determination for the modified group of bits that is being written.

Performing multiple access operations can cause timing constraints in the memory system because the internal read-modify-write operation can take longer than implementing a standard or non-masked write command. Further, additional control circuitry is employed to perform read-modify-write operations. Because of the timing constraints and the additional control circuitry, implementing the masked-write feature can involve providing at least one dedicated ECC engine for each memory bank of an LPDDR memory. The dedicated ECC engines consume valuable die space but may be important for LPDDR memory that supports data-masking functionality to lower latency to meet a given memory specification.

As indicated above, the portion of access-control circuitry for performing masked-write operations can be relatively large. This circuitry can reduce the area available for other control circuitry or additional memory capacity to improve device operation. For example, it can be challenging to add ECC circuitry that interacts with multiple memory banks due to chip layout limitations, which are exacerbated by enabling masked-write operations. Instead, a separate ECC engine is often built for each memory bank to reduce data paths among the memory banks. This approach, however, can introduce two drawbacks. First, computer engineers replicate an ECC engine in multiple locations, which wastes the limited chip die area. Second, because the ECC engine is replicated, it can be problematic from a cost or area perspective to utilize more-complex ECC engines.

To address these issues at least partially, this document describes other approaches in which ECC circuitry is configurable to use a shared ECC engine in conjunction with local ECC engines to provide higher data reliability. For example, the local ECC engines can provide 128:8 ECC functionality to the respective memory bank of a memory array. In this example, the shared ECC engine can provide 256:16 ECC functionality to two or more memory banks of the memory array and improved error detection relative to 128:8 ECC functionality. As another example, the shared ECC engine can use a portion of communicated data to improve detection of two-bit errors to the memory banks by using ECC values with a larger quantity of bits (e.g., 10, 12, 14, or 16 bits instead of 8 bits).

For example, a first ECC engine of the configurable ECC circuitry can correspond to a first memory bank of multiple memory banks and provide ECC determinations (e.g., computations) for data stored in the first memory bank. A second ECC engine can correspond to a second memory bank and provide ECC determinations for data stored in the second memory bank. A third ECC engine (e.g., a shared ECC engine) can correspond to the first memory bank and the second memory bank and provide ECC determinations for data stored in the first memory bank and for data stored in the second memory bank. In operation, the first ECC engine provides a first ECC value for the first memory bank. The second ECC engine provides a second ECC value for the second memory bank. The first ECC value and the second ECC value have a first quantity of bits. The shared ECC engine provides a third ECC value for at least one of the first memory bank or the second memory bank. The third ECC value has a second quantity of bits, which is larger than the first quantity. Using a shared ECC engine, ECC technology that uses ECC values with more bits than those of the local ECC engines can be employed in a memory device. With larger quantities of bits in the ECC values, higher levels of error detection or correction can be implemented to provide greater data reliability than per-memory-bank ECC approaches.

Accordingly, this document describes approaches for configurable ECC circuitry and schemes with better error coverage within a given die size. Many applications and use cases rarely employ the masked-write functionality. The memory device can include the shared ECC engine without incurring an appreciable die-area penalty by selectively disabling the masked-write functionality and utilizing global data lines. The shared ECC engine can use an ECC value with more bits than the local ECC engines because there are fewer instances of the larger shared ECC engine (e.g., as few as a single instance) as compared to multiple instances of the local ECC engines. In this way, the masked-write functionality can still be selectively available and supported by local ECC engines to meet latency targets, but the memory device can also provide better error coverage when the masked-write functionality is disabled by using the shared ECC engine.

The wiring that extends from multiple memory banks (e.g., for byte-mode functionality) can also couple to the shared ECC engine. Because the shared ECC engine does not need to be replicated across the die at each memory bank, configurable ECC circuitry can be implemented with greater error-detection coverage without an infeasible area penalty. The shared ECC engine can provide higher-order reliability by using ECC values with larger bit sizes. Therefore, memory devices can be “upgraded” from using ECC values of a first size (e.g., 8 bits) to using larger ECC values (e.g., 10-bit, 12-bit, 14-bit, or 16-bit) without appreciably increasing the die size or cost and without omitting masked-write functionality. In this way, the detectability of two-bit errors can increase to over ninety percent in some cases. Further, by using the shared ECC engine when the masked-write functionality is disabled, the memory device can avoid signal propagation delays between a memory bank and a shared ECC engine that might adversely impact a read-modify-write operation.

Thus, if masked-write commands and the corresponding internal read-modify-write operations are selectively disabled, the associated timing constraints or control complexity can be reduced or eliminated. In such situations, memory designers can more feasibly implement larger ECC values with an ECC engine shared across multiple memory banks in a memory device. Using the shared ECC engine can provide better error detection and increased data reliability relative to per-bank or dedicated ECC mechanisms that are used when masked-write functionality is enabled. Employing configurable ECC circuitry and schemes that can respond to the enabling or disabling of masked-write functionality suitable to a given application or use case can improve memory performance. Thus, flexibility in enabling masked-write functionality and the size of ECC values may improve the rate of data failure detections or corrections.

This document, therefore, describes memory device approaches that utilize configurable ECC circuitry and schemes. Local ECC engines may service respective memory banks on a given memory die with ECC values of a first size. An ECC engine shared across two or more memory banks may use ECC values of a second size, which is larger than the first size. For example, the shared ECC engine may service two or more memory banks on the given memory die using ECC values with larger second size. The memory device can improve error detection at least when masked-write functionality is disabled without an appreciable die area penalty. In these manners, the configurable ECC circuitry and schemes can increase data reliability, decrease die area that would otherwise be devoted to higher-order ECC functionality, increase chip-topology flexibility, or provide other features and benefits described herein.

Example Operating Environments

illustrates, atgenerally, an example apparatusthat can implement configurable error correction code (ECC) circuitry and schemes. The apparatuscan include various types of electronic devices, including an internet-of-things (IoT) device-, tablet device-, smartphone-, notebook computer-, passenger vehicle-, server computer-, server cluster-that may be part of cloud computing infrastructure or a data center, or a portion thereof (e.g., a printed circuit board (PCB)). Other examples of the apparatusinclude a wearable device (e.g., a smartwatch or intelligent glasses), entertainment device (e.g., a set-top box, video dongle, smart television, a gaming device), desktop computer, motherboard, server blade, consumer appliance, vehicle, drone, industrial equipment, security device, sensor, or the electronic components thereof. Each type of apparatus can include one or more components to provide computing functionalities or features.

In example implementations, the apparatuscan include at least one host device, at least one interconnect, at least one cache memory, and at least one memory device. The host devicecan include at least one processor, at least one cache memory, and at least one memory controller. The memory device, which can be also be a memory module, can include, for example, a dynamic random-access memory (DRAM) die or module (e.g., LPDDR SDRAM). The DRAM die or module can include a three-dimensional (3D) stacked DRAM device, which may be a high-bandwidth memory (HBM) device or a hybrid memory cube (HMC) device. The memory devicecan operate as a main memory for the apparatus. Although not illustrated, the apparatuscan also include storage memory. The storage memory can include, for example, a storage-class memory device (e.g., a flash memory, hard disk drive, solid-state drive, phase-change memory (PCM), or memory employing 3D XPoint™).

The processoris operatively coupled to the cache memory, which is operatively coupled to the memory controller. The processoris also coupled, directly or indirectly, to the memory controller. The host devicemay include other components to form, for instance, a system-on-a-chip (SoC). The processormay include a general-purpose processor, central processing unit (CPU), graphics processing unit (GPU), neural network engine or accelerator, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) integrated circuit (IC), or communications processor (e.g., a modem or baseband processor).

In operation, the memory controllercan provide a high-level or logical interface between the processorand at least one memory (e.g., an external memory). The memory controllercan, for example, receive memory requests from the processorand provide the memory requests to external memory with appropriate formatting, timing, and reordering. The memory controllercan also forward to the processorresponses to the memory requests received from external memory.

The host deviceis operatively coupled, via the interconnect, to the cache memory, which may be operatively coupled to the memory device. In some examples, the memory deviceis connected to the host devicevia the interconnectwithout an intervening buffer or cache, such as without the cache. The memory devicemay operatively couple to storage memory (not shown). The host devicecan also be coupled, directly or indirectly via the interconnect, to the memory deviceand the storage memory. The interconnectand other interconnects (not illustrated in) can transfer data between two or more components of the apparatus. Examples of the interconnectinclude a bus, switching fabric, or one or more wires that carry voltage or current signals.

The interconnectcan include at least one command and address bus(CA bus) and at least one data bus(DQ bus). Each bus may be a unidirectional or a bidirectional bus. The CA busand the DQ busmay couple to CA and DQ pins, respectively, of the memory device. In some implementations, the interconnectmay also include a chip-select (CS) I/O (not illustrated in) that can, for example, couple to one or more CS pins of the memory device. The interconnectmay also include a clock bus (CK bus—not illustrated in) that is part of or separate from the CA bus.

The illustrated components of the apparatusrepresent an example architecture with a hierarchical memory system. A hierarchical memory system may include memories at different levels, with each level having memory with a different speed or capacity. As illustrated, the cache memorylogically couples the processorto the cache memory. The cache memoriesandlogically couple the processorto the memory device. In the illustrated implementation, the cache memoryis at a higher level than the cache memory. Similarly, the cache memoryis at a higher level than the memory device. A storage memory, in turn, can be at a lower level than the main memory (e.g., the memory device). Memory at lower hierarchical levels may have a decreased speed but increased capacity relative to memory at higher hierarchical levels.

The apparatuscan be implemented in various manners with more, fewer, or different components. For example, the host devicemay include multiple cache memories (e.g., including multiple levels of cache memory) or no cache memory. In other implementations, the host devicemay omit the processoror the memory controller. A memory (e.g., the memory device) may have an “internal” or “local” cache memory. As another example, the apparatusmay not include cache memory between the interconnectand the memory device. Computer engineers can also include the illustrated components in distributed or shared memory systems.

Computer engineers may implement the host deviceand the various memories in multiple manners. In some cases, the host deviceand the memory devicecan be disposed on, or physically supported by, a PCB (e.g., a rigid or flexible motherboard). The host deviceand the memory devicemay additionally be integrated on an IC or fabricated on separate ICs packaged together. The memory devicemay also be coupled to multiple host devicesvia one or more interconnectsand may respond to memory requests from two or more host devices. Each host devicemay include a respective memory controller, or the multiple host devicesmay share a memory controller. This document describes an example computing system architecture with at least one host devicecoupled to the memory devicewith reference to.

Two or more memory components (e.g., modules, dies, banks, or bank groups) can share the electrical paths or couplings of the interconnect. In some implementations, the CA bustransmits addresses and commands from the memory controllerto the memory device, which may exclude propagating data. The DQ buscan propagate data between the memory controllerand the memory device. The memory devicemay include multiple memory banks (not illustrated in). The memory devicemay also be implemented as any suitable memory including, but not limited to, DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDR SDRAM).

The memory devicecan form at least part of the main memory of the apparatus. The memory devicemay, however, form at least part of a cache memory, a storage memory, or an SoC of the apparatus. As described further below, the architecture or protocol of the memory devicecan selectively enable or disable masked-write functionality or byte-mode functionality. The architecture or protocol of the memory devicecan also select the bit-size of ECC values in some implementations.

As illustrated in, the memory devicecan include configurable error correction code (ECC) circuitry, which may include multiple ECC engines (not illustrated in). The configurable ECC circuitry, or the ECC engines thereof, can be realized as hardware (e.g., logic) that implements an ECC algorithm or other mechanism. In some implementations, the configurable ECC circuitrycan include multiple portions, with each portion allocated to a respective memory bank or set of memory banks of the memory device. The configurable ECC circuitrycan also include a portion shared between two or more of the memory banks of the memory device. The configurable ECC circuitrycan perform error corrections, error detections, or both. The hardware or logic of the configurable ECC circuitrymay implement, for example, a double-error correction (DEC) Bose-Chaudhuri-Hocquenghem (BCH) code or a double-error-correcting and triple-error-detecting (DEC-TED) BCH code. Other ECC algorithms and mechanisms are described below.

illustrates an example computing systemthat can implement aspects of configurable ECC circuitry and schemes. In some implementations, the computing systemincludes at least one memory device, at least one interconnect, and at least one processor. The memory devicecan include, or be associated with, at least one memory array, at least one interface, and control circuitryoperatively coupled to the memory array. The memory devicecan correspond to one or more of the cache memoryor, the main memory, or a storage memory of the apparatusof. Thus, the memory arraycan include an array of memory cells, including but not limited to memory cells of DRAM, SDRAM, 3D-stacked DRAM, DDR memory, low-power DRAM, or LPDDR SDRAM. For example, the memory arraycan include memory cells of SDRAM configured as a memory module with one channel containing either 16 or 8 data (DQ) signals, double-data-rate input/output (I/O) signaling, and supporting a supply voltage of 0.3 to 0.5V. The density of the memory devicecan range, for instance, from 2 Gb to 32 Gb. The memory arrayand the control circuitrymay be components on a single semiconductor die or on separate semiconductor dies. The memory arrayor the control circuitrymay also be distributed across multiple dies.

The control circuitrycan include various components that the memory devicecan use to perform various operations. These operations can include communicating with other devices, managing memory performance, and performing memory read or write operations. For example, the control circuitrycan include one or more registers, at least one instance of array control logic, clock circuitry, and the configurable ECC circuitry. The registersmay be implemented, for example, as one or more registers (e.g., a masked-write enablement register) that can store information to be used by the control circuitryor another part of the memory device. The array control logiccan be circuitry that provides command decoding, address decoding, input/output functions, amplification circuitry, power supply management, power control modes, and other functions. The clock circuitrycan synchronize various memory components with one or more external clock signals provided over the interconnect, including a command/address clock (e.g., CK_t or CK_c) or a data clock (e.g., WCK_t or WCK_c). The clock circuitrycan also use an internal clock signal to synchronize memory components.

The interfacecan couple the control circuitryor the memory arraydirectly or indirectly to the interconnect. As shown in, the registers, the array control logic, the configurable ECC circuitry, and the clock circuitrycan be part of a single component (e.g., the control circuitry). In other implementations, one or more of the registers, the array control logic, the configurable ECC circuitry, or the clock circuitrymay be separate components on a single semiconductor die or across multiple semiconductor dies. These components may individually or jointly couple to the interconnectvia the interface.

The interconnectmay use one or more of a variety of interconnects that communicatively couple together various components and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between the memory deviceand the processor). Although the interconnectis illustrated with a single line in, the interconnectmay include at least one bus, at least one switching fabric, one or more wires or traces that carry voltage or current signals, at least one switch, one or more buffers, and so forth. Further, the interconnectmay be separated into at least a CA busand a DQ bus(as illustrated in).

In some aspects, the memory devicemay be a “separate” component relative to the host device(of) or any of the processors. The separate components can include a PCB, memory card, memory stick, and memory module (e.g., a single in-line memory module (SIMM) or dual in-line memory module (DIMM)). Thus, separate physical components may be located together within the same housing of an electronic device or may be distributed over a server rack, a data center, and so forth. Alternatively, the memory devicemay be integrated with other physical components, including the host deviceor the processor, by being combined on a PCB or in a single package or an SoC.

The designed apparatuses and methods may be appropriate for memory designed for lower-power operations or energy-efficient applications. An example of a memory standard related to low-power applications is the LPDDR standard for SDRAM as promulgated by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association. In this document, some terminology may draw from one or more of these standards or versions thereof, like the LPDDR5 standard, for clarity. The described principles, however, are also applicable to memories that comport with other standards, including other LPDDR standards (e.g., earlier versions or future versions like LPDDR6) and to memories that do not adhere to a standard.

As shown in, the processorsmay include a computer processor-, a baseband processor-, and an application processor-, coupled to the memory devicethrough the interconnect. The processorsmay include or form a part of a CPU, GPU, SoC, ASIC, or FPGA. In some cases, a single processor can comprise multiple processing resources, each dedicated to different functions (e.g., modem management, applications, graphics, central processing). In some implementations, the baseband processor-may include or be coupled to a modem (not illustrated in) and referred to as a modem processor. The modem or the baseband processor-may be coupled wirelessly to a network via, for example, cellular, Wi-Fi®, Bluetooth®, near field, or another technology or protocol for wireless communication.

In some implementations, the processorsmay be connected directly to the memory device(e.g., via the interconnect). In other implementations, one or more of the processorsmay be indirectly connected to the memory device(e.g., over a network connection or through one or more other devices). Further, the processormay be realized similar to the processorof. Accordingly, a respective processorcan include or be associated with a respective memory controller, like the memory controllerillustrated in. Alternatively, two or more processorsmay access the memory deviceusing a shared memory controller.

The configurable ECC circuitrycan provide ECC functionality for data stored in the memory array. The configurable ECC circuitrycan determine an ECC value for storage as part of a write operation or for comparison with a stored ECC value as part of a read operation. Example operations of the configurable ECC circuitryare described below with reference to. Example implementations in which the memory arrayincludes multiple memory banks are presented below with reference to. Example architectures for internal data buses are described with reference to. Example hardware realizations of a memory deviceare described next with reference to.

Example Techniques and Hardware

illustrates an example memory device. An example memory moduleincludes multiple dies. As illustrated, the memory moduleincludes a first die-, a second die-, a third die-, and a Ddie-D, with “D” representing a positive integer. As a few examples, the memory modulecan be a SIMM or a DIMM. The memory deviceillustrated incan correspond, for example, to a single die, multiple dies-through-D, or a memory modulewith at least one die. As shown, the memory modulecan include one or more electrical contacts(e.g., pins) to interface the memory moduleto other components.

The memory modulecan be implemented in various manners. For example, the memory modulemay include a PCB, and the multiple dies-through-D may be mounted or otherwise attached to the PCB. The dies(e.g., memory dies) may be arranged in a line or along two or more dimensions (e.g., forming a grid or array). The diesmay have a similar size or may have different sizes. Each diemay be similar to another dieor unique in size, shape, data capacity, or control circuitries. The diesmay also be positioned on a single side or on multiple sides of the memory module.

illustrates an example architectureof a memory devicethat includes configurable ECC circuitrycoupled to a memory arraythat includes multiple memory banks. The multiple memory bankscan include two, three, four, or more memory banks. As shown, the memory arrayincludes a first memory bank-, a second memory bank-, a third memory bank-, and a “B” memory bank-B, with “B” representing a positive integer greater than one (e.g., B≥2).

The memory deviceincludes an interfacethat operatively couples to a masked-write enablement register, the memory array, and the configurable ECC circuitry. The masked-write enablement registercan, for example, couple the interfaceto the configurable ECC circuitry. In other examples, the masked-write enablement registerand the configurable ECC circuitrycan couple in parallel to the interface. The configurable ECC circuitrycan also couple the interfaceto the memory arrayfor ECC functions.

The memory devicecan permit masked-write functionality to be selectively enabled or disabled using the masked-write enablement register. As described above, the memory devicemay implement the masked-write command using an internal read-modify-write operation. In some environments, the memory devicemay complete a write command within one tCCD (minimum column-to-column command delay time). A masked-write command, in contrast, can consume or occupy four tCCDs because the command comprises an atomic command that may be completed using read, modify, and write commands. This four-unit tCCD duration corresponds to ECC circuitry (e.g., the ECC engines) positioned proximate to the memory bank (not explicitly shown in). There is, therefore, a relatively small propagation delay between the read-modify-write circuitry at the memory bankand the respective local ECC enginedue to the physical proximity.