Silicon carbide MOSFET transistor device with improved characteristics and corresponding manufacturing process

The present disclosure relates to a silicon carbide MOSFET transistor device with improved characteristics and to a corresponding manufacturing process.

Electronic semiconductor devices are known, in particular MOSFET transistors (Metal-Oxide-Semiconductor Field-Effect Transistors), for example, for electronic power applications, which are made starting from a silicon carbide substrate.

The above devices prove advantageous thanks to the favorable chemico-physical properties of silicon carbide. For instance, silicon carbide generally has a wider bandgap than silicon, which is commonly used in electronic devices. Consequently, even with relatively small thicknesses, silicon carbide has a higher breakdown voltage than silicon and may thus be advantageously used in high-voltage, high-power and high-temperature applications.

In particular, thanks to its crystalline quality and to its large-scale availability, silicon carbide with hexagonal polytype (4H-SiC) can be used for electronic power applications.

Manufacturing of a silicon carbide semiconductor device is, however, affected by some problems.

For instance, problems of crystallographic quality of silicon carbide may represent an obstacle to obtaining a high production yield, which may in general prove lower than those of similar devices made starting from silicon, consequently causing an increase in the production costs.

In particular, it has been shown that reliability problems are linked to high electrical fields developing at the interfaces between silicon oxide (SiO) and silicon carbide (4H-SiC).

shows a portion of a basic or elementary structure (a so-called cell), of a MOSFET device of a vertical type, in particular an N-channel VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor) device, for power applications, designated by 1 and comprising: a substrate of semiconductor material (in particular, silicon carbide 4H-SiC), which is heavily doped (for example, with N-type doping, with high doping concentration, for instance higher than 10atoms/cm), not illustrated herein, and an epitaxial layer (referred to as drift layer), also made of silicon carbide, having the same conductivity type as, and overlying, the substrate, with a lower dopant concentration (N). The substrate operates as drain for the MOSFET device, and the epitaxial layerconstitutes a surface extension thereof defining a top surface

Each cell of the MOSFET devicecomprises a body wellhaving a conductivity opposite to that of the epitaxial layer(in the example, of a P type), and a source region, arranged within the body wellat the top surface, having the same conductivity type as the substrateand a high dopant concentration (N).

The surface portion of the epitaxial layer, arranged at the top surfaceand interposed between adjacent body wells, is commonly referred to as JFET region.

The devicefurther comprises a gate structure, constituted by a gate dielectric region, for example, of silicon oxide, formed on the JFET region and partially overlapping the body welland the source region; and a gate electrodeprovided on the gate dielectric region.

A dielectric material region, for example, of field oxide, overlies the gate electrode; an electrical-contact regionis defined through this dielectric material region, designed to contact a surface portion of the source region.

A source metallizationis arranged in contact with the aforesaid electrical-contact region; moreover, in a way not illustrated, a drain metallization contacts the substrate from the back and gate metallizations, provided within contact openings provided through the dielectric material region, contact the gate electrodes.

The channel of each cell of the MOSFET deviceis formed in the portion of the corresponding body wellset directly underneath the gate electrode, and is delimited by the junction between the source regionand the body wellon one side, and by the junction between the same body welland the JFET region, on the other side.

The gate electrodeis capacitively coupled to the channel to modulate the conductivity type thereof; in particular, application of an appropriate voltage to the gate electrodeallows to cause channel inversion and thus create a conductive path for the electrons between the source region(first current-conduction region of the device) and the substrate (second current-conduction region of the device), through the channel and the drift layer.

A problem afflicting silicon carbide MOSFET devices is linked to the increase in the electrical field on account of the possible crystallographic defects, with the electrical field that tends to increase in the insulating material, in particular in the gate dielectric regionat the central part of the JFET region, especially in reverse-biasing configuration.

shows the trend of the electrical field, designated by E, within the dielectric material in the above defined region. The increase of the electrical field in the central area of the JFET region is clear, where it may even assume levels such as to cause dielectric breakdown and thus jeopardize the reliability of the MOSFET device.

Known solutions for overcoming the aforesaid problem envisage a reduction of the electrical field at the interface between the silicon carbide and the gate dielectric region by one or more of the following approaches: an increase in the thickness of the epitaxial layer (drift layer); a reduction of the doping of the epitaxial layer; and a reduction of the distance between adjacent body wells and therefore of the width of the JFET region.

The above solutions do not, however, prove altogether satisfactory in so far as they generally envisage an undesired increase in the on-resistance of the MOSFET device and moreover have a non-negligible impact on the cost and efficiency of the manufacturing process.

The present disclosure provides various embodiments which solve or at least partially solve or overcome one or more of the problems highlighted above.

According to the present disclosure, a silicon carbide MOSFET transistor device and a corresponding manufacturing process are consequently provided.

In at least one embodiment, a MOSFET transistor device is provided that includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of said functional layer, and each of the gate structures includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within said functional layer, and the body wells are separated from one another by surface-separation regions of said functional layer. Source regions having said first conductivity type are formed within said body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions of said functional layer, underneath respective gate structures. The modified-doping regions have a modified concentration of dopant as compared to the concentration of the functional layer.

In at least one embodiment, a process for manufacturing a MOSFET transistor device is provided that includes: forming a functional layer of silicon carbide, having a first conductivity type; forming gate structures on a top surface of said functional layer, each of the gate structures including a dielectric region and an electrode region; forming body wells having a second conductivity type, within said functional layer, the body wells separated from one another by surface-separation regions of said functional layer; forming source regions having said first conductivity type, within said body wells, laterally and partially underneath respective gate structures; and forming modified-doping regions, arranged in the surface-separation regions of said functional layer, underneath respective gate structures, said modified-doping regions having a modified concentration of dopant as compared to the concentration of the functional layer.

As will be described in detail in what follows, an aspect of the present solution envisages a reduction of the electrical field in the gate dielectric region, in particular in reverse-biasing conditions, by introducing a modified-doping region in the JFET region of the MOSFET device (the latter being in particular a 4H-SiC polytype silicon carbide power MOSFET transistor). The modified-doping region is a region having a net concentration of dopant reduced as compared to the concentration of the epitaxial layer in which the JFET region is provided.

shows a MOSFET device, in particular an N-channel vertical transistor for high-power application.

The MOSFET deviceis provided in a die of semiconductor material, in particular of silicon carbide (more in particular of a 4H-SiC polytype), and comprises a substrate (or structural layer), which is heavily doped (with doping of an Ntype), and a functional layer, arranged on the substrateand having the same conductivity type as the substrateand a lower concentration (for example, with a doping of an Ntype). The functional layer, having a top surface, is, for example, grown using an epitaxial technique on the substrate, and provides, together with the substrate, the drain of the MOSFET device(i.e., a first current-conduction region of the same device); in particular, this functional layerdefines the so-called drift layer of the MOSFET device. A drain contact (here not illustrated), of an appropriate conductive material, is coupled underneath the substrate(i.e., on the side opposite to the functional layeralong a vertical direction z).

A plurality of functional units or cells of the MOSFET deviceare formed within an active area of the functional layer; these cells may, for example, have a generally strip-like extension in a longitudinal direction y (in a direction orthogonal to the transverse direction x of the cross-section ofand to the aforesaid vertical direction z, which corresponds to the thickness of the MOSFET device).

Each functional unit comprises a body wellhaving a conductivity opposite to that of the functional layer(in the example, of a Ptype), and a source region, arranged within the body wellat the top surface, having the same conductivity type as the substrate(and high concentration, in the example with doping of an Ntype) and defining a second current-conduction region of the same device. Each body welland source regionare shared, in the example, by two contiguous functional units of the MOSFET device.

A drain region, having the same conductivity type as the body wellsand high doping (in the example of a Ptype), is moreover arranged within one or more of the same body wellsat the top surfaceof the functional layer.

An inter-cell or JFET regioncorresponds to the portion of the functional layerarranged between two adjacent body wells(in the horizontal direction, in the example along the transverse direction x) and between the top surfaceof the functional layerand the depth of the body wells(in the vertical direction z).

Each functional unit further comprises a gate structure, arranged on the top surface, overlapping the JFET regionand partially the body welland the source region, in particular, being arranged on top of the channel region of the body well(this channel region being delimited by the junction between the source regionand the body wellon one side, and by the junction between the body welland the JFET region, on the other side). In the example, the gate structureis shared by two adjacent cells of the MOSFET device.

In greater detail, the gate structure, which has, for example, a strip-like conformation along the longitudinal direction y, comprises a gate dielectric region, including, for example, silicon oxide (SiO) and arranged on the front surfaceof the functional layer, and a gate electrode region, overlapping the gate dielectric regionand having substantially a same transverse dimensions as the same gate dielectric region.

A passivation layer, of a dielectric material, is arranged on the gate structures, and source-contact openings, at the underlying source regions, and body-contact openings, at the underlying drain regions, are defined through the same passivation layer. Electrical-contact regionsare arranged in the aforesaid source-contact openingsand body-contact openings, providing an electrical contact, of an Ohmic type, to the underlying source regionsand, respectively, drain regions.

The MOSFET devicefurther comprises a source-metallization layer, of a conformable type, for example, including Aluminium, arranged on the passivation layerin the entire active area and in particular provided within the source-contact openingsand the body-contact openingsso as to contact the respective electrical-contact regionsand, consequently, the source regionsand drain regions.

In a way not illustrated, further electrical-contact regions are provided on the front, for electrical connection to the gate electrodes, which also extend through the passivation layer, and on the back, for electrical connection to the drain contact.

According to a particular aspect of the present solution, the MOSFET devicefurther comprises modified-doping regions, arranged within the surface portions of the functional layerthat separate adjacent body wells, i.e., within the JFET regions, at the top surface, underneath respective gate structures, in particular underneath the corresponding gate dielectric regions.

The aforesaid modified-doping regions, in the embodiment illustrated, are arranged centrally with respect to the respective JFET regions; alternatively, as will be discussed and illustrated hereinafter, the same modified-doping regionscan extend transversally throughout the whole width of the respective JFET regions, terminating at the body wellsof the respective adjacent cells.

Furthermore, the aforesaid modified-doping regionshave a thickness, in the vertical direction z, smaller with respect to the thickness of the body wells(i.e., with respect to the position along the vertical direction z of the body junctions between the same body wellsand the functional layer); the aforesaid thickness of the modified-doping regionsmay be comprised between 10% and 50% of the thickness of the body wells.

In detail, the modified-doping regionshave the same conductivity type as the functional layerand a net concentration of dopant reduced as compared to the concentration of the same functional layer. In particular, the doping concentration of the modified-doping regionsis comprised between 5% and 50%, for example, it is equal to 20%, of the doping concentration of the functional layer.

As will be discussed hereinafter, the aforesaid modified-doping regionsmay be obtained by localized and partial deactivation of the N-type doping of the functional layer, in particular through localized implantations. This localized implantations may have an opposite conductivity type (of a P type), for example, with aluminium atoms or some other appropriate material, which provide a localized counter-doping for the functional layer; or they can cause localized damage to the functional layer.

Alternatively, the modified-doping regionsmay be obtained by dedicated growth of an epitaxial layer, with suitable and specific doping, at the top surfaceof the functional layer.

In any case, the presence of the aforesaid modified-doping regions, arranged underneath the gate structuresand within the JFET regions, enables reduction of the electrical field in the corresponding gate dielectric regions, in particular in conditions of reverse-biasing of the MOSFET device.

In this regard,shows with a continuous line the trend, along the transverse direction, of the electrical field within the gate dielectric regionsin the presence of the modified-doping regions; represented, instead, with a dashed line, for the purposes of a comparison provided by way of example, is the trend of the electrical field in the same gate dielectric regionsin a traditional solution, where the modified-doping regionsare not present. From an examination of the two trends, the reduction of the electrical field in the JFET region(highlighted by the circular box) is evident; advantageously, this reduction is sufficient to prevent dielectric breakdown and thus safeguards reliability of the MOSFET device.

It is underlined that the present Applicant has shown that the beneficial effect of reduction of the electrical field does not involve any substantial modification of the breakdown characteristics of the MOSFET device, the values of breakdown voltage and threshold voltage being in fact substantially unaltered. In other words, the reduction of the electrical field may be obtained with the breakdown voltage value and the threshold voltage value of the MOSFET devicebeing unchanged.

In addition, it is pointed out that it is sufficient to reduce the electrical field even by a small amount (for example, not higher than 10%) to guarantee a significant increase in the reliability of the MOSFET device. This is particularly important in so far as an excessive decrease in the electrical field could lead to an undesired increase of the on-state resistance (Ron) of the MOSFET device. It is thus possible to achieve in any case a good compromise between the beneficial effect of the reduction of the electrical field and the undesired increase of the on-state resistance.

Possible processes for manufacturing the MOSFET device, with particular regard to the formation of the aforesaid modified-doping regions, are now discussed.

In a first embodiment, the modified-doping regionsare obtained by an appropriate localized implantation carried out in the JFET regionsof the MOSFET device, aimed at partial deactivation of the N-type doping of the functional layerof the same MOSFET device.

As shown in, the manufacturing process first envisages, in a per se known manner, the formation of: the body wellsin the functional layer, by implantation of dopant atoms of a P type (for example, aluminium atoms); the source regionswithin the same body wells, by a respective implantation of dopant atoms of an N type (for example, phosphorus atoms); and the drain regionswithin one or more of the body wellsat the top surfaceof the functional layer, by a respective implantation of dopant atoms of a P type with a high doping dose.

Next,, according to an aspect of the present solution, the modified-doping regionsare provided by implantation of a P type (for example, with aluminium or boron atoms) in the JFET regionsbetween adjacent body wells; this implantation, with dopant atoms having a conductivity opposite to the conductivity of the functional layer(in this case, being of an N type) performs a counter-doping and therefore a partial deactivation of the doping of the functional layer, thus leading to formation of the modified-doping regions, with reduced net doping concentration.

After thermal activation of the dopants, the process proceeds in a per se known manner, with the formation of the gate structureson the functional layer(by deposition and subsequent definition of a dielectric layer and of a metal layer for the formation of the gate dielectric regionsand of the gate electrodesand then by deposition of the passivation layer). Moreover, the electrical-contact regionsare formed (on the front and on the back) to provide the source, gate and drain contacts, and then the source-metallization layeris formed (thus defining the structure illustrated previously with reference to).