Integrated circuit and manufacturing method thereof

This application claims the benefit of U.S. provisional application Ser. No. 63/430,439, filed Dec. 6, 2022, the subject matter of which is incorporated herein by reference.

An integrated circuit is an electronic component that utilizes the electronic properties of semiconductor materials to affect electrons or their associated fields. One widely used type of integrated circuit is the field-effect transistor (FET). However, parasitic impedance may exist in these semiconductor materials and it will negatively affect the performance of the integrated circuit.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Referring to,illustrates a schematic diagram of an integrated circuitaccording to an embodiment of the present disclosure,illustrates a schematic diagram of a view of the vertical local interconnectionofin +Y axis,illustrates an equivalent circuit diagram of the integrated circuitof,illustrates a schematic diagram of a top view of the integrated circuitof, andillustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-′. The integrated circuitis, for example, CFET (complementary FET) device. In the present disclosure, the integrated circuitis a logic circuit, for example, an AOI (AND-OR-INVERTOR) logic circuit; however, such exemplification is not meant to be for limiting.

As illustrated in, the integrated circuitincludes a plurality of transistorsand a vertical local interconnection. The transistorsinclude a plurality of gate components, a plurality of front-side source/drain epitaxiesand a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxiesare closer to a front-side FS of the integrated circuitthan the back-side source/drain epitaxies. The vertical local interconnectionconnects a first connected-oneAC of the front-side source/drain epitaxieswith a second connected-oneCD of the back-side source/drain epitaxy. A covered-oneC of the gate componentsis located between the first connected-oneAC and the second connected-oneCD, the covered-oneC includes a front-side portionC, a back-side portionCand a covered portionCconnecting the front-side portionCwith the back-side portionC, and the vertical local interconnectioncrosses the covered portionCand exposes the front-side portionCand the back-side portionC. As a result, it could reduce the parasitic capacitance of gate-to-drain and accordingly increase the oscillation frequency (response speed) of the integrated circuit. In comparison to the conventional integrated circuit, the integrated circuitmay increase the oscillation frequency by at least 3%.

As illustrated in, due to the structure of the vertical local interconnectionof the present embodiment, the overlapping area of the vertical local interconnectionoverlapping to the gate componentin Y-axis may be reduced, and accordingly the parasitic capacitance of gate-to-drain may be reduced.

As illustrated in, the vertical local interconnectionmay be formed of a material including, for example, a metal such as Cu, Co, Ru, W, etc. The vertical local interconnectionmay be shaped as a Z-shape, etc. For example, the vertical local interconnectionincludes a first notchR, a second notchR, a first lateral surface, a second lateral surfaceopposite to the first lateral surface, a front-side surfaceand a back-side surfaceopposite to the front-side surface. The first notchRextends toward a first-one of the first lateral surfaceand the second lateral surfacefrom a second-one of the first lateral surfaceand the second lateral surface. The first notchRextends toward a third-one of the front-side surfaceand the back-side surfacefrom a fourth-one of the front-side surfaceand the back-side surface. Although not illustrated, the first notchRmay be filled up with a dielectric material.

As illustrated in, the second notchRextends toward the second-one of the first lateral surfaceand the second lateral surfacefrom the first-one of the first lateral surfaceand the second lateral surface. The second notchRextends toward the fourth-one of the front-side surfaceand the back-side surfacefrom the third-one of the front-side surfaceand the back-side surface. Although not illustrated, the second notchRmay be filled up with a dielectric material.

As illustrated in, the vertical local interconnectionincludes a first portion, a second portionand a third portionconnecting the first portionwith the second portion. The third portionprojected on the vertical local interconnectionin −Y axis overlaps the covered portionCof the gate componentC. In another embodiment, a portion of the first portionand/or a portion of the second portionmay overlap the covered portionCin −Y axis.

As illustrated in, the first portionhas a first height Hranging between, for example, 10 nanometers (nm) to 100 nm, the second portionhas a second height Hranging between, for example, 10 nm to 100 nm, and the third portionhas a second height Hranging between, for example, 10 nm to 100 nm. In addition, the first portionhas a first width Lranging between, for example, 40 nm to 1000 nm, and the second portionhas a second width Lranging between, for example, 40 nm to 1000 nm. In addition, the vertical local interconnectionhas a thickness Wranging between, for example, 5 nm to 20 nm.

As illustrated in, the gate componentsinclude a gate componentA, a gate componentB, a gate componentC and a gate componentD. The front-side source/drain epitaxiesinclude a front-side source/drain epitaxyAB, the front-side source/drain epitaxyAC, a front-side source/drain epitaxyB, a front-side source/drain epitaxyCD and a front-side source/drain epitaxyD. The back-side source/drain epitaxiesinclude a back-side epitaxyAB, a back-side epitaxyAC, a back-side epitaxyB, the back-side epitaxyCD and a back-side epitaxyD.

As illustrated in, the equivalent circuit of the integrated circuitincludes eight transistors, such as a transistor AP, a transistor BP, a transistor CP and a transistor DP, a transistor AN, a transistor BN, a transistor CN and a transistor DN. The transistor AP includes a gate AP_G, a source AP_S and a drain AP_D, the transistor BP includes a gate BP_G, a source BP_S and a drain BP_D, the transistor CP includes a gate CP_G, a source CP_S and a drain CP_D, the transistor DP includes a gate DP_G, a source DP_S and a drain DP_D, the transistor AN includes a gate AN_G, a source AN_S and a drain AN_D, the transistor BN includes a gate BN_G, a source BN_S and a drain BN_D, the transistor CN includes a gate CN_G, a source CN_S and a drain CN_D, the transistor DN includes a gate DN_G, a source DN_S and a drain DN_D. The integrated circuitincludes eight inputs, such as the gate AP_G, the gate AN_G, the gate BP_G, the gate BN_G, the gate CP_G, the gate CN_G, the gate DP_G and the gate DN_G.

As illustrated in, the front-side source/drain epitaxiesare, for example, NMOS, while the back-side source/drain epitaxiesare, for example, PMOS. The gate componentA is corresponding to the gate AP_G and the gate AN_G, the gate componentB is corresponding to the gate BP_G and the gate BN_G, the gate componentC is corresponding to the gate CP_G and the gate CN_G, and the gate componentD is corresponding to the gate DP_G and the gate DN_G, wherein the gate AP_G of the transistor AP and the gate AN_G of the transistor AN share the gate componentA, the gate BP_G of the transistor BP and the gate BN_G of the transistor BN share the gate componentB, the gate CP_G of the transistor CP and the gate CN_G of the transistor CN share the gate componentC, and the gate DP_G of the transistor DP and the gate DN_G of the transistor DN share the gate componentD.

A source/drain of a transistor and a source/drain of another transistor may share a source/drain epitaxy.

As illustrated in, the source AN_S of the transistor AN and the drain BN_D the transistor BN share the front-side source/drain epitaxyAB, and the source CN_S of the transistor CN and the drain DN_D of the transistor DN share the front-side source/drain epitaxyCD. A NMOS and a PMOS share the first connected-one, and the first connected-one is drain epitaxy. For example, the drain AN_D of the transistor AN and the drain CP_D of the transistor CP share the front-side source/drain epitaxyAC (for example, the first connected-one).

As illustrated in, the source AP_S of the transistor AP and the source BP_S of the transistor BP share the back-side source/drain epitaxyAB, and the drain AP_D of the transistor AP and the source CP_S of the transistor CP share the back-side source/drain epitaxyAC. A NMOS and a PMOS share the second connected-one, and the second connected-one is drain epitaxy. For example, the drain CP_D of the of the transistor CP and the drain CN_D of the of the transistor CN share the back-side source/drain epitaxyCD (for example, the second connected-one).

As illustrated in, the vertical local interconnectionconnects the first connected-one and the second connected-one in parallel. The integrated circuitfurther includes an output node ZN coupled to the drain CP_D of the transistor CP, the drain AN_D of the transistor AN, the drain DP_D of the transistor DP and the drain CN_D of the transistor CN. Furthermore, as illustrated in, the front-side source/drain epitaxyAC (the first connected-one, corresponding to the drain CP_D of the transistor CP and the drain AN_D of the transistor AN) and the back-side source/drain epitaxyCD (the second connected-one, corresponding to the drain DP_D of the transistor DP and the drain CN_D of the transistor CN) are connected through the vertical local interconnection.

As illustrated in, the integrated circuitfurther includes a plurality of front-side conductive segmentsA,B,C andD, and a plurality of front-side conductive viasA,B,C andD. The front-side conductive viaA connects the front-side conductive segmentsA and the gate componentB, the front-side conductive viaB connects the front-side conductive segmentsB and the gate componentA, the front-side conductive viaC connects the front-side conductive segmentsC and the gate componentC, and the front-side conductive viaD connects the front-side conductive segmentsD and the gate componentD.

As illustrated in, the source BN_S of the transistor BN and the source DN_S of the transistor DN are electrically coupled to a voltage V. For example, as illustrated in, the integrated circuitfurther includes at least one front-side conductive segment, at least one front-side conductive viaB and at least one front-side conductive viaD. The front-side conductive viaB connects the front-side conductive segmentand the front-side source/drain epitaxyB, and the front-side conductive viaD connects the front-side conductive segmentand the front-side source/drain epitaxyD. The front-side source/drain epitaxyB (corresponding to the source BN_S of the transistor BN) and the front-side source/drain epitaxyD (corresponding to the source DN_S of the transistor DN) are electrically coupled to the voltage Vthrough the front-side conductive segment.

As illustrated in, the drain AP_D of the transistor AP, the drain CP_S of the transistor CP, the drain BP_D of the transistor BP and the drain DP_S of the transistor DP are electrically coupled. For example, as illustrated in, the integrated circuitfurther includes at least one back-side conductive segments, and a plurality of back-side conductive viasA,B andC. The back-side conductive viaA connects the back-side conductive segmentand the back-side source/drain epitaxyB, the back-side conductive viaB connects the back-side conductive segmentand the back-side source/drain epitaxyAC, and the back-side conductive viaC connects the back-side conductive segmentand the back-side source/drain epitaxyD. The back-side source/drain epitaxyB (corresponding to the drain BP_D of the transistor BP), the back-side source/drain epitaxyAC (corresponding to the drain AP_D of the transistor AP and the source CP_S of the transistor CP) and the back-side source/drain epitaxyD (corresponding to the source DP_S of the transistor DP) are electrically coupled to the back-side conductive segmentthrough the back-side conductive viaA, the back-side conductive viaB and the back-side conductive viaC.

As illustrated in, the source AP_S of the transistor AP and the source BP_S of the transistor BP are electrically coupled to a voltage VDD. For example, as illustrated in, the integrated circuitfurther includes a back-side conductive segment, and at least one back-side conductive viaA. The back-side conductive viaA connects the back-side conductive segmentand the back-side source/drain epitaxyAB. The back-side source/drain epitaxyAB (corresponding to the source AP_S of the transistor AP and the source BP_S of the transistor BP) is electrically coupled to the voltage VDD through the back-side conductive segment.

Referring to,illustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-′,illustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-′, andillustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-′.

As illustrated in, the integrated circuitfurther includes a plurality of contact etch stop layer CESL each covering the corresponding front-side source/drain epitaxyor back-side source/drain epitaxy. The integrated circuitfurther includes a plurality of metal over diffusions MD electrically connected with the corresponding front-side source/drain epitaxyor back-side source/drain epitaxy, and the conductive via (the front-side conductive via or the back-side conductive via) is electrically connected with the epitaxy through the metal over diffusion MD. The integrated circuitfurther includes an interlayer dielectric covering the front-side source/drain epitaxies and the back-side source/drain epitaxies. In addition, the integrated circuitfurther includes a first dielectric sidewalland a second dielectric sidewallrespectively formed on opposite two sides of the vertical local interconnectionfor electrically isolated from the front-side source/drain epitaxy and the back-side source/drain epitaxy. The first dielectric sidewalland the second dielectric sidewallare, for example, CMG (cut metal gate) dielectric. The first dielectric sidewalland the second dielectric sidewallmay be formed of a material including, for example, SiN, SiCN, SiOC, SiO2, etc.

Referring to,illustrates a schematic diagram of an integrated circuitaccording to an embodiment of the present disclosure,illustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-, andillustrates a schematic diagram of a cross-sectional view of the integrated circuitofin a direction-′.

As illustrated in, the integrated circuitincludes the features the same as or similar to that of the integrated circuitexcept that, for example, the integrated circuitincludes a vertical local interconnectiondifferent from the vertical local interconnectionin structure and the number of the transistors is different. The integrated circuitmay be is a logic circuit different from the integrated circuit.

As illustrated in, the integrated circuitfurther includes at least one gate component, at least one front-side source/drain epitaxies, at least one back-side source/drain epitaxies, at least one front-side conductive portion, at least one back-side conductive portion, at least one cut metal gate (CMG), a first dielectric sidewalland a second dielectric sidewall. The front-side conductive portionand the back-side conductive portionare, for example, metal over diffusions (MD).

As illustrated in, the front-side source/drain epitaxiesand the back-side source/drain epitaxiesform at least two transistors. The vertical local interconnectionconnects a first-connected one of the front-side source/drain epitaxiesand a second-connected one of the back-side source/drain epitaxies, wherein the first-connected one and the second-connected one are opposite to each other in Z-axis. The front-side conductive portionelectrically connects at least one of the one front-side source/drain epitaxieswith the vertical local interconnection, and the back-side conductive portionelectrically connects at least one of the one back-side source/drain epitaxieswith the vertical local interconnection. In the present embodiment, the vertical local interconnectionextends in a straight line or single straight line, for example, Z-axis. In addition, the vertical local interconnectionis formed on in cut metal gate. The cut metal gatemay be formed of a material including, for example, a dielectric material. The first dielectric sidewalland a second dielectric sidewallrespectively formed on opposite two sides of the vertical local interconnectionfor electrically isolated from the front-side source/drain epitaxy and the back-side source/drain epitaxy.

As illustrated in, there is a contacted poly pitch (CPP) Pbetween adjacent two metal gates G, wherein the pitch Pranges between, for example, 20 nanometer (nm) to 60 nm, even greater, or even smaller. In the present embodiment, the vertical local interconnectionhas a width Wless than the pitch P. As a result, it could reduce the parasitic capacitance of gate-to-drain and accordingly increase the oscillation frequency (response speed) of the integrated circuit.

Referring to,illustrate schematic diagrams of manufacturing processes of the integrated circuitof.

As illustrated in,illustrates a schematic diagram of a dielectric layer′ formed within an integrated circuit′, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the front-side FS of the integrated circuit′ faces up. Although no illustrated, the integrated circuit′ including the gate components, the front-side source/drain epitaxies, the back-side source/drain epitaxiesand an insulation layer′ is formed, wherein the back-side source/drain epitaxiesare formed on the insulation layer′, and the dielectric layer′ is formed within a recessof the interlayer dielectric. The recessis, for example, a recess for cut metal gate. The dielectric layer′ may be formed of a material including, for example, SiN, SiCN, SiOC, SiO2, etc.

As illustrated in,illustrates a schematic diagram of forming a recesson the dielectric layer′ of, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the recessis formed on the dielectric layer′ by using, for example, etching, such as an anisotropic plasma dry etching, etc. After the recessis formed, a remaining portion of the remaining dielectric layer′ includes the first dielectric sidewalland the second dielectric sidewall.

As illustrated in,illustrates a schematic diagram of forming a vertical local interconnection material′ within the recess, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the vertical local interconnection material′ fills up the recessby using, for example, deposition, electroplating, etc.

As illustrated in,illustrates a schematic diagram of forming a photoresist PRon the integrated circuit′ of, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the photoresist PRis formed on the integrated circuit′ and exposes a portion of the vertical local interconnection′.

As illustrated in,illustrates a schematic diagram of forming a first notchRon the vertical local interconnection′, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the first notchRis formed on the vertical local interconnection′ by using, for example, etching, etc. The first notchRextends from a front-side surfaceof the first dielectric sidewalland a front-side surfaceof the second dielectric sidewalltoward the back-side BS, but not extend to the insulation layer′. In other words, the first notchRis a blind hole.

As illustrated in,illustrates a schematic diagram of removing the photoresist PR. In this step, the photoresist PRofis removed by using, for example, etching, etc.

Then, a plurality of front-side conductive segmentsA,B,C andD, at least one front-side conductive segment, a plurality of front-side conductive viasA,B,C andD, and at least one front-side conductive viaB and at least one front-side conductive viaD are formed on the structure of.

As illustrated in,illustrates a schematic diagram of flipping the integrated circuit′ of, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the back-side BS of the integrated circuit′ faces up.

As illustrated in,illustrates a schematic diagram of forming a photoresist PRon the integrated circuit′ of. In this step, the photoresist PRis formed on the integrated circuit′ and exposes a portion of the insulation layer′ corresponding to the vertical local interconnection′.

As illustrated in,illustrates a schematic diagram of forming a second notchRon the vertical local interconnection′, andillustrates a schematic diagram of the integrated circuit′ ofin a directionB-B′. In this step, the second notchRis formed on the vertical local interconnection′ to form the vertical local interconnectionby using, for example, etching, etc. The second notchRextends from a back-side surfaceof the back-side dielectric sidewalland a back-side surfaceof the second dielectric sidewalltoward the front-side FS. In an embodiment, the second notchRis a blind hole.

As illustrated in,illustrates a schematic diagram of removing the photoresist PR. In this step, the photoresist PRis removed from the insulation layer′ by using, for example, etching, etc.

As illustrated in,illustrates a schematic diagram of removing the insulation layer. In this step, the insulation layer′ is removed to expose the vertical local interconnectionby using, for example, etching, etc.

Then, at least one back-side conductive segmentsand a plurality of back-side conductive viasA,B andC are formed on the structure of. So far, the integrated circuitofis completed.

Referring to,illustrate schematic diagrams of manufacturing processes of the integrated circuitof.

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of a recessfor the cut metal gatebeing formed, andillustrates a cross-sectional view, viewed in a direction-of, of a recessfor the cut metal gatebeing formed. In this step, a plurality of the front-side source/drain epitaxiesand a plurality of the back-side source/drain epitaxiesare formed on an insulation′, and an insulation′ is formed over the front-side source/drain epitaxiesand the back-side source/drain epitaxies. The recessmay be formed by using, for example, lithography, etching, etc. The recessis, for example, a recess for a cut metal gate.

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of the first dielectric sidewalland the second dielectric sidewallbeing formed, andillustrates a cross-sectional view, viewed in a direction-of, of the first dielectric sidewalland the second dielectric sidewallbeing formed. In this step, the first dielectric sidewalland the second dielectric sidewallis formed within the recessby using, for example, deposition, etching, etc. In addition, the forming method of the first dielectric sidewalland the second dielectric sidewallincludes the processes the same as or similar to that of the first dielectric sidewalland the second dielectric sidewallas aforementioned, and similarities will not be repeated here.

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of a vertical local interconnection material′ being formed, andillustrates a cross-sectional view, viewed in a direction-of, of the vertical local interconnection material′ being formed. In this step, the vertical local interconnection material′ is formed within the recessby using, for example, deposition, etc.

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of a portion of the vertical local interconnection material′ being removed, andillustrates a cross-sectional view, viewed in a direction-of, of a portion of the vertical local interconnection material′ being removed. In this step, an insulation layer′ of, a portion of the vertical local interconnection material′ are removed by using, for example, a CMP (Chemical Mechanical Polishing).

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of a photoresist PRbeing formed on the structure′ of, andillustrates a cross-sectional view, viewed in a direction-of, of the photoresist PRbeing formed on the structure′ of. In this step, the photoresist PRhas a translucent portion PRexposing a region other than a defining regionfor the subsequent vertical local interconnection.

Referring to,illustrates a cross-sectional view, viewed in a direction-of, of the vertical local interconnectionbeing formed, andillustrates a cross-sectional view, viewed in a direction-of, of the vertical local interconnectionbeing formed. In this step, a portion of the vertical local interconnection material′ is removed to form the vertical local interconnectionand expose a portion of the recessthrough the photoresist PRby using, for example, etching, etc.