Low-stress passivation layer

This application claims the benefit of U.S. Provisional Application No. 63/380,688, filed Oct. 24, 2022, the entirety of which is incorporated by reference herein.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.

For example, ICs are formed on a semiconductor substrate that may be cut into individual device dies or IC chips. Each IC chip may be further attached (such as by bonding) to an interposer, a reconstituted wafer, a circuit board, or another die to form a package or a device. To meet various routing needs, a redistribution layer (RDL) of conductive metal lines may be formed on an IC chip to reroute bond connections from the edge to the center of the chip, or generally to disperse bond connections to an area greater than that of the IC chip. One or more passivation layers are implemented around the RDL to protect the semiconductor surface from electrical shorts, stress, and chemical contaminants. However, some passivation layers are prone to stress and cracks during subsequent annealing processes and may lead to voids or cracks between adjacent metal contacts. Therefore, although existing passivation layers and the fabrication thereof have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described, or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

On many IC chips, a redistribution layer (RDL) of conductive metal lines is formed to reroute bond connections from the edge to the center of the chip or generally to distribute bond connections to an area larger than that of the IC chip. One or more passivation layers, which are formed of various dielectric layers, may be formed around the RDL to provide protection against electrical shorts, mechanical stresses, and chemical contaminants. By way of example, an RDL may be formed over a first passivation layer, and a second passivation layer may be formed over the RDL and over the first passivation layer. In some instances, a coefficient of thermal expansion (CTE) of the RDL, which is a metal layer, is much greater than that of the surrounding first and second passivation layers. Further, the one or more passivation layers may include a nitride layer (e.g., such as SiN), which has a high Young's modulus. As a result, when the RDL expands or contracts during subsequent annealing processes, the nitride layer of the one or more passivation layers may constrain the RDL and cause residual stress to be exerted from the RDL onto the one or more passivation layers. In some examples, such stress may be concentrated at locations where the device topography is not planar, such as at corners near an interface between the RDL and a passivation layer (e.g., such as at corners where the second passivation layer is formed over the RDL). Concentrated stress at those corners may propagate from the RDL through the one or more passivation layers, thus degrading device reliability.

Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include a semiconductor device with a multi-layer passivation structure and methods of making the same to address the issues described above. In some embodiments, after patterning the RDL, a corner rounding process may be performed to release stress from RDL corners, where stress may be concentrated. The corner rounding process may include a main etching step (with at least some over-etching), followed by an argon (Ar) bombardment step. In some examples, the main etching step is performed using chlorine gas (Cl) and boron trichloride gas (BCl), where a Cl/BClgas ratio is less than about 2. The Ar bombardment step may be performed for about 10-30 seconds, depending on a pattern density (PD) of the RDL. In some embodiments, the corner rounding process may be further tuned by modulating the deposition rate of the RDL, after which the etching and Ar bombardment steps are performed. In some examples, a dielectric deposition and etching process may be performed to chop portions of the second passivation layer, which may include a nitride layer, at corners where the second passivation layer is formed over the RDL to further release stress from RDL corners. In a further embodiment, the second passivation layer may be formed such that a portion of the second passivation layer that includes a nitride layer is only formed over a top surface the RDL and not over sidewalls of the RDL. As a result, constraint on the RDL by the nitride layer will be significantly reduced and residual stress from the RDL will be released. In some cases, this may also help to reduce formation of voids in the RDL. By implementation of one or more of the above processes to reduce residual RDL stress, cracks in the passivation layers can be avoided, thereby enhancing device yield and reliability, and improving subsequent die-to-die stacking processes. Other embodiments and advantages will be evident to those skilled in the art upon reading the present disclosure.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,provides a flowchart illustrating a methodfor fabricating a semiconductor device according to embodiments of the present disclosure. The methodis merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method. Additional steps can be provided before, during, and after the method, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. The methodis described below in conjunction with, which provide cross-sectional views of a workpieceat different stages of fabrication according to embodiments of the present disclosure. As the workpieceis to become or include a semiconductor device, the workpiecemay be referred to as semiconductor devicefrom time to time for simplicity.

Referring to, the methodincludes a blockwhere a workpiecethat includes a redistribution layer (RDL)is received. As shown in the example of, the workpieceincludes a substrate, an interconnect structureover the substrate, an etch stop layerover the interconnect structure, a first passivation layer, a barrier layer, and the RDLover and electrically coupled to the interconnect structure. In some embodiments, substratemay be made of silicon or other semiconductor materials such as germanium. In some other embodiments, substratemay include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In still other embodiments, substratemay include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some alternative embodiments, the substratemay include an epitaxial layer overlying a bulk semiconductor. Various microelectronic components may be formed in or on the substrate, such as transistor components including source/drain features and/or gate structures, isolation structures including shallow trench isolation (STI) structures, passive components, or any other suitable components.

The interconnect structuremay be a multi-layer interconnect (MLI) structure, which is formed over the substrateand may include contact viasand conductive linesembedded into multiple inter-metal dielectric (IMD) layersto provide interconnections (e.g., wiring) between the various microelectronic components that have been or will be formed on the workpiece. There may be intermediate layers or components disposed between the interconnect structureand the substrate, but in the interest of simplicity such layers or components are not shown. The IMD layersmay include silicon oxide or low-K dielectric materials whose K-values (dielectric constants) are smaller than that of silicon dioxide, which is about 3.9. In some embodiments, the low-K dielectric materials include a porous organosilicate thin film such as SiOCH, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOCN), hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), or combinations thereof.

Contact viasand conductive linesare formed in the IMD layers. The formation process for the contact viasand conductive linesmay include single damascene and/or dual damascene processes. In a single damascene process, a trench is first formed in one of the IMD layers, followed by filling the trench with a conductive material. A planarization such as a chemical mechanical polishing (CMP) process is then performed to remove the excess portions of the conductive material higher than the top surface of the IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, with the via opening underlies and is connected to the trench. The conductive material is then deposited into the trench and the via opening to form a metal line and a metal via, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, cobalt nitride, tungsten nitride, ruthenium, ruthenium nitride, other metal, or other metal nitride. The copper-containing metallic material may include copper, cupronickel, or a copper-aluminum alloy. Conductive linesat the same level may be collectively referred to as a metal layer and different metal layers are interconnected by one or more contact vias. In in the example of, the workpieceincludes a top metal layer, which serves as an interface to the RDL.

The workpiecealso includes the etch stop layerand the first passivation layerthat are formed before the RDL. In an embodiment, the etch stop layermay include silicon carbon nitride (SiCN), silicon oxycarbide (SiOCN), silicon oxycarbide (SiOC), silicon carbide (SiC), or silicon nitride (SiN), or combinations thereof. The first passivation layeris formed over the etch stop layer. The first passivation layermay be a single layer or a composite layer, and may be formed of a non-porous material. In some instances, the first passivation layermay be a single layer including silicon oxide. In at least some embodiments, the first passivation layerincludes an undoped silicate glass (USG) layer.

The RDLis electrically coupled to the interconnect structureby way of openings through the etch stop layerand the first passivation layer. In some embodiments, after the openings are formed, the barrier layeris deposited over the workpieceto insulate the to-be-formed RDLfrom the first passivation layer. The barrier layerserves as a diffusion barrier to block copper or aluminum diffusion into the first passivation layeras well as to block oxygen diffusion into the RDLas a result of subsequent annealing processes. The barrier layermay include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, cobalt nitride, tungsten nitride, ruthenium, ruthenium nitride, other metal, or other metal nitride. Although not separately shown, a blanket copper seed layer may also be formed over the barrier layersuch that the RDLmay be formed using electroplating. The RDLmay be formed of copper or an aluminum-copper alloy. In some embodiments represented by, the RDLis formed of an aluminum-copper alloy.

Referring now to, the methodincludes a blockwhere the RDLis patterned and cornersof the RDLare rounded.provide cross-sectional views (e.g., extending along the X direction or the Y direction) of a portion of the workpieceduring the patterning of the RDL, andprovide enlarged views of a portionof the workpieceillustrated inafter the RDLis patterned. Initially, as shown in, a nitride layer(e.g., such as SiON) is deposited over the RDL, and a photoresist layeris formed over the nitride layer. While not explicitly shown in all figures, the nitride layermay remain over a top surface of the RDL, as shown in, throughout the processing of the workpiece. In various examples, the photoresist layeris exposed (e.g., through a mask) and developed to form a pattern in the photoresist layerthat is subsequently transferred to the RDLby an etching processto form a recess. A shown in, the recessextends through the RDLto electrically separate the RDLinto a first conductive feature-and a second conductive feature-. Each of the first conductive feature-and the second conductive feature-may further extend along the Y direction. In some implementations and as shown in, the recessnot only extends through the RDL, but also through the barrier layer, and into the first passivation layer. After patterning the RDL, the photoresist layeris removed from over the patterned RDL.

In some embodiments, the etching processto pattern and round the cornersof the RDLmay include one or more etching steps. For example, the etching processmay include a main etching stepA (with at least some over-etching) that etches through the nitride layerand through substantially all of the RDL, where the main etching stepA (and the at least some over-etching) is performed using a first Cl/BClgas ratio. Thereafter, and also as part of the etching process, a further over-etching stepB may be performed to etch through the barrier layerand part of the first passivation layer, where the further over-etching stepB is performed using a second Cl/BClgas ratio different than the first Cl/BClgas ratio. In some examples, transitioning the etching processfrom the main etching stepA to the further over-etching stepB is performed by changing the Cl/BClgas ratio from the first Cl/BClgas ratio to the second Cl/BClgas ratio. In some embodiments, the first Cl/BClgas ratio of the main etching stepA is less than about 2, and the second Cl/BClgas ratio of the further over-etching stepB is in a range from between about 2-3. In some examples, rounding of the cornersby the etching processis achieved by ensuring that the photoresist layeris etched to form a dome shape, as shown in. This is done by ensuring that the first Cl/BClgas ratio of the main etching stepA is less than about 2, which causes the photoresist layerto be consumed faster, especially along lateral ends, to form the dome shape. By providing the dome shape, the cornerswill be more exposed and amenable to rounding by the etching process. In contrast, for at least some existing techniques that use a Cl/BClgas ratio of the main etching stepA that is equal to or greater than 2, the cornersmay remain substantially square-shaped and are thus not amenable to rounding. After the etching processof block, any remaining portion of the photoresist layeris removed, while the nitride layerremains.

Still referring to, the methodincludes a blockwhere the cornersof the RDLare further rounded. In particular, after removing any remaining portion of the photoresist layer, the cornersof the RDLare further rounded by performing an argon (Ar) ion bombardment step. In some examples, the Ar ion bombardment stepis primarily directed at the corners, as shown in. The Ar ion bombardment stepmay be performed for about 10-30 seconds, for example, depending on a pattern density (PD) of the RDL. For instance, the Ar ion bombardment stepmay be performed for a shorter amount of time for an RDLwith a lower PD, and for a greater amount of time for an RDLwith a higher PD. As merely one example, the Ar ion bombardment stepmay be performed for about 10 seconds for an RDLhaving a low PD and for about 30 seconds for an RDLhaving a high PD. In various embodiments, the Ar ion bombardment stepserves to further enhance the rounding of the cornersof the RDL. It is further noted that in some examples, the density of the as-deposited RDLmay be modified (e.g., by modifying the deposition rate of the RDL), and as a result, the corner rounding of the RDLprovided by the etching process(block) and the Ar ion bombardment step(block) may be improved.

As noted above,provides an enlarged view of a portionof the workpieceillustrated inafter the RDLis patterned (e.g., after the Ar ion bombardment stepof block). In particular, the example ofprovides an exemplary technique for measuring an extent of rounding of the cornersof the RDL. As shown, a circle may be drawn such that the surface of the rounded cornersoverlaps with a portion of a circumference (an arc ‘S’) of the circle. A length of the arc ‘S’ may be determined according to the equation: arc length=2πR*(θ/360), where R is the radius of the circle and θ is the central angle of the arc ‘S’. In the example shown, the central angle θ is equal to about 90 degrees, and the radius R is in a range of about 200-210 nm. Thus, in the example of, the length of the arc ‘S’ is in a range of about 314-330 nm. The length of the arc ‘S’ may thus be equivalently referred to as the length of the rounded portion of the cornersof the RDL.

also provides an enlarged view of the portionof the workpieceillustrated inafter the RDLis patterned (e.g., after the Ar ion bombardment stepof block), as previously noted. The example ofprovides an exemplary alternative technique for measuring an extent of rounding of the cornersof the RDL. As shown, tangent lines can be drawn that are tangent to the sidewall surface of the patterned RDL(tangent line A) and tangent to the top surface of the patterned RDL(tangent line B). As shown, the two tangent lines A and B intersect at a point C. In an example, the corner rounding can then be described as a distance D between the intersection point C and the rounded surface of the RDL. In some embodiments, this may also be described as a distance D by which the corner of the patterned RDLhas “withdrawn” from the intersection point C due to the corner rounding. In various embodiments, the distance D may be greater than or equal to about 70 nm.

Referring now to, the methodincludes a blockwhere a first dielectric layeris deposited over the patterned RDLthat includes the first conductive feature-and the second conductive feature-, including within the recess. As noted above, and in some embodiments, since the nitride layerremains over the RDL, the first dielectric layermay be deposited over the nitride layer. In some embodiments, the first dielectric layerincludes silicon oxide and may be formed using chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), or plasma-enhanced CVD (PECVD). In some implementations, the first dielectric layermay be an undoped silicate glass (USG) layer formed to a thickness between about 1500 Angstroms (Å) and about 5000 Å. In at least some examples, the first dielectric layerhas a thickness of about 4000 Å. As shown in the example of, in some embodiments and due to the aspect ratio of the recessand/or to the deposition process used to deposit the dielectric layer, the deposited first dielectric layermay accumulate over the cornersof the RDLadjacent to the recessto form overhang regions. As a result, the as-deposited thickness of the first dielectric layermay be non-conformal. For example, the first dielectricmay have a thickness ‘T1’ between about 3000 Å and about 5000 Å along a top surface of the RDL(on a first side of the overhang region) and a thickness ‘T2’ between about 2000 Å and about 4000 Å along a sidewall surface of the RDLwithin the recess(on a second side of the overhang region).

Referring now to, the methodincludes a blockwhere a nitride layeris deposited over the first dielectric layer, including within the recessand over the overhang regions. In some embodiments, the nitride layerincludes silicon nitride (SiN) and may be formed using CVD, SACVD, or PECVD. In some implementations, the nitride layermay be formed to a thickness between about 675 Å and about 825 Å. In at least some cases, the nitride layermay be formed to a thickness of about 750 Å. In some examples, the nitride layermay serve as an etch-stop layer. Moreover, as the nitride layerhas a high Young's modulus, the nitride layercan constrain the RDLduring subsequent annealing processes and cause residual stress to form in the RDL. In accordance with some embodiments, and as described further below, portions of the nitride layerat the overhang regions(and over the corners) can be removed (or chopped) so as to release the residual stress from cornersof the RDLwhere such stress can accumulate.

Referring now to, the methodincludes a blockwhere a second dielectric layeris formed. The second dielectric layeris formed using a deposition technique different from the one used to deposit the first dielectric layer. In some embodiments, the second dielectric layerincludes silicon oxide and may be deposited using a high-density plasma chemical vapor deposition (HDPCVD) process. In various examples, the HDPCVD deposition of the second dielectric layerincludes alternating deposition and etching-back cycles to chop portions of the nitride layerin the overhang regions, thereby releasing residual stress from cornersof the RDL. The HDPCVD deposition also provides excellent gap fill (e.g., of the recess) and a void-free dielectric layer (the second dielectric layer) over the RDL. In some cases, the various deposition and etching-back cycles may be performed at different radio frequency (RF) power values and/or at different pressures, as discussed below. Also, in some embodiments, the deposition and etching-back cycles may occur concurrently, with a net positive deposition rate.

By way of example, and as shown in, the HDPCVD deposition of the second dielectric layerbegins with a first deposition of the second dielectric layer(denoted inas-) over the nitride layer, including within the recessand over the overhang regions. In an example, the first deposition of the second dielectric layermay be performed at an RF power of between about 4.7 kW and about 6.7 kW, such as for instance about 5.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the first deposition of the second dielectric layer-may be formed to a thickness between about 250 nm and about 350 nm along a top surfaceof the workpiece. In at least some examples, the first deposition of the second dielectric layer-may have a thickness of about 300 nm. It is noted that due to the overhang regions, the first deposition of the second dielectric layer-may be thinner within the recess(e.g., such as along sidewalls of the recess) as compared to the top surface.

After the first deposition of the second dielectric layer-, the HDPCVD process continues with an etching-back process. With reference to, an etching-back process is performed (e.g., using an oxygen-containing species, such as high-energy oxygen atoms) to remove a portion of the previously deposited first deposition of the second dielectric layer-. In some embodiments, the etching-back process is performed at a high RF power of about 8 kW and at a pressure of about 9E-3 Torr. In some embodiments, the etching-back process may be performed at an RF power of between about 7 kW and about 9 kW, and at a pressure in a range of between about 10E-2 Torr and 10E-3 Torr. In some cases, the etching-back process may cause thinning of a thickness of the first deposition of the second dielectric layer-along the top surface. More particularly, the etching-back process may preferentially etch the workpieceat or near the overhang regions. As a result, the etching-back process may remove (or chop) corners of the first deposition of the second dielectric layer-, the nitride layer, and the first dielectric layerin the overhang regionsto form etched surfacesthat define a discontinuity regionin the nitride layer. As shown, the discontinuity regionin the nitride layeris substantially aligned with the cornersof the RDL, thereby providing for residual stress from the cornersof the RDLto be released.

After performing the etching-back process to form the etched surfaces, and as shown in, the HDPCVD process continues with a second deposition of the second dielectric layerover the first deposition of the second dielectric layer-(on the top surfaceand within the recess), and over the etched surfacesthat include the discontinuity regionin the nitride layer. In some embodiments, the second deposition of the second dielectric layeris performed at a low RF power of about 5.7 kW and at a pressure of about 4.5E-3 Torr. In some embodiments, the second deposition of the second dielectric layermay be performed at an RF power of between about 4.7 kW and about 6.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the second deposition of the second dielectric layermay be formed to a thickness between about 2,225 nm and about 2,750 nm. In at least some examples, the second deposition of the second dielectric layermay have a thickness of about 2,500 nm. In one example, a total thickness ‘T3’ of the second dielectric layer, which includes the net deposition of both the first and second depositions of the second dielectric layer, may be about 2,700 nm.

It is noted that while after the second deposition of the second dielectric layerthe recessis substantially filled, because of the topography of the workpiece, a dent′ remains. In some embodiments, the second dielectric layeris deposited to the thickness ‘T3’ to ensure that a bottom surfaceof the dent′ is higher (farther away from the substrate) than a top surfaceof the RDL. When the bottom surfaceis higher (farther away from the substrate) than the top surface, the first conductive feature-and the second conductive feature-are spaced apart by portions of the first dielectric layer, the nitride layer, and the second dielectric layer, and a third dielectric layer(shown in) does not extend between the first conductive feature-and the second conductive feature-. That means the first conductive feature-and the second conductive feature-are separated largely by the second dielectric layer, which may include high-quality and substantially void-free silicon oxide deposited using HDPCVD.

Referring now to, the methodincludes a blockwhere a third dielectric layeris deposited over the second dielectric layer. The third dielectric layeris deposited using a deposition technique different from the one used to deposit the second dielectric layer. In some embodiments, the third dielectric layerincludes silicon oxide and may be deposited using CVD, SACVD, or PECVD. In some implementations, the third dielectric layermay be an undoped silicate glass (USG) layer formed to a thickness ‘T4’ between about 8,000 Angstroms (Å) and about 10,000 Å. The thickness ‘T4’ is selected such that a lowest top surface of the third dielectric layeris higher (farther away from the substrate) than a top surface of the second dielectric layer. This arrangement helps to ensure that after the planarization process at block(described below), the workpiecewould include a level top surface.

Referring now to, the methodincludes a blockwhere a top surface of the workpieceis planarized to provide a level top surface. In some embodiments, the workpieceis planarized using CMP. Portions of the third dielectric layerand the second dielectric layerare removed at blockto produce the level top surface. In some embodiments, and after the CMP process, the total thickness ‘T3’ of the second dielectric layermay be between about 900 nm and about 1,500 nm. As illustrated in, the level top surfaceincludes a portion of the third dielectric layerand a portion of the second dielectric layer.

Referring to, the methodincludes a blockwhere a fourth dielectric layeris deposited over the level top surface. In some embodiments, the fourth dielectric layermay be a nitrogen-containing dielectric material such as silicon nitride or silicon carbonitride and may be deposited using CVD, PECVD, HDPCVD, SACVD, or a suitable deposition technique. In one embodiment, the fourth dielectric layeris formed of silicon nitride. Because the fourth dielectric layeris deposited over and in direct contact with the level top surface, the fourth dielectric layeris planar and does not extend downward (towards the substrate) into either the third dielectric layeror the second dielectric layer. In some implementations, the fourth dielectric layeris formed to a thickness between about 4,000 Å and about 10,000 Å, including about 7,000 Å. In some cases, the fourth dielectric layeris a barrier layer, for example protecting against moisture or other contaminants, to protect the underlying elements of the workpiece. The first dielectric layer, the nitride layer, the planarized second dielectric layer, the planarized third dielectric layer, and the fourth dielectric layermay be regarded as a second passivation layer. As illustrated in, the RDL, such as the first conductive feature-and the second conductive feature-, is thus sandwiched between the underlying first passivation layerand the overlying second passivation layer.

Referring to, the methodincludes a blockwhere a bonding layeris formed over the fourth dielectric layer. In some embodiments, the bonding layermay include an oxide or nitrogen-containing dielectric material such as SiO, SiN, SiON, SiCN, or SiOCN and may be deposited using CVD, PECVD, HDPCVD, SACVD, or a suitable deposition technique. In one embodiment, the bonding layeris formed of SiON. In some cases, the bonding layerprovides for improved bonding between the workpiece(which may include a first die) and another workpiece (which may include a second die), for example, as part of a subsequent die-to-die stacking process.

Still referring to, the methodincludes a blockwhere contact features, such as a contact featureincluding a conductive via portionA and a conductive line portionB, are formed. Initially, a contact recess may be formed through the bonding layer, the fourth dielectric layer, the second dielectric layer, the nitride layer, and the first dielectric layerto expose the first conductive feature-. After forming the contact recess, a metal layer is deposited therein to form the contact feature. The contact features, such as the contact feature, may be formed of copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, or an alloy thereof and may be deposited by electroplating, evaporation, electroless plating, sputter deposition, or other suitable technique. In an example, the contact featureis formed of copper. After formation of the contact feature, a CMP process may be performed to remove excess material and planarize a top surface of the workpiece. In some embodiments, the first conductive feature-thus serves as a contact pad to engage the contact featureformed there above. In some examples, a contact feature may be similarly formed to engage the second conductive feature-, and other contact features may also be formed to engage other conductive features (e.g., of the RDL) not explicitly shown.

Referring to, the methodincludes a blockwhere a bonding process is performed. In an example, the bonding process may be a hybrid bonding process which includes bonding of metal pads (e.g., such as the conductive line portionB of the contact feature) and the surrounding dielectric material (e.g., such as the bonding layer) of two IC chips (die), two wafers, or a die and a wafer to create a low profile, low parasitic, high-performance interconnect therebetween. In the example of, the workpieceprovides a first die(or IC chip), and another workpiecemay be similarly processed according to the methodto provide a second die(or IC chip) which can be bonded to the firstdie as part of the bonding process. In the example shown, the second diemay be flipped so that a front sideof the first diefaces, and is in contact with, a front side-of the second die. It is noted that prior to contacting the first dieand the second die, a surface activation process may be performed to each of the front sideof the first dieand the front side-of the second die. In some embodiments, the surface activation may include a plasma treatment process (e.g., such as using an Ar plasma) to increase the bonding energy of the bonding layerof the first dieand a bonding layer-of the second die.

After the surface activation process, and using a high precision alignment process, the front sideof the first diemay be brought into contact with the front side-of the second diealong an interfacesuch that the conductive line portionB of the first dieis substantially aligned with a conductive line portionB-of the second die. In some embodiments, the surfaces of the bonding layerand the bonding layer-, which are now in contact with each other along the interface, may form covalent bonds and/or may be attracted to each other by van der Waals forces. In some cases, the bonding of the surfaces of the bonding layerand the bonding layer-may occur at room temperature. Once the front sideof the first dieis brought into contact with the front side-of the second die, an annealing process may be performed to form an electrical connection between the conductive line portionB of the first dieand the conductive line portionB-of the second die. In some cases, the annealing process may be performed at a temperature between about 200 degrees Celsius and about 400 degrees Celsius. As an example, for instance when the contact featuresare formed of copper, the annealing process may result in volume expansion of the copper, including filling of any gaps that may have been present between the conductive line portionB and the conductive line portionB-(e.g., due to CMP dishing), thereby completing the electrical connection between the conductive line portionB and the conductive line portionB-. It is noted that in accordance with various embodiments which provide for the release of residual stress from the RDL, the formation of cracks (e.g., in the second passivation layer) can be substantially avoided during the annealing process to form the electrical connection between the conductive line portionsB,B-, as well as during other annealing processes that may be performed during fabrication of the first dieand the second die. As a result, device yield and reliability are enhanced, and the process of bonding of the first dieto the second dieis improved.

Referring now to, illustrated therein is a flowchart illustrating a methodfor fabricating a semiconductor device according to some alternative embodiments of the present disclosure. The methodis merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method. Additional steps can be provided before, during, and after the method, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. The methodis described below in conjunction with, which provide cross-sectional views of the workpieceat different stages of fabrication according to embodiments of the present disclosure. It is noted that the methodis substantially similar to the method, described above. As such, the discussion of the methodprovided below focuses primarily on the differences between the methods,. Moreover, unless otherwise stated, like reference numerals in the figures may refer to the same features or elements previously described.

Referring to, the methodincludes the blockwhere the workpiecethat includes the RDLis received. In some embodiments, the workpiecemay be substantially the same as described above with reference to the example of. Still referring to, instead of initially patterning the RDLas in the method, the methodfirst proceeds to the blockwhere the first dielectric layeris deposited over the RDL. After depositing the first dielectric layer, and still with reference to, the methodproceeds to the blockwhere the nitride layeris deposited over the first dielectric layer. It is noted that in at least some embodiments, the first dielectric layermay not be formed and instead the nitride layermay be formed directly over the nitride layer(e.g., such as SiON) that remains over the RDL(e.g., as shown in).

Referring to, the methodincludes a block′ where the RDL, the first dielectric layer, and the nitride layerare patterned to form the recessand cornersof the RDLare rounded. A shown in, the recessextends through the nitride layer, the first dielectric layer, and the RDLto electrically separate the RDLinto the first conductive feature-and the second conductive feature-. The etching processmay be used to pattern and round the cornersof the RDL, as previously described. However, in some embodiments of the method, since the dielectric layerand the nitride layerare deposited prior to the patterning and rounding process, corners of the dielectric layerand the nitride layer(disposed directly above the cornersof the RDL) may likewise be rounded by the etching process. More particularly, since the nitride layeris deposited prior to the patterning and rounding process of block′, the nitride layeris absent from the recess(and thus absent from sidewalls of the RDL), in contrast to the method. In other words, the nitride layeris only formed over a top surface the RDLand not over sidewalls of the RDL. As a result, constraint on the RDLby the nitride layerwill be significantly reduced and residual stress from the RDLwill be released. Further, as the nitride layermay be used as an etch-stop layer, formation of the nitride layerover only the top surface of the RDLwill reduce an etch-stop layer area by greater than about 20%, including about 24%. In some cases, this may also help to reduce formation of voids in or adjacent to the RDL.

After the patterning and rounding process of block′, the methodincludes the blockwhere the cornersof the RDL(and in some embodiments corners of the dielectric layerand the nitride layerdisposed directly over the cornersof the RDL) are further rounded. In some embodiments, the further rounding may be performed by using the Ar ion bombardment step, as described above.

Referring to, the methodincludes the blockwhere the second dielectric layeris formed. The second dielectric layermay include silicon oxide and may be formed using an HDPCVD process, as described above. In the method, and in some embodiments, since the nitride layeris not formed along sidewalls of the RDL, chopping portions of the nitride layernear the cornersmay not be necessary (or at least is an optional step). Thus, in some examples of the method, the various deposition and etching-back cycles of the HDPCVD may be performed at a substantially constant RF power value and pressure. For instance, in some embodiments, the second dielectric layermay be deposited at a low RF power of about 5.7 kW and at a pressure of about 4.5E-3 Torr. In some embodiments, the second dielectric layermay be deposited at an RF power of between about 4.7 kW and about 6.7 kW, and at a pressure in a range of between about 4E-3 Torr and 5E-3 Torr. In some implementations, the second dielectric layermay be formed to a thickness of about 2,700 nm.

Referring now to, the methodincludes the blockwhere the third dielectric layeris deposited over the second dielectric layer. In some embodiments, the third dielectric layermay be substantially the same as described above. Referring to, the methodalso includes the blockwhere a top surface of the workpieceis planarized (e.g., using CMP) to provide the level top surface. In some embodiments, and after the CMP process, the total thickness ‘T3’ of the second dielectric layermay be between about 900 nm and about 1,500 nm. As illustrated in, the level top surfaceincludes a portion of the third dielectric layerand a portion of the second dielectric layer.

Referring to, the methodfurther includes the blockwhere the fourth dielectric layeris deposited over the level top surface. In some embodiments, the fourth dielectric layermay be substantially the same as described above. Referring to, the methodincludes the blockwhere the bonding layeris formed over the fourth dielectric layer. In some embodiments, the bonding layermay be substantially the same as described above.

Still referring to, the methodincludes the blockwhere contact features, such as the contact featureincluding the conductive via portionA and the conductive line portionB, are formed. In some examples, the contact featuremay be substantially the same as described above. After formation of the contact feature, a CMP process may be performed to remove excess material and planarize a top surface of the workpiece.

Referring to, the methodfurther includes the blockwhere a bonding process is performed. In some cases, the bonding process may be a hybrid bonding process, as previously discussed. In the example of, the workpieceprovides the first die(or IC chip), and another workpiecemay be similarly processed according to the method(or according to the method) to provide the second die(or IC chip) which can be bonded to the firstdie as part of the bonding process. The bonding process of the blockmay be performed as discussed above. For instance, a surface activation process may be performed to each of the front sideof the first dieand the front side-of the second die. Thereafter, the front sideof the first diemay be brought into contact with the front side-of the second diealong the interfacesuch that the conductive line portionB of the first dieis substantially aligned with a conductive line portionB-of the second die. An annealing process may then be performed to form an electrical connection between the conductive line portionB of the first dieand the conductive line portionB-of the second die. It is noted that in accordance with embodiments of the method, the release of residual stress from the RDLprovided by not forming the nitride layeralong sidewalls of the RDLhelps to prevent the formation of cracks (e.g., in the second passivation layer) during various annealing processes. As a result, device yield and reliability are enhanced, and the process of bonding of the first dieto the second dieis improved.

With respect to the description provided herein, disclosed are embodiments of a semiconductor device with a multi-layer passivation structure and methods of making the same to address various issues associated with at least some existing implementations. In some embodiments, after patterning an RDL, a corner rounding process may be performed to release stress from RDL corners, where stress may be concentrated. The corner rounding process may include a plurality of etching steps, followed by an Ar bombardment step. In some examples, a main etching step is performed using chlorine gas (Cl) and boron trichloride gas (BCl), where a Cl/BClgas ratio is less than about 2. The Ar bombardment step may be performed for about 10-30 seconds, depending on a pattern density (PD) of the RDL. In some embodiments, the corner rounding process may be further tuned by modulating the deposition rate of the RDL, after which the etching and Ar bombardment steps are performed. In some examples, a dielectric deposition and etching process may be performed to chop portions of the second passivation layer, which may include a nitride layer, at corners where the second passivation layer is formed over the RDL to further release stress from RDL corners. In a further embodiment, the second passivation layer may be formed such that a portion of the second passivation layer that includes a nitride layer is only formed over a top surface the RDL and not over sidewalls of the RDL. As a result, constraint on the RDL by the nitride layer will be significantly reduced and residual stress from the RDL will be released. In some cases, this may also help to reduce formation of voids in or adjacent to the RDL. By implementation of one or more of the above processes to reduce residual RDL stress, cracks in the passivation layers can be avoided, thereby enhancing device yield and reliability, and improving subsequent die-to-die stacking processes.

Thus, one of the embodiments of the present disclosure described a method that includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. In some examples, the method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. In some embodiments, the method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.

In another of the embodiments, discussed is a method that includes providing a substrate having a redistribution layer disposed over a multi-layer interconnect (MLI) structure. In some embodiments, the method further includes depositing a nitride layer over the redistribution layer and forming a recess extending through the nitride layer and the redistribution layer. In an example, the recess separates a first portion of the redistribution layer from a second portion of the redistribution layer. In some embodiments, and after forming the recess, the nitride layer remains disposed over top surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer, while sidewall surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer are free of the nitride layer.

In yet another of the embodiments, discussed is a semiconductor device including a redistribution layer having a first conductive feature and a second conductive feature separated by a recess, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. In some embodiments, the semiconductor device further includes a passivation layer disposed over the redistribution layer and within the recess. In various examples, the semiconductor device further includes a contact feature extending through the passivation layer and electrically coupled to the first conductive feature. In some embodiments, the passivation layer includes a nitride layer having a discontinuity region that is substantially aligned with the corners of the first conductive feature and the second conductive feature. In some cases, a top surface of the first conductive feature defines a first plane, a sidewall of the first conductive feature adjacent to the recess defines a second plane that intersects the first plane, and a rounding of the corner of the first conductive feature is defined at least partly by a distance between the intersection of the first and second planes and a surface of the corner of the first conductive feature.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.