Semiconductor device

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0089883, filed on Jul. 20, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The inventive concepts relate to semiconductor devices. More particularly, the inventive concepts relate to semiconductor devices including a cell pad structure.

With the development of the electronics industry, semiconductor devices are gradually being downscaled. Accordingly, the size of individual microcircuit patterns for implementing a semiconductor device is further reduced. In addition, as the integrated circuit device is highly integrated, the line width of the bit line decreases and the difficulty of the process for forming the contact between the bit lines increases.

The inventive concepts provide semiconductor devices capable of reducing the cost of a semiconductor device manufacturing process while improving reliability.

According to an aspect of the inventive concepts, a semiconductor device including a substrate includes a cell array region and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a plurality of word lines in the substrate and extending in a first direction, a plurality of bit lines in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on corresponding ones of the word lines, respectively, the first pad separation patterns extending in the first direction, a cell pad structure on the substrate and being between two adjacent ones of the first pad separation patterns, and a second pad separation pattern between two adjacent ones of the first pad separation patterns and being adjacent to the cell pad structure, wherein a cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape in which both corners of a lower surface are rounded.

According to another aspect of the inventive concepts, a semiconductor device including a substrate includes a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a word line in the substrate and extending in a first direction, a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a plurality of first pad separation patterns on the word line, the first pad separation patterns extending in the first direction, a cell pad structure on the substrate and between two adjacent ones of the first pad separation patterns, a second pad separation pattern between two adjacent ones of the first pad separation patterns the second pad separation pattern being adjacent to the cell pad structure, a first insulating layer on the cell pad structure and extending to the boundary region, and a second insulating layer on the first insulating layer and extending to the boundary region, wherein a first cross-section of the cell pad structure perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface are rounded, and wherein an upper surface of the first insulating layer and an upper surface of the second insulating layer are flat.

According to another aspect of the inventive concepts, a semiconductor device includes a substrate including a cell array region, a boundary region, and a peripheral circuit region, the substrate including a plurality of first active regions defined in the cell array region and at least one second active region defined in the peripheral circuit region, a word line in the substrate and extending in a first direction, a capping insulating film on the word line, a bit line in the cell array region of the substrate and extending in a second direction perpendicular to the first direction, a direct contact between the bit line and a corresponding one of the first active regions, a plurality of cell pad structures in contact with the first active regions, respectively, the cell pad structures being on the substrate, a buried contact on a corresponding one of the cell pad structures, a first pad separation pattern on the word line and extending in the first direction, a second pad separation pattern between two adjacent ones of the cell pad structures and extending in the second direction, a buffer layer on the cell pad structure and extending to the boundary region, and a first insulating layer on the buffer layer and extending to the boundary region, wherein a first cross-section of each of the cell pad structures perpendicular to the first direction has a quadrangular shape, in which both corners of a lower surface are rounded, wherein an upper surface of the buffer layer and an upper surface of the first insulating layer are flat, and wherein the capping insulating film and a corresponding one of the first pad separation patterns are portions of a single integral structure, respectively.

Hereinafter, some example embodiments of the technical ideas of the inventive concepts will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

While the term “same,” “equal” or “identical” is used in description of example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

is a layout diagram illustrating a semiconductor deviceaccording to an example embodiment of the inventive concepts.is an enlarged layout diagram of a portion EX of.is a cross-sectional view taken along line A-A′ of.is a cross-sectional view taken along line B-B′ of.

Referring to, the semiconductor devicemay include a substrateincluding a cell array region MCA and a peripheral circuit region PCA. The cell array region MCA may be a memory cell region of a dynamic random access memory (DRAM) element, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM element. For example, the cell array region MCA may include a cell transistor CTR and a capacitor structure (not shown) connected thereto, and the peripheral circuit region PCA may include a peripheral circuit transistor (not shown) for transmitting a signal and/or power to a cell transistor (not shown) included in the cell array region MCA. In some example embodiments, the peripheral circuit transistor may configure various circuits such as a command decoder, a control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input/output circuit.

A boundary trenchT may be formed in a boundary region BA between the cell array region MCA and the peripheral circuit region PCA, and a boundary structuremay be formed in the boundary trenchT. In a plan view, the boundary trenchT may be disposed to surround four surfaces (e.g., four sides) of the cell array region MCA. The boundary structuremay include a buried insulating layerA, an insulating linerB, and a gap-fill insulating layerC disposed inside the boundary trenchT.

The buried insulating layerA may be conformally disposed on the inner wall of the boundary trenchT. In some example embodiments, the buried insulating layerA may include silicon oxide. For example, the buried insulating layerA may include silicon oxide formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, a low pressure CVD (LPCVD) process, or the like.

The insulating linerB may be conformally disposed on the inner wall of the boundary trenchT, more specifically, on the buried insulating layerA. In some example embodiments, the insulating linerB may include silicon nitride. For example, the insulating linerB may include silicon nitride formed by an ALD process, a CVD process, a PECVD process, an LPCVD process, or the like.

The gap-fill insulating layerC on the insulating linerB may fill the inside of the boundary trenchT. In some example embodiments, the gap-fill insulating layerC may include silicon oxide, such as tonen silazene (TOSZ), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma enhanced deposition of tetra-ethyl-ortho-silicate (PE-TEOS), or fluoride silicate glass (FSG).

A plurality of first active regions ACTmay be disposed to have long axes in a diagonal direction with respect to a first horizontal direction X and a second horizontal direction Y, respectively. A plurality of word lines WL may extend parallel to each other in the first horizontal direction X across the plurality of first active regions ACT. A plurality of bit lines BL may extend parallel to each other in the second horizontal direction Y on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of first active regions ACTthrough direct contacts DC, respectively.

A plurality of cell pad structuresmay be formed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of cell pad structuresmay be arranged in a line in the first horizontal direction X and the second horizontal direction Y.

The substratemay include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other example embodiments, the substratemay include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some example embodiments, the substratemay include a conductive region, for example, a well doped with an impurity, or a structure doped with an impurity.

An element isolation trenchT may be formed in the substrate, and an element isolation filmmay be formed in the element isolation trenchT. The element isolation filmmay include, for example, an oxide film, a nitride film, or a combination thereof. In the cell array region MCA, a plurality of first active regions ACTmay be defined on the substrateby the element isolation film, and at least one second active region ACTmay be defined on the substratein the peripheral circuit region PCA.

In the cell array region MCA, a plurality of word line trenchesT, which extends in a first horizontal direction (X direction) to intersect with a plurality of first active regions ACT, may be disposed in the substrate, and a buried gate structuremay be disposed in each of the plurality of word line trenchesT. The buried gate structuremay include a gate dielectric film, a gate electrode, and a capping insulating film. The plurality of gate electrodesmay correspond to the plurality of word lines WL illustrated in, respectively.

The gate dielectric filmmay include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide/nitride/oxide (ONO) film, or a high-k dielectric film having a higher dielectric constant than that of the silicon oxide film. The gate electrodemay include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The capping insulating filmsmay include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

A plurality of first pad separation patternsmay be disposed on the plurality of buried gate structures, respectively. Each of the plurality of first pad separation patternsmay extend in the first direction (X direction) and may be apart from each other in a second direction (Y direction). The first pad separation patternmay include, for example, silicon nitride. In some example embodiments, the first pad separation patternmay be integrally formed with the capping insulating film. In other words, the capping insulating filmand the first pad separation patternmay be portions of a single integral structure, respectively. Accordingly, the length of the first pad separation patternin the second direction (Y direction) may be the same as the length of the capping insulating filmin the second direction (Y direction). However, the inventive concepts are not limited thereto, and if desired, spacers (not shown) may be additionally formed on both sidewalls of the first pad separation pattern.

The plurality of cell pad structuresmay be disposed between two adjacent first pad separation patterns. In some example embodiments, a cross-section of the cell pad structureperpendicular to the first direction (X direction) may have a quadrangular shape in which both corners of the lower surface are rounded. As stated later, after forming the first separation pad patternby using a first mask pattern Ox (refer to) used to form the word line WL, without using a separate mask pattern, and the cell pad structureis formed using the first separation pad pattern, the aforementioned cross-sectional shape of the cell pad structuremay be obtained. Because a separate mask pattern is not used to form the first pad separation pattern, compared to the case of forming pad separation patterns using two mask patterns in the conventional art, the manufacturing process of the semiconductor devicemay be simplified. Accordingly, the cost of the manufacturing process of the semiconductor devicemay be reduced.

In some example embodiments, as shown in, the upper surface of the cell pad structuremay be disposed at a higher vertical level than the upper surface of the second active region ACT, and the lower surface of the cell pad structuremay be disposed at a lower vertical level than the upper surface of the second active region ACT. For example, the upper surface of the cell pad structuremay be disposed at the first vertical level X, the upper surface of the second active region ACTmay be disposed at a second vertical level Xthat is lower than the first vertical level X, and the lower surface of the cell pad structuremay be disposed at a third vertical level Xthat is lower than the second vertical level X. As shown in, the cell pad structureis disposed on the first active region ACT. Accordingly, the lower surface of the cell pad structureand the upper surface of the first active region ACTmay be disposed at the same vertical level. Because the lower surface of the cell pad structureis located at a lower vertical level than the upper surface of the second active region ACT, the upper surface of the first active region ACTmay also be located at a lower vertical level than the lower surface of the second active region ACT. This is because, as will be described later with reference to, a process of recessing the upper surface of the first active region ACTof the substrateis performed in the manufacturing process of the semiconductor device. When such a recess process is performed, even if the cell pad structureis disposed on the upper surface of the first active region ACT, a step difference between the cell array region MCA and the peripheral circuit region PCA due to the length of the cell pad structurein the third direction (Z direction) may be minimized. In addition, compared to the case where the recess process is not performed, the desired length in the third direction (Z direction) of the first mask pattern Ox used to form the first pad separation patternmay be reduced, thereby reducing the difficulty of the manufacturing process of the semiconductor device.

In some example embodiments, the lower surfaces of the plurality of cell pad structuresmay be disposed at a lower vertical level than the lower surfaces of the first pad separation pattern, and the upper surfaces of the plurality of cell pad structuresmay be disposed at the same vertical level as the upper surface of the first pad separation pattern.

In some example embodiments, the lower surfaces of the plurality of cell pad structuresmay be disposed at a higher vertical level than the lower surfaces of a second pad separation pattern, and the upper surfaces of the plurality of cell pad structuresmay be disposed at the same vertical level as the upper surface of the second pad separation pattern.

In some example embodiments, the plurality of cell pad structuresmay include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

The plurality of second pad separation patternsmay be disposed between two adjacent first pad separation patterns. The plurality of second pad separation patternsmay be disposed adjacent to the cell pad structure. The plurality of second pad separation patternsmay extend in the second direction. The plurality of second pad separation patternsmay have an island-like pattern shape in a plan view. The second pad separation patternmay include, for example, silicon nitride.

A first insulating layerand a second insulating layermay be sequentially disposed on the cell pad structure, the first pad separation pattern, and the second pad separation pattern. In some example embodiments, the first insulating layerand the second insulating layerextend in parallel in the first direction (X direction) and the second direction (Y direction) from the cell array region MCA on the substrateto the boundary region BA and may be flat. The first insulating layermay be, for example, silicon oxide, and the second insulating layermay be, for example, silicon nitride.

A plurality of buried contactsmay be disposed on the plurality of cell pad structures. The plurality of buried contactsmay pass through the first insulating layerand the second insulating layer. The plurality of buried contactsmay be disposed to partially overlap in the third direction (Z direction) corresponding ones of the plurality of cell pad structures, respectively. The plurality of cell pad structuresand the plurality of buried contactsmay connect a capacitor structure (not shown) formed on the plurality of bit lines BL to the first active region ACT.

The plurality of buried contactsmay be electrically insulated from each other by the second insulating patternsurrounding the plurality of buried contacts. The second insulating patternmay include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

A capacitor structure (not shown) may be disposed on the plurality of buried contacts.

A plurality of direct contacts DC may be formed in the plurality of direct contact holes DCH on the substrate. The plurality of direct contacts DC may pass through the first insulating layerand the second insulating layer. The plurality of direct contacts DC may be connected to the plurality of first active regions ACT. The plurality of direct contacts DC may include TiN, TiSiN, W, tungsten silicide, doped polysilicon, or a combination thereof.

The direct contact spacersA may be disposed on both sidewalls of the plurality of direct contacts DC. The direct contact spacerA may cover both sidewalls of the direct contact DC.

The first insulating patternis formed on an inner wall of the direct contact hole DCH and may fill the direct contact hole DCH. The upper surface of the first insulating patternmay be disposed at the same vertical level as the upper surface of the direct contact DC.

A plurality of bit lines BL may extend in the second horizontal direction Y on the substrateand the plurality of direct contacts DC. Each of the plurality of bit lines BL may be connected to the first active region ACTthrough a direct contact DC. The plurality of bit lines BL may include ruthenium (Ru), tungsten (W), cobalt (Co), titanium (Ti), titanium nitride (TiN), or a combination thereof.

The plurality of bit lines BL may be covered with a plurality of insulating capping structures, respectively. The plurality of insulating capping structuresmay extend in the second horizontal direction Y on the plurality of bit lines BL.

A bit line spacerB may be disposed on both sidewalls of each of the plurality of bit lines BL. The bit line spacersB may extend in the second direction (Y direction) on both sidewalls of the plurality of bit lines BL. The bit line spacerB may extend in the third direction (Z direction) on both sidewalls of the plurality of bit lines BL to cover both sidewalls of the insulating capping structure. Although the bit line spacerB is shown as a single material layer in, in some example embodiments, the bit line spacermay be formed in a stacked structure of a plurality of spacer layers (not shown), and at least one of the plurality of spacer layers may be an air spacer.

is a cross-sectional view taken along a line A-A′ ofof a semiconductor deviceaccording to another example embodiment of the inventive concepts.is a cross-sectional view taken along the line B-B′ ofof the semiconductor deviceaccording to another example embodiment of the inventive concepts. Since each configuration of the semiconductor deviceshown inis similar to the corresponding configuration of the semiconductor deviceshown in, the differences therebetween will be mainly described below.

Referring to, as shown in the illustrated line Y, the upper surface of a cell pad structureis disposed at the same or substantially similar vertical level as the upper surface of a second active region ACT, or as shown in the illustrated line Y, the lower surface of the cell pad structureis disposed at the same or substantially similar vertical level as the lower surface of the second active region ACT. This may be accomplished by performing a process of recessing the upper surface of the first active region ACTof the substrateas described later with reference to. Compared with the manufacturing process of the semiconductor devicedescribed with reference to, in the manufacturing process of the semiconductor deviceillustrated in, a recess process, which will be described later with reference to, may be performed until the height of the first active region ACTbecomes lower than before.

In some example embodiments, the lower surfaces of the plurality of cell pad structuresmay be disposed at a lower vertical level than the lower surfaces of the first pad separation pattern, and the upper surfaces of the plurality of cell pad structuresmay be disposed at the same vertical level as the upper surfaces of the first pad separation pattern.

In some example embodiments, the lower surfaces of the plurality of cell pad structuresmay be disposed at a higher vertical level than the lower surfaces of the second pad separation pattern, and the upper surface of the plurality of cell pad structuresmay be disposed at the same vertical level as the upper surface of the second pad separation pattern.

is an enlarged cross-sectional view of a portion PXof.is an enlarged cross-sectional view of a portion corresponding to the portion PXofof a semiconductor deviceaccording to another example embodiment of the inventive concepts.

Referring to, in the semiconductor deviceshown in, in relation to a cross-section of the cell pad structureperpendicular to the second direction (Y direction), a cornerSadjacent to the second pad separation patternamong both corners of the lower surface of the cross-section may be rounded, and the remaining cornerSamong both corners of the lower surface of the cross-section may have an angled. Thus, the cross-section of the cell pad structuremay have a quadrangular shape including a rounded corner. This shape is because a deposition process of forming the cell pad structure, which will be described later with reference to, is performed after the first patterning process of forming the second pad separation pattern, which will be described later with reference to, is first performed.

On the other hand, referring to, in the semiconductor device, a cross-section of a cell pad structureperpendicular to the second direction (Y direction) may have a quadrangular shape in which both cornersSandSof the lower surface of the cross-section are angled. Thus, the cross-section of the cell pad structuremay have a quadrangular shape with angled corners. This shape is because the first patterning process of forming the second pad separation patternto be described later with reference tois performed after the deposition process of forming the cell pad structureto be described later with reference tois first performed.

are cross-sectional views illustrating a method of manufacturing the semiconductor device, according to an example embodiment of the inventive concepts. For example,are enlarged cross-sectional views illustrating portions CXand CXof.

Referring to, a plurality of word line trenchesT may be formed in the substrate, and a gate dielectric film, a gate electrode, and a capping insulating filmP may be sequentially formed in the plurality of word line trenchesT. After that, the first mask pattern Ox used to form the gate dielectric film, the gate electrode, and the capping insulating filmP remains, and a planarization process may be performed so that the upper surface of the capping insulating filmP is disposed at the same vertical level as the upper surface of the first mask pattern Ox. At this time, an upper portion of the capping insulating filmP may be the first pad separation pattern(see) through processes to be described later with reference to, and a lower portion of the capping insulating filmP may be the capping insulating filmincluded in the buried gate structure(refer to). The planarization process may be, for example, a chemical mechanical polishing (CMP) process, but is not limited thereto. Because the remaining first mask pattern Ox is used instead of using a separate mask pattern, the semiconductor device manufacturing process may be simplified and the manufacturing process cost may be reduced. In addition, because the first pad separation pattern(refer to) may be formed in a self-aligning manner, misalignment of the cell pad structure(refer to) may be mitigated or prevented, and reliability of the semiconductor device may be improved.

Referring to, a first patterning process of forming a second pad separation patternmay be performed. For example, a second mask pattern (not shown) having an opening (not shown) is formed on the first mask pattern Ox, and a first patterning process of etching the first mask pattern Ox, the substrate, and the element isolation filmmay be performed using the second mask pattern (not shown) as an etching mask. Thereafter, a second pad separation patternP may be formed by depositing silicon nitride and performing a planarization process. The planarization process may be, for example, a CMP process.

Referring to, the first mask pattern Ox may be recessed. The first mask pattern Ox may be recessed to expose the first active region ACTand the element isolation filmof the substrate.