Forksheet field effect transistor including self-aligned gate

The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to processing methods and resulting structures for forksheet field effect transistors (FETs).

Nanosheet field effect transistors (FETs) are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 7 nm node. Nanosheet FET structures may include a plurality of sheets gated on at least two sides of each of the semiconductor fins, as well as a source region and a drain region adjacent to the fin on opposite sides of the gate. FET structures having n-type source and drain regions may be referred to as nFETs, and FET structures having p-type source and drain regions may be referred to as pFETs.

This need to further minimize N-P spacing has motivated a particular type of nanosheet FET referred to as a “forksheet” FET. The typical forksheet FET process effectively de-tunes the fin etch process and allows for creating a sub-20 nm gap between device fins. The gap is then filled with a dielectric material such as silicon nitride, for example, which forms an isolation wall or dielectric bar that serves as an insulator and etch stop between the N-type and P-type devices.

Various non-limiting embodiments of the invention provide a method of fabrication a semiconductor device. The method includes forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further includes forming an isolation wall in the isolation region, where the isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further includes forming an electrically conductive gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall, and forming a gate interlayer dielectric (ILD) on an upper surface the electrically conductive gate stack such that the wall upper surface contacts the gate ILD.

According to another non-limiting embodiment, a method of fabricating a semiconductor device comprises forming a stack of semiconductor nanosheets on a semiconductor substrate, and performing a nanosheet fin reveal cut process that etches the stack of semiconductor nanosheets to from a first nanosheet fin and a second nanosheet fin. The first and second nanosheet fins are separated by one another by a distance defining an isolation region. The method further comprises forming an isolation wall in the isolation region. The isolation wall extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The method further comprises forming a sacrificial gate stack that surrounds the first nanosheet fin, the second nanosheet fin, and the isolation wall. The method further comprises etching a portion of the sacrificial gate stack and the isolation wall such the a wall upper surface is below an upper surface of the sacrificial gate stack, and replacing the sacrificial gate stack with an electrically conductive gate stack. The electrically conductive gate stack includes a shared gate region between the wall upper surface and an upper surface of the electrically conductive gate.

According to another non-limiting embodiment, a semiconductor device comprises a first stack of nanosheet channels on a semiconductor substrate and a second stack of nanosheet channels on the semiconductor substrate. An isolation wall is interposed between the first stack of nanosheet channels and the second stack of nanosheet channels. The isolation wall separates the first and second stacks of nanosheet channels and extends continuously from a wall based contacting the semiconductor substrate to an opposing wall upper surface. The semiconductor device further includes an electrically conductive gate stack that surrounds the first stack of nanosheet channels, the second stack of nanosheet channels, and the isolation wall. A gate interlayer dielectric (ILD) is on an upper surface the electrically conductive gate stack and contacts the wall upper surface of the isolation wall.

Various non-limiting embodiments of the invention provide a semiconductor device including an isolation wall having a first end contacting the substrate and an opposing second end directly contacting an interlayer dielectric (ILD).

Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.

The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified.

In the accompanying figures and following detailed description of the described embodiments of the invention, the various elements illustrated in the figures are provided with two or three-digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

It is understood in advance that although example embodiments of the invention are described in connection with a particular transistor architecture, embodiments of the invention are not limited to the particular transistor architectures or materials described in this specification. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of transistor architecture or materials now known or later developed.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present invention, known forksheet FET fabrication processes form an isolation region following the fin reveal etch. The isolation region is then subsequently filled with a dielectric material and subsequently etched to form the isolation wall, which is used to separate and electrically insulate neighboring the N-type and P-type devices from one another. As trends continue to further reduce forksheet FET scaling, however, the spacing of the isolation region between neighboring the N-type and P-type devices becomes too small to effectively receive the dielectric material and form the isolation wall.

In addition, known forksheet fabrication processes perform a wall etchback that etches portions of the dielectric wall material to define the isolation wall. A subsequent dielectric via (sometimes referred to as a “CT dielectric”) is then formed on the upper surface of the isolation wall to establish contact with an upper-level interlayer dielectric and complete the electrical isolation between the N-type and P-type devices. However, the interface between the dielectric via and the upper surface of the isolation wall may be susceptible to promoting undesirable gate leakage current. Furthermore, the reduced thickness of the isolation wall resulting from the reduced isolation region spacing (e.g., isolation region spacings less than 20 nm) causes misalignment of the dielectric via with respect to the upper surface of the isolation wall, causing a portion of the dielectric via to contact the N-type and/or P-type and causing isolation failure and undesirable shorting.

Turning now to an overview of aspects of the present invention, one or more non-limiting embodiments of the invention address the above-described shortcomings by providing fabrication methods and resulting structures for a providing a forksheet FET having a reduced isolation wall region (e.g., that can be scaled below 20 nm) compared to conventional forksheet FETS, while still capable of employing an isolation wall that effectively isolates neighboring the N-type and P-type from one another. In one or more non-limiting embodiments, the isolation wall extends continuously from a wall base that contacts the FET substrate to a wall upper surface that directly contacts the ILD layer. In this manner, the dielectric via (i.e., CT dielectric) not required and can be excluded such that dielectric via misalignment issues (i.e., is self-aligned) and the resulting interface between the dielectric via and isolation wall found in conventional forksheet FETs can be avoided.

Turning now to a more detailed description of fabrication operations and resulting structures according to aspects of the invention,depict an semiconductor deviceat an intermediate stage of a fabrication process flow according to a non-limiting embodiment of the present disclosure. In the present specification and claims, an “intermediate” semiconductor device is defined as a semiconductor device in a stage of fabrication prior to a final stage. The semiconductor deviceincludes an nanosheet stackformed on an upper surface of a semiconductor substrate. The semiconductor substrateextends along a first axis (e.g. X-axis) to define length, a second axis (e.g., Y-axis) orthogonal to the X-axis to define a width, and a third axis orthogonal to the first and second axes to define a height.

The nanosheet stackincludes an alternating stack of sacrificial sheetsand active sheets. In one or more non-limiting embodiments, the active sheetscan serve as channel layers as described herein. Although three active sheetsare shown, more or fewer active sheetscan be used, and the number of sacrificial sheetswill be increased or decreased accordingly.

In one or more non-limiting embodiments, the nanosheet stackcan include a bottom sacrificial layerinterposed between the semiconductor baseand a sacrificial sheet. The bottom sacrificial layercan later be transformed into a bottom dielectric isolation (BDI) layer, which serves to reduce, or even completely remove, a problem referred to as “half-sheet”, which creates a potential leakage path between source and drain regions (not shown in) when the bottom sacrificial layeris omitted.

The bottom sacrificial layeris a material that can be replaced (e.g., etched) without etching the sacrificial sheetsand the active sheets. In other words, the bottom sacrificial layeris formed from a material that can be replaced without removing the sacrificial sheetsand active sheets. In one or more non-limiting embodiments, the bottom sacrificial layerincludes silicon germanium (SiGe). To facilitate etching of the bottom sacrificial layerwithout damaging the active sheetsand the sacrificial sheets, the bottom sacrificial layercan be SiGey % where the atomic percent % for “y” ranges from 50-70% atomic percent, while the sacrificial sheetshave a SiGey % of 25%-40%. In an example, “y” in the SiGey % of the layer bottom sacrificial layercan be about (or at least) 65% atomic percent, for example, while “y” in the SiGey % of the sacrificial sheetscan be about (or at least) 30% atomic percent such that the bottom sacrificial layercan be etched without etching the sacrificial sheetsand the active sheets.

In one or more non-limiting embodiments, the sacrificial sheets, the active sheets, and the bottom sacrificial layercan be epitaxially grown. The material of the active sheetscan include, for example, Si. The thickness or height (e.g., along the Z-axis) (e.g., along the Z-axis) of the bottom sacrificial layercan range from about 5 nm to 15 nm, the thickness or height of each sacrificial sheetcan range from about 5 nm to 15 nm, and the thickness or height of each active sheetand the can range from about 5 nm to 15 nm.

Epitaxial materials can be grown from gaseous or liquid precursors using, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. Epitaxial silicon, silicon germanium, and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface will take on a {100} orientation. In some embodiments of the invention, epitaxial growth and/or deposition processes are selective to forming on semiconductor surfaces, and generally do not deposit material on non-crystalline surfaces such as silicon dioxide or silicon nitride.

In some embodiments of the invention, the gas source for the deposition of epitaxial semiconductor material include a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

Turning now to, the semiconductor deviceis illustrated following a fin reveal etch process. The fin reveal etch process can include patterning a lithographic mask (e.g., a thick layer of amorphous silicon (aSi)) formed on an upper surface of the nanosheet stackto form individual mask elements that define an opening between one another. The pattern (e.g., opening) can then be transferred into the exposed nanosheet stackusing an reactive ion etch (RIE) process, for example. Accordingly, a first nanosheet finand a second nanosheet finare formed on the substrateand are separated from one another by an isolation region. The distance (d) (e.g., the width of the isolation region) determines a width or thickness of an isolation wall to be formed in the isolation regionas described in greater detail below. In one or more non-limiting embodiments, the distance (d) between the first nanosheet finand the second nanosheet fin(e.g., the width of the isolation region) ranges, for example, from about 2 nm to about 15 nm.

In one or more non-limiting embodiments, the first nanosheet fincan be utilized to form a first type of semiconductor device and the second nanosheet fincan be utilized to form a second type of semiconductor device different from the first type of semiconductor device. For example, the first nanosheet fincan be used to form a N-FET while the second nanosheet fincan be used to form a P-FET, or vice versa.

In one or more embodiments, shallow trench isolation (STI) regionscan be formed in the substrateand adjacent to the base of the first nanosheet finand the second nanosheet fin. According to an example embodiment, STI regionscan be formed from an oxide material (also referred to herein as an “STI oxide”) such as silicon oxide (SiOx). Although not explicitly shown in the figures, a liner (e.g., a thermal oxide or silicon nitride (SiN)) may be deposited prior to the STI oxide.

Referring to, the semiconductor deviceis illustrated following formation of an isolation wallin the isolation region. In one or more non-limiting embodiments, the isolation wallis formed by overfilling the isolation regionwith a dielectric material such as, for example, silicon nitride (SiN). Accordingly, the isolation wallextends continuously (e.g., without an intervening interface) from a wall base that contacts the substrateto an opposing wall upper surface. The distance from the wall base to the wall upper surface defines a height (h) (e.g., extending along the Z-axis) of the isolation wall.

In one or more non-limiting embodiments, the dielectric material can be deposited in the isolation region using an atomic layer deposition (ALD) process, for example. Accordingly, the isolation wallcan be formed with a height (h) (e.g., along the Z-axis) that is defined by a combination of the height of the first and second nanosheet finsand, along with the vertical thickness (e.g., along the Z-axis) of the masking elements.

In one or more non-limiting embodiments, a chemical-mechanical planarization (sometimes referred to as a chemical-mechanical polishing) (CMP) process can be performed to recess the masking elementsand the isolation wall. In this manner, the height (e.g., along the Z-axis) of the isolation wallcan be defined and tuned to meet a target height.

Turning to, the semiconductor deviceis illustrated after removing the masking elementsfrom the upper surface of the first and second nanosheet finsand. The top view of the semiconductor deviceillustrated inshows designated gate stack regions, which are reserved to support corresponding gate stacks to be formed now that masking elementsare removed.

According to one or more non-limiting embodiments, a hydrofluoric acid (HF) chemical etching process can be used to remove masking elementsformed from an aSi material. Following removal of the masking elements, a protruding portionof the isolation wallextends above the upper surface of the first and second nanosheet finsand. The protruding portionof the isolation wallcan effectively be utilized to establish contact with a subsequently ILD formed on an upper of the subsequently formed gate structure, as described in greater detail below.

With reference now to, the semiconductor deviceis illustrated following the formation of a sacrificial gate stack(sometimes referred to as a “dummy gate stack”) over the first and second nanosheet finsand. The portion of the first and second nanosheet finsandover which sacrificial gate stackis formed are referred to as channel regions. The sacrificial gate stackcan be made of any suitable material, such as, for example, amorphous silicon (aSi) or polysilicon (PC). Any known method for patterning the sacrificial gate can be used, such as, for example, a wet etch, a dry etch, or a combination of sequential wet and/or dry etches.

At this stage of the process flow, a bottom dielectric isolation (BDI) layercan also be formed from the bottom sacrificial layerincluded in the first and second nanosheet finsand. As described herein, bottom sacrificial layercan be replaced with the BDI layerwithout etching the sacrificial sheetsand the active sheetsof the first and second nanosheet finsand.

With continued reference to, a CMP process can be performed to recess the sacrificial gate sacksuch that upper surface of the sacrificial gateis flush (i.e., co-planar) with the upper surface of the isolation wall. Accordingly, the isolation wall serves as a gate cut (e.g., a CT gate cut, or simply a “CT cut”), which separates and electrically isolates the first nanosheet finfrom the second nanosheet fin. In other words, the isolation wallseparates and electrically isolates the first nanosheet finand the portion of the sacrificial gate stackcovering the first nanosheet finfrom the second nanosheet finand the portion of the sacrificial gate stackcovering the second nanosheet fin.

Turning to, the semiconductor deviceis illustrated after forming a hard maskis formed on the sacrificial gate. The hard maskcan be made of any suitable material, such as, for example, a silicon nitride (SiN). The hard maskcan be utilized to preserve the sacrificial gate stackwhile forming the source/drain regionsof the semiconductor device(see).

With continued reference to, the sacrificial sheetsof the first and second nanosheet finsandcan be recessed and inner spacerscan be formed on the recessed sidewalls of the sacrificial sheets. For example, sidewalls of the sacrificial sheetscan be recessed to form cavities (not shown) in the first and second nanosheet finsand. In some embodiments of the invention, the inner spacersare formed on recessed sidewalls of the sacrificial sheetsby filling these cavities with dielectric material. In some embodiments of the invention, portions of the inner spacersthat extend beyond sidewalls of the first and second nanosheet finsandare removed, using, for example, by an isotropic etching process. In this manner, sidewalls of the inner spacersare coplanar (e.g., flush) to sidewalls of the active sheets. In some embodiments of the invention, the inner spacersare formed using a CVD, PECVD, ALD, PVD, chemical solution deposition, or other like processes in combination with a wet or dry etch process. The inner spacerscan be made of any suitable material, such as, for example, a low-k dielectric, a nitride, silicon nitride, silicon dioxide, SiON, SiC, SiOCN, or SiBCN.

In some embodiments of the invention, source and drain regionsare formed on exposed sidewalls of the active sheets. The source and drain regionscan be epitaxially grown using, for example, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable processes. The source and drain regionscan be semiconductor materials epitaxially grown from gaseous or liquid precursors.

In some embodiments of the invention, the gas source for the epitaxial deposition of semiconductor material includes a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, a Si layer can be epitaxially deposited (or grown) from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. A germanium layer can be epitaxially deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. A silicon germanium alloy layer can be epitaxially formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used. In some embodiments of the invention, the epitaxial semiconductor materials include carbon doped silicon (Si:C). This Si:C layer can be grown in the same chamber used for other epitaxy steps or in a dedicated Si:C epitaxy chamber. The Si:C can include carbon in the range of about 0.2 percent to about 3.0 percent.

Epitaxially grown silicon and silicon germanium can be doped by adding n-type dopants (e.g., P or As) or p-type dopants (e.g., Ga, B, BF2, or Al). In some embodiments of the invention, the source and drain regionscan be epitaxially formed and doped by a variety of methods, such as, for example, in-situ doped epitaxy (doped during deposition), doped following the epitaxy, or by implantation and plasma doping. The dopant concentration in the doped regions can range from 1×10cmto 2×10cm, or between 1×10cmand 1×10cm.

As illustrated in, a semiconductor devicecan be illustrated having a forksheet FET having a reduced isolation wall region (e.g., that can be scaled below 20 nm) compared to conventional forksheet FETS, while still capable of employing an isolation wallthat effectively isolates neighboring first and second nanosheet finsand(e.g., a N-type semiconductor device and a P-type semiconductor device) from one another. In the non-limiting embodiment of the invention shown in, the isolation wallextends continuously from a wall base that contacts the substrateto a wall upper surface, which extends above the upper-most surface of the first and second nanosheet finsand. In this manner, the semiconductor deviceis not required to implement a dielectric via (i.e., CT dielectric) such that dielectric via misalignment issues (i.e., is self-aligned) and the resulting interface between the dielectric via and isolation wall found in conventional forksheet FETs can be avoided.

With reference to, the semiconductor deviceis illustrated after performing a replacement metal gate (RMG) process (sometimes referred to as a “gate-first process”. The RMG process involves performing various known masking, etching and deposition processes to replace the sacrificial gatewith a metal gate, e.g., a high-k metal gate (HKMG), which is formed over the channel region of the first and second nanosheet finsand.

Prior to performing the RMG process, the active nanosheetsare released by removing the sacrificial sheets. Once released, the active sheetsserve as the channel region of the first and second nanosheet finsand. In other words, the active nanosheetsretained from the first nanosheet finforms a first stack of nanosheet channelsand the active nanosheetsretained from the second nanosheet finforms a second stack of nanosheet channels. In addition, one or more non-limiting embodiments of the invention forms the wall upper surface of the isolation wallabove the first and second stacks of nanosheet channels.

The sacrificial sheetscan be removed from the active sheets. For example, when the active nanosheetsare formed of silicon and the sacrificial sheetsare formed of SiGe, carboxylic acid/nitric acid/HF chemistry, citric acid/nitric acid/HF, and vapor phased HCl, for example, can be utilized to remove SiGe selective to silicon. In another example, when the active sheetsare formed of SiGe and the sacrificial sheetsare formed of silicon, aqueous hydroxide chemistry, including ammonium hydroxide and potassium hydroxide, for example, can be utilized to remove silicon selective to SiGe.

With continued reference to, the gatecan include a gate dielectric(s) (not shown) and a work function metal stack (not shown). In some embodiments, the gateincludes a main body formed from bulk conductive gate material(s).

In some embodiments of the invention, the gate dielectric is a high-k dielectric film formed on a surface (sidewall) of the active sheets. The high-k dielectric film can be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, high-k materials, or any combination of these materials. Examples of high-k materials include but are not limited to metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k materials can further include dopants such as lanthanum and aluminum. In some embodiments of the invention, the high-k dielectric film can have a thickness of about 0.5 nm to about 4 nm. In some embodiments of the invention, the high-k dielectric film includes hafnium oxide and has a thickness of about 1 nm, although other thicknesses are within the contemplated scope of the invention.

In some embodiments of the invention, the gateincludes one or more work function layers (sometimes referred to as a work function metal stack) formed between the high-k dielectric film and a bulk gate material. In some embodiments of the invention, the gateincludes one or more work function layers, but do not include a bulk gate material.

If present, the work function layers can be made of, for example, aluminum, lanthanum oxide, magnesium oxide, strontium titanate, strontium oxide, titanium nitride, tantalum nitride, hafnium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium silicon nitride, titanium aluminum nitride, tantalum silicon nitride, titanium aluminum carbide, tantalum carbide, and combinations thereof. The work function layer can serve to modify the work function of the gatesand enables tuning of the device threshold voltage. The work function layers can be formed to a thickness of about 0.5 to 6 nm, although other thicknesses are within the contemplated scope of the invention. In some embodiments of the invention, each of the work function layers can be formed to a different thickness. In some embodiments of the invention, the work function layers include a TiN/TiC/TiCAl stack.

In some embodiments, the gateincludes a main body formed from bulk conductive gate material(s) deposited over the work function layers and/or gate dielectrics. The bulk gate material can include any suitable conducting material, such as, for example, metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conducting metallic compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), conductive carbon, graphene, or any suitable combination of these materials. The conductive gate material can further include dopants that are incorporated during or after deposition.

With continued reference to, the metal gatecan be planarized (e.g., using a CMP process) such that the wall upper surface of the isolation wallis co-planar (e.g., flush) with the upper surface of the metal gate. Thereafter, a gate ILDis deposited on the upper surface of the metal gate. The gate ILDcan include any materials known in the art, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, or other dielectric materials. The gate ILDcan be formed using any method known in the art, such as, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

The dielectric material of the gate ILDcan include, but is not limited to, ultra-low-k (ULK) materials, such as, for example, porous silicates, carbon doped oxides, silicon dioxides, silicon nitrides, silicon oxynitrides, carbon-doped silicon oxide (SiCOH) and porous variants thereof, silsesquioxanes, siloxanes, or other dielectric materials.