Cross-domain voltage bus resource sharing for improved power delivery network

Aspects of the present disclosure relate generally to power delivery networks (PDNs) for integrated circuits (ICs), such as system on chip (SoC), and in particular, to a cross-domain voltage bus resource sharing for improved PDN.

An integrated circuit (IC), such as a system on chip (SoC), typically includes a set of cores (e.g., subsystems or circuits), such as a central processing unit (CPU), graphics processing unit (CPU), memory, neural signal processor (NSP), radio frequency (RF) transceiver, modem, input/output (I/O) core, security core, etc. A power management integrated circuit (PMIC) typically provides a set of supply voltages on a set of voltage buses coupled to the set of cores, respectively. The stability of the set of supply voltages including mitigating voltage transients therein is of interest in such power delivery network (PDN).

The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

An aspect of the disclosure relates to an apparatus. The apparatus includes: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

Another aspect of the disclosure relates to a method. The method includes: coupling a bus resource of a first voltage bus to a second voltage bus in response to an actual or predicted voltage transient on the second voltage bus; and decoupling the bus resource from the second voltage bus in response to an absence of the actual or predicted voltage transient on the second voltage bus.

Another aspect of the disclosure relates to an apparatus. The apparatus includes: a power management integrated circuit (PMIC) including first and second voltage regulators; a first voltage bus coupled to the first voltage regulator of the PMIC; a second voltage bus coupled to the second voltage regulator of the PMIC; a first core coupled to the first voltage bus; a second core coupled to the second voltage bus; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to: couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first mode; and couple the bus resource to the second voltage bus based on a second mode.

Another aspect of the disclosure relates to an apparatus. The apparatus includes: a first core; a first voltage bus coupled to the first core; a second core; a second voltage bus coupled to the second core; a bus resource coupled or selectively coupled to the first voltage bus, and selectively coupled to the second voltage bus; and a control circuit configured to couple the bus resource to the first voltage bus and decouple the bus resource from the second voltage bus based on a first priority allowing the first core to share the bus resource and a second priority allowing the second core to borrow the bus resource from the first core.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

illustrates a block diagram of an example power delivery network (PDN)in accordance with an aspect of the disclosure. The PDNincludes a battery V, a power management integrated circuit (PMIC), and a system on chip (SoC), where the PMICand SoCmay be mounted on a printed circuit board (PCB). The PMICincludes a set of voltage regulators (VRs)-to-N configured to generate a set of supply voltages Vddto VddN based on the voltage Vgenerated by the battery. As an example, the set of voltage regulators (VRs)-to-N may include switching regulators (SRs), low-dropout (LDO) regulators, and/or other types of voltage regulators.

The SoC, in turn, includes a set of cores (e.g., subsystems or circuits)-to-N. For example, the set of cores-to-N may include a multimedia (MM) core, a neural signal processing (NSP) core, a graphics processing unit (GPU) core, a central processing unit (CPU) core, a security core, a radio frequency (RF) core, an input/output (I/O) core, and/or other cores. The set of cores-to-N of the SoCmay be coupled to the set of voltage regulators (VRs)-to-N via a set of transmission lines-to-N on the PCB, respectively. Accordingly, for power delivery purpose, the set of cores-to-N may receive the set of supply voltages Vddto VddN from the set of voltage regulators (VRs)-to-N via the set of transmission lines-to-N, respectively.

illustrates a block/schematic diagram of another example power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNmay be an example more detailed implementation of the SoCside of the PDNpreviously discussed. In particular, the PDNincludes a system on chip (SoC), an integrated circuit (IC) package, and a printed circuit board (PCB). The SoCmay be mounted to and within the IC package; and the IC package, in turn, may be mounted on the PCB.

In this example, the SoCincludes an input/output (I/O) coreand a graphics processing unit (GPU) core. It shall be understood that the SoCmay include other different types of cores or a different set of cores. The I/O coreis coupled to a voltage (power) bus (rail)-to receive a supply voltage Vdd_io from, for example, a voltage regulator (VR) of a power management integrated circuit (PMIC), such as PMIC. Similarly, the GPU coreis coupled to a voltage bus-to receive a supply voltage Vdd_gpu from, for example, another voltage regulator (VR) of the PMIC.

The steadiness or stability of the supply voltages Vdd_io and Vdd_gpu is of concern for proper operations of the I/O coreand GPU cores, respectively. If the supply voltages Vdd_io and Vdd_gpu are subjected to voltage transients (e.g., voltage droops, glitches, spikes, undershoots, overshoots, and/or other voltage artifacts) due to different load demands from the I/O coreand GPU core(as well as other sources of noise), the voltage transients may cause problems for the I/O coreand GPU core, respectively. For example, such problems may cause a collapse of the SoC, as well as failed operations of the I/O coreand GPU core, and/or other cores of the SoC.

To mitigate voltage transients on the voltage buses-to-, the PDNmay include various decoupling capacitors. For example, the SoCincludes a first set of one or more on-chip decoupling capacitors Cand Ccoupled between the Vdd_io voltage bus-and ground (a negative voltage rail), and a second set of one or more on-chip decoupling capacitors Cand Ccoupled between the Vdd_gpu voltage bus-and ground. Further, in this regard, the IC packagemay include a first set of one or more IC package (off-chip) decoupling capacitors Ccoupled between the Vdd_io voltage bus-and ground, and a second set of one or more IC package (off-chip) decoupling capacitors Ccoupled between the Vdd_gpu voltage bus-and ground. In a similar vein, the PCBmay include a first set of one or more PCB (off-chip and off-package) decoupling capacitors Ccoupled between the Vdd_io voltage bus-and ground, and a second set of one or more PCB (off-chip and off-package) decoupling capacitors Ccoupled between the Vdd_gpu voltage bus-and ground.

For example, if there is a sudden high load demand from the I/O core, the supply voltage Vdd_io may experience a voltage transient in the form of a voltage droop. As the decoupling capacitors C, C, C, and Care charged to the specified supply voltage Vdd_io, the voltage droop causes a discharging of the decoupling capacitors C, C, C, and Cto provide charges to the Vdd_io voltage bus-to counter the voltage drop. Similarly, if there is a sudden reduction in the load demand from the I/O core, the supply voltage Vdd_io may experience a voltage transient in the form of a voltage spike or overshoot. As the decoupling capacitors C, C, C, and Care charged to the specified supply voltage Vdd_io, the voltage overshoot causes a charging of the decoupling capacitors C, C, C, and Cto remove charges from the Vdd_io voltage bus-to counter the voltage overshoot. In a similar manner, the decoupling capacitors C, C, C, and Cprovide voltage transient mitigation for the Vdd_gpu voltage bus-.

illustrates a cross-sectional view of an example deep trench capacitor (DTC)in accordance with another aspect of the disclosure. The DTCmay be an example of any of the decoupling capacitors discussed herein. In particular, the DTCincludes a substrate (e.g., silicon or p-doped silicon substrate), a well (e.g., an n-doped well)formed at least partially within the substrate, a first (lower) dielectric layer (e.g., silicon dioxide (SiO) or silicon nitride (SiN))formed at least partially within the well, a first (lower) polysilicon layerdisposed over the first dielectric layerat least partially within the well, a second (upper) dielectric layer (e.g., SiOor SiN)disposed over the first polysilicon layerat least partially within the well, and a second (upper) polysilicon layerdisposed over the second dielectric layerat least partially within the well.

The DTCmay include a first metal electrode or terminal(e.g., a metallized via hole through an insulating layer) disposed over and electrically coupled to the second (upper) polysilicon layer. Further, the DTCmay include a second metal electrode or terminal(e.g., a metallized via hole through the insulating layer) disposed and electrically coupled to the well. The first metal electrode or terminalmay be the upper plate of the decoupling capacitor, which may be electrically coupled to the corresponding voltage bus, and the second metal electrode or terminal may be the bottom plate of the decoupling capacitor electrically coupled to ground.

An issue with the PDNpreviously discussed is that typically the sets of decoupling capacitors C-Cand C-Ccoupled to the Vdd_io and Vdd_gpu voltage busses-and-are typically fixed once the corresponding product is shipped. If the number of decoupling capacitors coupled to a voltage bus is not sufficient to properly mitigate voltage transients on the bus due to different load demands from the corresponding core, such voltage transients may impact the operation of the core and the corresponding SoC. Such PDNmay be designed to increase the number of decoupling capacitors coupled to a bus to improve the stability of the supply voltage, but that would consume more chip, package, and PCB area, which may not be desirable.

illustrates a block diagram of an example cross-domain bus resource sharing power delivery network (PDN)in accordance with another aspect of the disclosure. A concept herein is that if a voltage bus is experiencing or is about to experience high load demands that produce or likely to produce voltage transient, the voltage bus may temporarily borrow voltage transient mitigation resources from another voltage bus to better mitigate the actual or predicted voltage transient. Once the high load demand has ended, subsided, or is no longer a factor, the voltage transient mitigation resources may be returned to the sharing voltage bus. Thus, the PDNmay provide improved voltage transient mitigation for voltage buses through this bus resource borrowing/sharing technique without increasing the number of transient mitigating resources on each bus.

In particular, the PDNincludes a first core-(e.g., subsystem or circuit), a second core-(e.g., subsystem or circuit), a first voltage bus Vdd_BUS-coupled to the first core-, and a second voltage bus Vdd_BUS-coupled to the second core-. The PDNfurther includes a first (Vdd) voltage bus resourcecoupled to the first voltage bus Vdd_BUS-, and a second (Vdd) voltage bus resourcecoupled to the second voltage bus Vdd_BUS-. As discussed in more detail further herein, each of the voltage bus resourcesandmay include one or more decoupling capacitors, one or more clamps, electrostatic discharge (ESD) circuit (e.g., one or more ESD diodes), the corresponding supply voltage, and/or other transient mitigating bus resources.

The PDNmay further include a control circuitand at least one switching device SW. The control circuitmay be configured to receive a signal Sindicating whether the supply voltage Vddon the second voltage bus Vdd_BUS-is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand interval). Based on the signal Sindicating no such actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., default configuration or mode), the control circuitgenerates a (e.g., deasserted) control signal CS to open the at least one switching device SW. In such default configuration or mode, the Vddbus resourceof the first voltage bus Vdd_BUS-is not shared with the second voltage bus Vdd_BUS-. In other words, the bus resourcesanddeal with providing supply voltage stability and mitigating voltage transients on their assigned first and second voltage busses Vdd_BUS-and Vdd_BUS-, respectively.

Based on the signal Sindicating an actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., share/borrow configuration or mode), the control circuitgenerates the (e.g., asserted) control signal CS to close the at least one switching device SW so that the Vddbus resourceof the first voltage bus Vdd_BUS-is provided to the second voltage bus Vdd_BUS-(as indicated by the dashed arrow) directly or via the Vddbus resourceto better mitigate the impact or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-. Once the signal Sindicates that the actual or predicted impact on the supply voltage has ended, subsided, or is no longer a factor, the control circuitgenerates the (e.g., deasserted) control signal CS to open the at least one switching device SW to return the Vddbus resourceto the first voltage bus Vdd_BUS-per the default configuration or mode.

The PDNmay optionally include a communication link (e.g., IS, or other)from the control circuitto the corresponding PMIC (e.g., PMIC) to inform it of the bus resource sharing/borrowing event. The PMIC may use such information to modify its operations with respect to the supply voltages Vddand Vddfor the first and/or second voltage buses-and-, respectively. For example, if there are frequent supply voltage impacting events for the second voltage bus-, the PMIC may provide additional resources on the second voltage bus-, as well as additional sharing resources for the first voltage bus-(e.g., increase its supply voltage). Although not explicitly shown in other PDNs described herein, such communication linkmay be provided in such PDNs as well.

Although, in this example, the power domain of the first core-is sharing its Vddbus resourcewith the power domain of the second core-(e.g., cross-domain resource sharing), it shall be understood that the PDNmay be configured to selectively implement bidirectional bus resource sharing between the first and second power domains, where the Vddbus resourcemay be shared with the first voltage bus Vdd_BUS-.

illustrates a block/schematic diagram of an example cross-domain decoupling capacitor sharing power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNmay be an example of a specific implementation of the PDNpreviously discussed. In this example, the voltage bus resource that is being shared/borrowed is one or more decoupling capacitors.

In particular, the PDNincludes a first core-(e.g., subsystem or circuit), a second core-(e.g., subsystem or circuit), a first voltage bus Vdd_BUS-coupled to the first core-, and a second voltage bus Vdd_BUS-coupled to the second core-. The PDNfurther includes a first set of one or more decoupling capacitors Cincluding a top plate or terminal selectively coupled to the first voltage bus Vdd_BUS-via a first switching device SW, and selectively coupled to the second voltage bus Vdd_BUS-via an optional diode D or a voltage level shifter (LS)and a second switching device SW. The first set of one or more decoupling capacitors Cincludes a bottom plate or terminal coupled to ground. The PDNfurther includes a second set of one or more capacitors Ccoupled between the second voltage rail Vdd_BUS-and ground. The first and second sets of one or more decoupling capacitors Cand Cmay be one or more on-chip capacitors, one or more IC package (off-chip) capacitors, and/or one or more PCB (off-chip and off-package) capacitors.

The PDNmay further include a control circuitconfigured to receive a signal Sindicating whether the supply voltage Vddon the second voltage bus Vdd_BUS-is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sindicating no such actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., default configuration or mode), the control circuitgenerates a first (e.g., asserted) control signal CSto close the first switching device SWand a second (e.g., deasserted) control signal CSto open the second switching device SW. In such default configuration or mode, the first set of one or more decoupling capacitors Cis coupled to the first voltage bus Vdd_BUS-, and decoupled from the second voltage bus Vdd_BUS-. Thus, the first set of one or more decoupling capacitors Cis mitigating voltage transients and providing stability to the supply voltage Vddon the first voltage bus Vdd_-.

Based on the signal Sindicating an actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., share/borrow configuration or mode), the control circuitgenerates the first (e.g., deasserted) control signal CSto open the first switching device SWand the second (e.g., asserted) control signal CSto close the second switching device SW. In such share/borrow configuration or mode, the first set of one or more decoupling capacitors Cis decoupled from the first voltage bus Vdd_BUS-, and coupled to the second voltage bus Vdd_BUS-to assist the second set of one or more decoupling capacitors Cin mitigating voltage transient and providing stability to the supply voltage Vddon the second voltage bus Vdd_BUS-. Then, based on the signal Sindicating that the actual or predicted impact on the supply voltage Vddhas ended, subsided, or is no longer a factor, the control circuitgenerates the first (e.g., asserted) control signal CSto close the first switching device SWand the second (e.g., deasserted) control signal CSto open the second switching device SWto reconfigure the PDNback to the default configuration or mode.

The supply voltage Vddon the first voltage bus Vdd_BUS-(e.g., the sharing voltage bus) should be substantially the same or higher than the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., the borrowing voltage bus) to improve the transient mitigation on the second voltage bus Vdd_BUS-. The optional diode D or level shifter (LS)may provide an appropriate voltage drop and unidirectional current for a smooth sharing of the decoupling capacitor Cwith the second voltage bus Vdd_BUS-.

Although, in this example, the power domain of the first core-is sharing its first set of one or more decoupling capacitors Cwith the power domain of the second core-(e.g., cross-domain resource sharing), it shall be understood that the PDNmay be configured to selectively implement bidirectional bus resource (e.g., decoupling capacitors) sharing between the first and second power domains (e.g., the second set of one or more decoupling capacitors Cmay be selectively coupled to the first voltage bus Vdd_BUS-, and decoupled from the second voltage bus Vdd_BUS-).

illustrates a block/schematic diagram of another example cross-domain decoupling capacitor sharing power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNis a variation of PDNpreviously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “6” for PDNinstead of a “5” as in PDN. The PDNdiffers from PDNin that PDNincludes a selectable bank of decoupling capacitors Cto Cpertaining to the power domain of the first voltage bus Vdd_BUS-that may be shared with (borrowed by) the power domain of the second voltage bus Vdd_BUS-.

More specifically, the set of decoupling capacitors Cto Care coupled in series with a set of switching devices SWto SWbetween the first switching device SWand ground, respectively. The control circuitis configured to generate a set of control signals CSto CSseparately control the open/closed states of the set of switching devices SWto SW, respectively. For example, in default configuration or mode as indicated by signal S, the control circuitmay generate the control signals CS, CS, and CS-CSto close the first switching device SW, to close the set of switching devices SWto SW, and to open the second switching device SW. In this default configuration or mode, the bank of decoupling capacitors Cto Care fully coupled to the first voltage bus Vdd_BUS-to deal with voltage transient in the first supply voltage Vdd. It shall be understood that, in default configuration or mode, less than the entire set of decoupling capacitors Cto Cmay be coupled to the voltage bus Vdd_BUS-by keeping one or more of the set of switching devices SWto SWopen.

Based on the signal Sindicating an actual or predicted voltage transient on the supply voltage Vddon the second voltage bus Vdd_BUS-, the control circuitmay generate the generate the control signals CS, CS, and CS-CSto open the first switching device SW, to close one or more of the set of switching devices SWto SW, and to close the second switching device SW. In this share/borrow configuration or mode, one or more of the bank of decoupling capacitors Cto Care coupled to the second voltage bus Vdd_BUS-to assist the second set of one or more decoupling capacitors Cin mitigating the voltage transients in the second supply voltage Vdd.

The number of switching devices SWto SWthat are closed may be based on different conditions (e.g., the voltage difference between Vddand Vdd), and may also be dynamic. For example, if the signal Sindicates a fairly mild voltage transient on the second voltage bus Vdd_BUS-, the control circuitmay generate the control signal CS-CSto close only one or a few of the switching devices SWto SWso that the corresponding one or few decoupling capacitors Cto Care coupled to the second voltage bus Vdd_BUS-to mitigate the mild voltage transient on the second voltage bus Vdd_BUS-. Conversely, if the signal Sindicates an aggressive voltage transient on the second voltage bus Vdd_BUS-, the control circuitmay generate the control signal CS-CSto close most or all of the switching devices SWto SWso that the corresponding most or all of the decoupling capacitors Cto Care coupled to the second voltage bus Vdd_BUS-to mitigate the harsh voltage transient on the second voltage bus Vdd_BUS-.

As mentioned, the coupling of the set of decoupling capacitors Cto Cby closing the corresponding set of switching devices SWto SWmay be dynamic. For example, during a Vddtransient mitigation event, the control circuitmay generate the control signal CS-CSto progressively close the set of switching devices SWto SWto provide a smooth progressive coupling of the set of decoupling capacitors Cto Cto the second voltage bus Vdd_BUS-. When the signal Sindicates that the transient mitigation event has ended, subsided, or is no longer a factor, the control circuitmay generate the control signal CS-CSto progressively open the set of switching devices SWto SWto provide a smooth progressive decoupling of the set of decoupling capacitors Cto Cfrom the second voltage bus Vdd_BUS-. Further, based on the signal Sindicating that the transient mitigation event has ended, subsided, or is no longer a factor, the control circuitmay generate the control signals CS, CS, and CS-CSto close the switching device SW, open the switching device SW, and close the number of switching devices SWto SWpursuant to the default configuration or mode.

Although, in this example, the power domain of the first core-is sharing its selectable bank of decoupling capacitors Cto Cwith the power domain of the second core-(e.g., cross-domain resource sharing), it shall be understood that the PDNmay be configured to selectively implement bidirectional bus resource (e.g., bank of selectable decoupling capacitors) sharing between the first and second power domains (e.g., the second set of one or more decoupling capacitors Cmay be implemented as a selectable bank of decoupling capacitors, which may be selectively coupled to the first voltage bus Vdd_BUS-, and decoupled from the second voltage bus Vdd_BUS-).

illustrates a block/schematic diagram of an example cross-domain supply voltage sharing power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNmay be an example of a specific implementation of the PDNpreviously discussed. In this example, the voltage bus resource that is being shared/borrowed is the supply voltage itself.

In particular, the PDNincludes a first core-(e.g., subsystem or circuit), a second core-(e.g., subsystem or circuit), a first voltage bus Vdd_BUS-coupled to the first core-, and a second voltage bus Vdd_BUS-coupled to the second core-. The PDNfurther includes a set of one or more decoupling capacitors C including a top plate or terminal coupled to the second voltage bus Vdd_BUS-. The set of one or more decoupling capacitors C may be one or more on-chip capacitors, one or more IC package (off-chip) capacitors, and/or one or more PCB (off-chip and off-package) capacitors. The PDNfurther includes a first switching device SWcoupled between the first voltage bus Vdd_BUS-and a bottom plate of the set of one or more decoupling capacitors C. Additionally, the PDNincludes a second switching device SWcoupled between the bottom plate of the set of one or more decoupling capacitors C and ground.

The PDNmay further include a control circuitconfigured to receive a signal Sindicating whether the supply voltage Vddon the second voltage bus Vdd_BUS-is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sindicating no such actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., default configuration or mode), the control circuitgenerates a first (e.g., deasserted) control signal CSto open the first switching device SWand a second (e.g., asserted) control signal CSto close the second switching device SW. In such default configuration or mode, the first supply voltage Vddof the first voltage bus Vdd_BUS-is not shared with the second voltage bus Vdd_BUS-, and the set of one or more capacitors C each operate as a decoupling capacitor.

Based on the signal Sindicating an actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., share/borrow configuration or mode), the control circuitgenerates the first (e.g., asserted) control signal CSto close the first switching device SWand the second (e.g., deasserted) control signal CSto open the second switching device SW. In such share/borrow configuration or mode, the first supply voltage Vddis provided to the bottom plate of the set of one or more capacitors C to boost the second supply voltage Vddon the second voltage bus Vdd_BUS-by the first supply voltage Vddto assist in mitigating the voltage transient on the second voltage bus Vdd_BUS-. In such case, each of the set of one or more capacitors C has been reconfigured as a voltage boosting capacitor.

Then, based on the signal Sindicating that the actual or predicted impact on the supply voltage Vddhas ended, subsided, or no longer a factor, the control circuitgenerates the first (e.g., deasserted) control signal CSto open the first switching device SWand the second (e.g., asserted) control signal CSto close the second switching device SWto reconfigure the PDNback to the default configuration or mode.

Although, in this example, the power domain of the first core-is sharing its supply voltage Vddwith the power domain of the second core-(e.g., cross-domain resource sharing), it shall be understood that the PDNmay be configured to selectively implement bidirectional bus resource (e.g., supply voltage) sharing between the first and second power domains (e.g., the supply voltage Vddselectively provided to the first voltage bus Vdd_BUS-).

illustrates a block/schematic diagram of an example cross-domain voltage clamp sharing power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNmay be an example of a specific implementation of the PDNpreviously discussed. In this example, the voltage bus resource that is being shared/borrowed is a voltage clamp.

In particular, the PDNincludes a first core-(e.g., subsystem or circuit), a second core-(e.g., subsystem or circuit), a first voltage bus Vdd_BUS-coupled to the first core-, and a second voltage bus Vdd_BUS-coupled to the second core-. The PDNfurther includes a voltage clampselectively coupled to the first voltage bus Vdd_BUS-via a first switching device SW, and selectively coupled to the second voltage bus Vdd_BUS-via a second switching device SW. The voltage clampis coupled between the first and second switching devices SWand SWand ground.

The PDNmay further include a control circuitconfigured to receive a signal Sindicating whether the supply voltage Vddon the second voltage bus Vdd_BUS-is being impacted (e.g., subjected to a voltage transient) or may be predictably impacted (e.g., an upcoming high load demand time interval). Based on the signal Sindicating no such actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., default configuration or mode), the control circuitgenerates a first (e.g., asserted) control signal CSto close the first switching device SWand a second (e.g., deasserted) control signal CSto open the second switching device SW. In such default configuration or mode, the voltage clampis coupled to the first voltage bus Vdd_BUS-, and decoupled from the second voltage bus Vdd_BUS-. Thus, the voltage clampmay mitigate voltage transients (e.g., spikes or overshoots) in the supply voltage Vddon the first voltage bus Vdd_BUS-.

Based on the signal Sindicating an actual or predicted impact on the supply voltage Vddon the second voltage bus Vdd_BUS-(e.g., share/borrow configuration or mode), the control circuitgenerates the first (e.g., deasserted) control signal CSto open the first switching device SWand the second (e.g., asserted) control signal CSto close the second switching device SW. In such share/borrow configuration or mode, the voltage clampis decoupled from the first voltage bus Vdd_BUS-, and coupled to the second voltage bus Vdd_BUS-to assist in mitigating voltage transients (e.g., spikes or overshoots) and provide stability to the supply voltage Vddon the second voltage bus Vdd_BUS-. Then, based on the signal Sindicating that the actual or predicted impact on the supply voltage Vddhas ended, subsided, or is no longer a factor, the control circuitgenerates the first (e.g., asserted) control signal CSto close the first switching device SWand the second (e.g., deasserted) control signal CSto open the second switching device SWto reconfigure the PDNback to the default configuration or mode.

Although, in this example, the power domain of the first core-is sharing its voltage clampwith the power domain of the second core-(e.g., cross-domain resource sharing), it shall be understood that the PDNmay be configured to selectively implement bidirectional bus resource (e.g., voltage clamp) sharing between the first and second power domains (e.g., a voltage clamp assigned to the second voltage bus Vdd_BUS-selectively coupled to the first voltage bus Vdd_BUS-and decoupled from the second voltage bus Vdd_BUS-).

illustrates a block diagram of an example cross-domain bus resource sharing with voltage transient detection power delivery network (PDN)in accordance with another aspect of the disclosure. The PDNis a variation of PDNpreviously discussed, and includes many of the same/similar elements as indicated by the same reference indicators and numbers but with the most significant digit being a “9” for PDNinstead of a “4” as in PDN.

The PDNfurther includes a voltage transient detectorconfigured to detect a voltage transient on the second voltage bus Vdd_BUS-. In this regard, the voltage transient detectorincludes an input coupled to the second voltage bus Vdd_BUS-, and an output coupled to an input of the control circuitto provide the signal Sthereto. In this example, the signal Smay indicate an actual voltage transient occurring on the second voltage bus Vdd_BUS-, as opposed to a predicted voltage transient.