Array substrate and display panel

This application claims priority to Chinese Application No. 202222636126.0, filed on Sep. 30, 2022. The entire disclosure of the above application is incorporated herein by reference.

The present disclosure relates to the field of display technology, more specifically to an array substrate and a display panel.

With the development of 5G communication technology, virtual reality (VR) technology is in a period of rapid development due to improvement of content and hardware. VR technology has high requirements for the pixel density of the display panel (specifically requiring the pixel density of the display panel to be greater than 1000), but the existing display panel with a pixel density greater than 1000 has serious signal crosstalk. The photogenerated leakage current generated by the thin film transistors (TFTs) of the display panel will cause signal crosstalk, thereby affecting the display quality of the display panel. In view of this, it is necessary to solve the signal crosstalk problem of display panels with high pixel density.

The present disclosure provides an array substrate and a display panel to improve the signal crosstalk problem of a high pixel density display panel.

According to a first aspect of the present disclosure, an array substrate includes a substrate, an active layer disposed on the substrate, a first insulating layer disposed on a side of the active layer away from the substrate, a first anti-reflective coating layer disposed on a side of the first insulating layer away from the substrate, a second insulating layer disposed on a side of the first anti-reflective coating layer away from the substrate, a source disposed on a side of the second insulating layer away from the substrate, and a drain disposed on the side of the second insulating layer away from the substrate. The source includes a first electrode portion connected to the active layer by a first hole through the first insulating layer and the second insulating layer, and a second electrode portion connected to the first electrode portion. The drain includes a third electrode portion and fourth electrode portion. The third electrode portion is connected to the active layer through a second hole through the first insulating layer and the second insulating layer. The fourth electrode portion is connected to the third electrode portion. An orthographic projection of the second electrode portion or the fourth electrode portion on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

Optionally, the active layer includes a first connecting portion, a conductive channel, and a second connecting portion. The first connecting portion is connected to the first electrode portion through the third hole through the first insulating layer and the second insulating layer. The second connecting portion is connected to the third electrode through the fourth hole through the first insulating layer and the second insulating layer. An orthographic projection of the conductive channel on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

Optionally, the array substrate further includes a shading electrode disposed on the substrate, and a buffer layer, disposed on a side of the shading electrode away from the substrate. The active layer is disposed on a side of the buffer layer away from the substrate, and an orthographic projection of the shading electrode on the substrate overlaps with on the orthographic projection of the conductive channel on the substrate.

Optionally, the array substrate further includes a second anti-reflective coating layer, a gate, and an interlayer dielectric layer. The second anti-reflective coating layer is disposed on a side of the first insulating layer away from the substrate. The gate is disposed on a side of the second anti-reflective coating layer away from the substrate. The interlayer dielectric layer is disposed on a side of the gate away from the substrate. The first anti-reflective coating layer is disposed on a side of the interlayer dielectric layer away from the substrate. An orthographic projection of the second anti-reflective coating layer on the substrate overlaps an orthographic projection of the gate on the substrate, and an orthographic projection of the active layer on the substrate overlaps an orthographic projection of the shading electrode on the substrate.

Optionally, the second anti-reflective coating layer is a metal oxide layer.

Optionally, the array substrate further includes a third anti-reflective coating layer which is disposed on a side of the shading electrode away from the substrate and covered by the buffer layer. An orthographic projection of the third anti-reflective coating layer on the substrate overlaps an orthographic projection of the active layer on the substrate, and an orthographic projection of the shading electrode on the substrate overlaps the orthographic projection of the active layer on the substrate.

Optionally, the array substrate further includes a first metal layer. The first metal layer is disposed on the second insulating layer. The first metal layer includes the source and the drain.

Optionally, the array substrate further includes a third insulating layer which is disposed on the side of the source away from the substrate. The drain is disposed on a side of the third insulating layer away from the substrate.

Optionally, the first anti-reflective coating layer is a metal oxide layer.

According to a second aspect of the present disclosure, a display panel includes an array substrate. The array substrate includes a substrate, an active layer disposed on the substrate, a first insulating layer disposed on a side of the active layer away from the substrate, a first anti-reflective coating layer disposed on a side of the first insulating layer away from the substrate, a second insulating layer disposed on a side of the first anti-reflective coating layer away from the substrate, a source disposed on a side of the second insulating layer away from the substrate, and a drain disposed on the side of the second insulating layer away from the substrate. The source includes a first electrode portion connected to the active layer by a first hole through the first insulating layer and the second insulating layer, and a second electrode portion connected to the first electrode portion. The drain includes a third electrode portion and fourth electrode portion. The third electrode portion is connected to the active layer through a second hole through the first insulating layer and the second insulating layer. The fourth electrode portion is connected to the third electrode portion. An orthographic projection of the second electrode portion or the fourth electrode portion on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

Optionally, the active layer includes a first connecting portion, a conductive channel, and a second connecting portion. The first connecting portion is connected to the first electrode portion through the third hole through the first insulating layer and the second insulating layer. The second connecting portion is connected to the third electrode through the fourth hole through the first insulating layer and the second insulating layer. An orthographic projection of the conductive channel on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

Optionally, the array substrate further includes a shading electrode disposed on the substrate, and a buffer layer, disposed on a side of the shading electrode away from the substrate. The active layer is disposed on a side of the buffer layer away from the substrate, and an orthographic projection of the shading electrode on the substrate overlaps with on the orthographic projection of the conductive channel on the substrate.

Optionally, the array substrate further includes a second anti-reflective coating layer, a gate, and an interlayer dielectric layer. The second anti-reflective coating layer is disposed on a side of the first insulating layer away from the substrate. The gate is disposed on a side of the second anti-reflective coating layer away from the substrate. The interlayer dielectric layer is disposed on a side of the gate away from the substrate. The first anti-reflective coating layer is disposed on a side of the interlayer dielectric layer away from the substrate. An orthographic projection of the second anti-reflective coating layer on the substrate overlaps an orthographic projection of the gate on the substrate, and an orthographic projection of the active layer on the substrate overlaps an orthographic projection of the shading electrode on the substrate.

Optionally, the second anti-reflective coating layer is a metal oxide layer.

Optionally, the array substrate further includes a third anti-reflective coating layer which is disposed on a side of the shading electrode away from the substrate and covered by the buffer layer. An orthographic projection of the third anti-reflective coating layer on the substrate overlaps an orthographic projection of the active layer on the substrate, and an orthographic projection of the shading electrode on the substrate overlaps the orthographic projection of the active layer on the substrate.

Optionally, the array substrate further includes a first metal layer. The first metal layer is disposed on the second insulating layer. The first metal layer includes the source and the drain.

Optionally, the array substrate further includes a third insulating layer which is disposed on the side of the source away from the substrate. The drain is disposed on a side of the third insulating layer away from the substrate.

Optionally, the first anti-reflective coating layer is a metal oxide layer.

According to a third aspect of the present disclosure, an array substrate includes a substrate, an active layer disposed on the substrate, a first insulating layer disposed on the active layer, a first anti-reflective coating layer disposed on the first insulating layer, a second insulating layer disposed on the first anti-reflective coating layer, a source disposed on the second insulating layer, a drain disposed on the second insulating layer. An orthographic projection of the source or the drain on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

Optionally, the active layer includes a first connecting portion, a conductive channel, and a second connecting portion. The first connecting portion is connected to the first electrode portion through the third hole through the first insulating layer and the second insulating layer. The second connecting portion is connected to the third electrode through the fourth hole through the first insulating layer and the second insulating layer. An orthographic projection of the conductive channel on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate.

The present disclosure provides an array substrate and a display panel. The array substrate includes a substrate, an active layer disposed on the substrate, a first insulating layer disposed on a side of the active layer away from the substrate, a first anti-reflective coating layer disposed on a side of the first insulating layer away from the substrate, a second insulating layer disposed on a side of the first anti-reflective coating layer away from the substrate, a source disposed on a side of the second insulating layer away from the substrate, and a drain disposed on the side of the second insulating layer away from the substrate. The source includes a first electrode portion connected to the active layer by a first hole through the first insulating layer and the second insulating layer, and a second electrode portion connected to the first electrode portion. The drain includes a third electrode portion and fourth electrode portion. The third electrode portion is connected to the active layer through a second hole through the first insulating layer and the second insulating layer. The fourth electrode portion is connected to the third electrode portion. An orthographic projection of the second electrode portion or the fourth electrode portion on the substrate overlaps with an orthographic projection of the first anti-reflective coating layer on the substrate. The present disclosure is provided with the first anti-reflective coating layer, and the orthographic projection of the first anti-reflective coating layer on the substrate overlaps with the orthographic projection of the second electrode portion or the fourth electrode portion on the substrate, so that the second electrode portion and the fourth electrode portion can be avoided from reflecting light to the active layer, thereby reducing the photoleakage current of the active layer, and improving the signal crosstalk problem of the display panel with high pixel density.

To help a person skilled in the art better understand the solutions of the present disclosure, the following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are a part rather than all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present disclosure.

The term “first”, “second” are for illustrative purposes only and are not to be construed as indicating or imposing a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature that limited by “first”, “second” may expressly or implicitly include at least one of the features.

In the description of the present disclosure, the meaning of “plural” is two or more, unless otherwise specifically defined.

Throughout the specification and claims, when it is described that an element is “connected” to another element, the element may be “directly connected” to the other element, or “electrically connected” to the other element through a third element.

Furthermore, the term “comprising” will be understood as meaning the inclusion of elements but not the exclusion of any other elements, unless explicitly described to the contrary.

The following disclosure provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, the components and settings of specific examples are described below. They are for example purposes only and are not intended to limit this application. Further, the present disclosure may repeat reference numbers and/or reference letters in different examples, such duplication is for the purpose of simplification and clarity, and does not by itself indicate the relationship between the various embodiments and/or settings discussed. Further, the present disclosure provides various examples of specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and/or the use of other materials. The following are described in detail, it should be noted that the order of description of the following embodiments is not used as a qualification for the preferred order of embodiments.

Referring to,is a schematic diagram of the array substrateaccording to a first embodiment of the present disclosure. The first embodiment of the present disclosure is directed to an array substrate. The array substrateincludes a substrate, an active layer, a first insulating layer, a first anti-reflective coating layer, a second insulating layer, a source, and a drain.

The active layeris disposed on the substrate. The first insulating layeris disposed on the side of the active layeraway from the substrate. The first anti-reflective coating layeris disposed on the side of the first insulating layeraway from the substrate. The second insulating layeris disposed on the side of the first anti-reflective coating layeraway from the substrate. The sourceis disposed on the side of the second insulating layeraway from the substrate. The sourceincludes a first electrode portionand a second electrode portion. The first electrode portionis electrically connected to the active layerby a first hole through the first insulating layerand the second insulating layer. The drainis disposed on the side of the second insulating layeraway from the substrate. The drainincludes a third electrode portionand a fourth electrode portion. The third electrode portionis electrically connected to the active layerby a second hole through the first insulating layerand the second insulating layer.

An orthographic projection of the sourceor the drainon the substrateoverlaps with an orthographic projection of the first anti-reflective coating layeron the substrate. Optionally, the orthographic projection of at least one of the second electrode portionand the fourth electrode portionon the substrateoverlaps with the orthographic projection of the first anti-reflective coating layeron the substrate.

Anti-reflective coating layer is used to reduce reflected light to improve light transmission. Further, in the present embodiment, the orthographic projections of the second electrode portionand the fourth electrode portionon the substrateoverlaps with the orthographic projection of the first anti-reflective coating layeron the substrate.

Since the photoleakage current generated by the TFT device of the existing display panel will cause signal crosstalk, it is known that the light received by the active layerof the TFT device of the display panel is mainly reflected from the metal layer in the display panel. Therefore, in order to solve the above technical problems, because the orthographic projection of the first anti-reflective coating layeron the substrateoverlaps with the orthographic projection of the second electrode portionor the fourth electrode portionon the substrate, the second electrode portionand the fourth electrode portionare used to preventing light from reflecting to the active layer, thereby reducing the photoleakage current of the active layer. This improves signal crosstalk in display panels with high pixel density.

In some embodiments, the array substratefurther includes a gateand an interlayer dielectric layer.

The gateis disposed on the side of the first insulating layeraway from the substrate. The interlayer dielectric layeris disposed on the side of the gateaway from the substrate. The first anti-reflective coating layeris disposed on the side of the interlayer dielectric layeraway from the substrate.

In some embodiments, the array substratefurther includes a first metal layer. The first metal layer is disposed on the side of the second insulating layeraway from the substrate. The first metal layer comprises the sourceand the drain.

In the present embodiment, the sourceand the drainare disposed on the same layer of metal to reduce the thickness of the display panel.

Further, in some embodiments, the array substratefurther includes a passivation layer, a second metal layer, a fourth insulating layer, and a third metal layer.

The passivation layeris disposed on the side of the first metal layer away from the substrate. The second metal layer is disposed on the side of the passivation layeraway from the substrate. The second metal layer comprises a pixel electrodeelectrically connected to the drain. The fourth insulating layeris disposed on the side of the second metal layer away from the substrate. The fourth insulating layeris an inorganic insulating layer. The third metal layer is disposed on the side of the fourth insulating layeraway from the substrate. The third metal layer comprises a common electrode.

Further, in some embodiments, the active layercomprises a first connecting portion, a conductive channeland a second connecting portionconnected. The first electrode portionis electrically connected to the first connecting portionby a third hole through the first insulating layerand the second insulating layer. The third electrode portionis connected to the second connecting portionthrough a fourth hole through the first insulating layerand the second insulating layer.

An orthographic projection of the conductive channelon the substrateoverlaps with an orthographic projection of the first anti-reflective coating layeron the substrate.

Since there are other metal electrodes in the display panel, such as pixel electrodes and common electrodes, these metal electrodes are also located above the active layer, so light is also reflected to the active layer. Because the orthographic projection of the conductive channelon the substrateoverlaps the orthographic projection of the first anti-reflective coating layeron the substrate, the present disclosure can reduce the light reflected to the active layerby other metal layers in the display panel except the second electrode portionand the fourth electrode portion. The photoleakage current of the active layermay be further reduced.

Further, in some embodiments, the array substratefurther comprises a shading electrodeand a buffer layer. The shading electrodeis disposed on the substrate. The buffer layeris disposed on the side of the shading electrodeaway from the substrate. The active layeris disposed on the side of the buffer layeraway from the substrate. An orthographic projection of the shading electrodeon the substrateoverlaps an orthographic projection of the conductive channelon the substrate.

Because the orthographic projection of the shading electrodeon the substrateoverlaps the orthographic projection of the conductive channelon the substrate, the light emitted from the backlight module is not incident to the conductive channel, so that the photoleakage current of the active layercan be further reduced.

Further, in some embodiments, the material of the first anti-reflective coating layercomprises a metal oxide. Optionally, the material of the first anti-reflective coatingis molybdenum oxide.

Accordingly, another embodiment of the present disclosure also provides a manufacturing method for an array substrate. First, the shading electrodeis formed on the substrate. The buffer layeris formed on the shading electrode. The active layeris formed on the buffer layer. The orthographic projection of the active layeron the substrateoverlaps an orthographic projection the shading electrodeon the substrate. The first insulating layeris formed on the active layer. The gateis formed on the first insulating layer. The interlayer dielectric layeris formed on the gate. The first anti-reflective coating layeris formed on the interlayer dielectric layer. The second insulating layeris formed on the first anti-reflective coating layer.

The first metal layer is formed on the second insulating layer. The first metal layer comprises the sourceand the drain. The sourcecomprises a first electrode portionand a second electrode portion. The first electrode portionis connected to the active layerthrough a third hole through the first insulating layerand the second insulating layer. The drainincludes a third electrode portionand a fourth electrode portion. The third electrode portionis connected to the active layerthrough a fourth hole through the first insulating layerand the second insulating layer. An orthographic projection of the second electrode portionor the fourth electrode portionon the substrateoverlaps with an orthographic projection of the first anti-reflective coating layeron the substrate.