Semiconductor device, electronic device, and vehicle

This nonprovisional application is a continuation application of International Patent Application No. PCT/JP2022/025736 filed on Jun. 28, 2022, which claims priority Japanese Patent Application No. 2021-156468 filed on Sep. 27, 2021, the entire contents of which are hereby incorporated by reference.

The disclosure herein relates to semiconductor devices, and to electronic devices and vehicles that employ semiconductor devices.

The present applicant has been proposing and developing a number of new technologies directed to semiconductor devices such as vehicle onboard IPDs (intelligent power devices) (see, for example, Patent Document 1 identified below).

<Semiconductor Device>

Hereinafter, various embodiments directed to semiconductor devices will be described with reference to the accompanying drawings.

is a perspective view of a semiconductor deviceas seen from one direction. While the embodiments described below deal with examples where the semiconductor deviceis a high-side switching device, this is not meant to limit the semiconductor deviceto a high-side switching device. With appropriate adjustments made to the electrical connections or the functions of its structural parts, the semiconductor devicecan be provided also as a low-side switching device.

Referring to, the semiconductor deviceincludes a semiconductor layer. The semiconductor layercontains silicon. The semiconductor layeris formed in the shape of a rectangular parallelepiped chip. The semiconductor layerhas a first main surfaceon one side, a second main surfaceon the other side, and side surfacesA,B,C, andD that connect between the first main surfaceand the second main surface.

The first and second main surfacesandare each formed in a rectangular shape in a plan view as seen from the normal direction Z to it (hereinafter, simply referred to as “in a plan view”). The side surfacesA andC extend along a first direction X and face each other in a second direction Y which intersects the first direction X. The side surfacesB andD extend along the second direction Y and face each other in the first direction X. More specifically, the second direction Y is orthogonal to the first direction X.

In the semiconductor layer, an output regionand an input regionare defined. The output regionis defined as a region near the side surfaceC. The input regionis defined as a region rear the side surfaceA. In a plan view, the area SOUT of the output regionis equal to or larger than the area SIN of the input region(SIN≤SOUT).

The ratio SOUT/SIN of the area SOUT to the area SIN can be 1 or more but 10 or less (1≤SOUT/SIN≤10). The ratio SOUT/SIN can be 1 or more but 2 or less, or 2 or more but 4 or less, or 4 or more but 6 or less, or 6 or more but 8 or less, or 8 or more but 10 or less. The input regionand the output regioncan each have any planar shape, which is thus not limited to any specific shape. Needless to say, the ratio SOUT/SIN can be more than 0 but less than 1.

The output regionincludes a power MISFET (metal-insulator-semiconductor field-effect transistor)as an example of an insulated-gate power transistor. The power MISFEThas a gate, a drain, and a source. The power MISFETfunctions as a high-side switch that switches between a conducting state and a cut-off state a path between a power terminal and a load.

The input regionincludes a control IC (integrated circuit)as an example of a control circuit. The control ICincludes a plurality of kinds of functional circuits that carry out various functions. The plurality of kinds of functional circuits include one that generates a gate control signal for driving and controlling the power MISFETbased on an external electrical signal. The control ICalong with the power MISFETconstitutes what is called an IPD (intelligent power device). An IPD is also called an IPM (intelligent power module).

The input regionis electrically insulated from the output regionby a region separation structure. In, the region separation structureis indicated by hatching. While no specific description will be given, the region separation structurecan have a trench insulation structure that has an insulator embedded in a trench.

On the semiconductor layer, a plurality of (in this embodiment, six) electrodes,,,,, andare formed. In, the plurality of electrodestoare indicated by hatching. The plurality of electrodestoare each formed as a terminal electrode to be connected to the outside via a lead wire (for example, bonding wire) or the like. There is no restriction on the number, arrangement, and planar shapes of the plurality of electrodesto, which are thus not limited to those shown in.

The number, arrangement, and planar shapes of the plurality of electrodestoare adjusted according to the specifications of the power MISFETor the specifications of the control IC. In this embodiment, the plurality of electrodestoinclude a drain electrode(power electrode), a source electrode(output electrode), an input electrode, a reference voltage electrode, an ENABLE electrode, and a SENSE electrode.

The drain electrodeis formed on the second main surfaceof the semiconductor layer. The drain electrodeis electrically connected to the second main surfaceof the semiconductor layer. The drain electrodetransmits a supply voltage VB to the drain of the power MISFETand to various circuits in the control IC.

The drain electrodecan include at least one of a Ti layer, a Ni layer, a Au layer, a Ag layer, and an Al layer. The drain electrodecan have a single layer structure that includes a Ti layer, a Ni layer, a Au layer, a Ag layer, or an Al layer. The drain electrodecan have a stacked structure in which at least two of a Ti layer, a Ni layer, a Au layer, a Ag layer, and an Al layer are stacked together in any manner.

The source electrodeis formed on the first main surface, over the output region. The source electrodeis electrically connected to the source of the power MISFET. The source electrodetransmits an electrical signal generated by the power MISFETto the outside.

The input electrode, the reference voltage electrode, the ENABLE electrode, and the SENSE electrodeare formed separately on the first main surface, over the input region. The input electrodetransmits an input voltage for driving the control IC.

The reference voltage electrodetransmits a reference voltage (e.g., ground voltage) to the control IC. The ENABLE electrodetransmits an electrical signal for enabling or disabling some or all of the functions of the control IC. The SENSE electrodetransmits an electrical signal for detecting a fault in the control IC.

On the semiconductor layerare further formed a gate control wiringas one example of a control wiring. The gate control wiringis laid selectively in the output regionand the input region. The gate control wiringis, in the output region, electrically connected to the gate of the power MISFETand is, in the input region, electrically connected to the control IC.

The gate control wiringtransmits the gate control signal generated by the control ICto the gate of the power MISFET. The gate control signal includes an on signal Von and an off signal Voff, and controls the on/off state of the power MISFET.

The ON signal Von is higher than the gate threshold voltage Vth of the power MISFET(Vth≤Von). The OFF signal Voff is lower than the gate threshold voltage Vth of the power MISFET(Voff<Vth). The OFF signal Voff can be the reference voltage (e.g., ground voltage).

In this embodiment, the gate control wiringincludes a first gate control wiringA, a second gate control wiringB, and a third gate control wiringC. The first, second, and third gate control wiringsA,B, andC are electrically insulated from each other.

In this embodiment, two first gate control wiringsA are laid in different regions, two second gate control wiringsB are laid in different regions, and two third gate control wiringsC are laid in different regions.

The first, second, and third gate control wiringsA,B, andC transmit the same gate control signal or different gate control signals to the gate of the power MISFET. There is no restriction on the number, arrangement, shapes, etc., of the gate control wirings, which are adjusted according to the transmission distance of the gate control signals and/or the number of the gate control signals to be transmitted.

The source electrode, the input electrode, the reference voltage electrode, the ENABLE electrode, the SENSE electrode, and the gate control wiringcan each contain at least one of nickel, palladium, aluminum, copper, an aluminum alloy, and a copper alloy.

The source electrode, the input electrode, the reference voltage electrode, the ENABLE electrode, the SENSE electrode, and the gate control wiringcan each include at least one of an Al—Si—Cu (aluminum-silicon-copper) alloy, an Al—Si (aluminum-silicon) alloy, and an Al—Cu (aluminum-copper) alloy.

The source electrode, the input electrode, the reference voltage electrode, the ENABLE electrode, the SENSE electrode, and the gate control wiringcan include the same type of electrode material or can include mutually different electrode materials.

is a block circuit diagram showing an electrical configuration of the semiconductor deviceshown in. The following description deals with an example where the semiconductor deviceis incorporated in a vehicle.

The semiconductor deviceincludes a drain electrode, a source electrode, an input electrode, a reference voltage electrode, an ENABLE electrode, a SENSE electrode, a gate control wiring, a power MISFET, and a control IC.

The drain electrode(i.e., a power electrode VBB) is connected to a power source. The drain electrodefeeds the power MISFETand the control ICwith a supply voltage VB. The supply voltage VB can be 10 V or more but 20 V or less. On the other hand, the source electrode(i.e., an output electrode OUT) is connected to a load.

The input electrode(i.e., an input electrode IN) can be connected to an MCU (microcontroller unit), a DC/DC converter, a LDO (low dropout), or the like. The input electrodesupplies the control ICwith an input voltage. The input voltage can be 1 V or more but 10 V or less. The reference voltage electrodeis connected to a reference voltage wiring. The reference voltage electrodefeeds the power MISFETand the control ICwith a reference voltage.

The ENABLE electrodecan be connected to the MCU. The ENABLE electrodeis fed with an electrical signal for enabling or disabling some or all of the functions of the control IC. The SENSE electrodecan be connected to a resistor.

The gate of the power MISFETis connected via the gate control wiringto the control IC(a gate control circuit, which will be described later). The drain of the power MISFETis connected to the drain electrode. The source of the power MISFETis connected to the control IC(a current sense circuit, which will be described later), and to the source electrode.

The control ICincludes a sensor MISFET, an input circuit, a current/voltage control circuit, a protection circuit, a gate control circuit, an active clamp circuit, a current sense circuit, a reversed power connection protection circuit, and a fault detection circuit.

The gate of the sensor MISFETis connected to the gate control circuit. The drain of the sensor MISFETis connected to the drain electrode. The source of the sensor MISFETis connected to the current sense circuit.

The input circuitis connected to the input electrodeand to the current/voltage control circuit. The input circuitcan include a Schmitt trigger circuit. The input circuitshapes the waveform of the electrical signal fed to the input electrode. The signal generated by the input circuitis fed to the current/voltage control circuit.

The current/voltage control circuitis connected to the protection circuit, to the gate control circuit, to the reversed power connection protection circuit, and to the fault detection circuit. The current/voltage control circuitcan include a logic circuit.

The current/voltage control circuitgenerates various voltages according to an electrical signal from the input circuitand an electrical signal from the protection circuit. In this embodiment, the current/voltage control circuitincludes a driving voltage generation circuit, a first constant voltage generation circuit, a second constant voltage generation circuit, and a reference voltage/reference current generation circuit.

The driving voltage generation circuitgenerates a driving voltage for driving the gate control circuit. The driving voltage can be set to a value determined by subtracting a predetermined value from the supply voltage VB. The driving voltage generation circuitcan generate a driving voltage of 5 V or more but 15 V or less as a voltage determined by subtracting 5 V from the supply voltage VB. The driving voltage is fed to the gate control circuit.

The first constant voltage generation circuitgenerates a first constant voltage for driving the protection circuit. The first constant voltage generation circuitcan include a Zener diode or a regulator circuit (here, a Zener diode). The first constant voltage can be 1 V or more but 5 V or less. The first constant voltage is fed to the protection circuit(more specifically, a load open detection circuit, which will be described later, or the like).

The second constant voltage generation circuitgenerates a second constant voltage for driving the protection circuit. The second constant voltage generation circuitcan include a Zener diode or a regulator circuit (here, a regulator circuit). The second constant voltage can be 1 V or more but 5 V or less. The second constant voltage is fed to the protection circuit(more specifically, an overheating protection circuitand an undervoltage malfunctioning prevention circuit, which will be described later).

The reference voltage/reference current generation circuitgenerates a reference voltage and a reference current for various circuits. The reference voltage can be 1 V or more but 5 V or less. The reference current can be 1 mA or more but 1 A or less. The reference voltage and the reference current are fed to various circuits. If any of the various circuits includes a comparator, the reference voltage and the reference current can be fed to the comparator.

The protection circuitis connected to the current/voltage control circuit, to the gate control circuit, to the fault detection circuit, to the source of the power MISFET, and to the source of the sensor MISFET. The protection circuitincludes an overcurrent protection circuit, a load open detection circuit, an overheating protection circuit, and an undervoltage malfunctioning prevention circuit.

The overcurrent protection circuitprotects the power MISFETfrom an overcurrent. The overcurrent protection circuitis connected to the gate control circuitand to the source of the sensor MISFET. The overcurrent protection circuitcan include a current monitor circuit. A signal generated by the overcurrent protection circuitis fed to the gate control circuit(more specifically, to a driving signal output circuit, which will be described later).

The load open detection circuitdetects a shorted state and an open state in the power MISFET. The load open detection circuitis connected to the overcurrent protection circuitand to the source of the power MISFET. A signal generated by the load open detection circuitis fed to the current/voltage control circuit.

The overheating protection circuitmonitors the temperature of the power MISFETand protects the power MISFETfrom an excessive rise in temperature. The overheating protection circuitis connected to the current/voltage control circuit. The overheating protection circuitcan include a temperature-sensing device such as a temperature-sensing diode or thermistor. A signal generated by the overheating protection circuitis fed to the current/voltage control circuit.

The undervoltage malfunctioning prevention circuitprevents the power MISFETfrom malfunctioning when the supply voltage VB is less than a predetermined value. The undervoltage malfunctioning prevention circuitis connected to the current/voltage control circuit. A signal generated by the undervoltage malfunctioning prevention circuitis fed to the current/voltage control circuit.