Sigma delta modulation device capable of switching order of loop filter, and loop filter for sigma delta modulation device

This application is based on and claims priority from Korean Patent Application No. 10-2023-0158614, filed on Nov. 15, 2023, the disclosure of which is incorporated herein in its entirety by reference for all purposes.

The present disclosure relates to a sigma delta modulator and a loop filter therefor.

This work was supported in part by National Research Foundation of Korea (NRF) grant funded by Korea government (MSIT) (Project No.: 2021R1F1A1056073, and Research Project Title: Development of Integrated Low-Noise Power Converter for Next-Generation Semiconductor Beamforming Antennas) and in part by Regional Innovation Strategy (RIS) through the NRF of Korea government (MOE) (Project No.: 2021RIS-004).

A sigma delta modulation method is an analog to digital conversion (ADC) or digital to analog conversion (DAC) method derived from the delta modulation method, and has anti-aliasing characteristics and high signal to noise ratio (SNR) characteristics.

The principle of delta sigma modulation is to predict the value of a signal, obtain an error, and then correct the error using the cumulated error. In this regard, when a cumulative error value is finite, the average of an input signal may be the same as the average of an output signal.

Meanwhile, a sigma delta modulator used at a receiving end of a transceiver system is used in various standards due to its noise shaping characteristics. However, due to the complexity of design and the difficulty of maintaining stability, the modulator is typically limited to operating only in a single signal bandwidth and clock frequency. For example, a communication method requiring a high SNR in a narrow bandwidth and a communication method requiring a medium SNR in a wide signal bandwidth use delta sigma modulators having different structures and orders. Therefore, since a different modulator should be implemented depending on the system, there is a problem that the size and power consumption of the system increases.

In order to solve the problem, a technology that can support multiple modes by switching the order of a loop filter of a sigma delta modulator has been proposed. However, this technology does not consider a notch frequency of a noise transfer function when switching the order.

The description provided above as a related art of the present disclosure is technical information that the inventor(s) possessed for deriving the present invention or acquired in the process of deriving the present invention, and may not necessarily said to be technology known to those of ordinary skill in the art before the present invention is filed.

In view of the above, the present disclosure provides a sigma delta modulation device that can support multiple modes by switching an order of a loop filter and can compensate for a notch frequency of a noise transfer function when switching the order.

An embodiment of the present disclosure provides a loop filter for a sigma delta modulation device that can support multiple modes and can compensate for a notch frequency of a noise transfer function when switching an order.

In accordance with an aspect of the present disclosure, there is provided a loop filter for a sigma delta modulation device, the loop filter comprises: an operational amplifier; a circuit including a plurality of capacitors, a plurality of resistors, and a plurality of switches, which are connected to the operational amplifier; a memory configured to store one or more instructions; and a processor configured to execute the one or more instructions stored in the memory, wherein the instructions, when executed by the processor, cause the processor to control turn on or off of the plurality of switches so as to represent signal transfer characteristics of the loop filter for satisfying a third-order transfer function or a second-order transfer, and to adjust resistor values in an equivalent circuit of the loop filter in order to compensate a notch frequency reduced in the loop filter for satisfying the second-order transfer function.

The processor may be configured to control turn on or off of the plurality of switches so as to adjust resistor values to be reduced in the equivalent circuit of the loop filter for satisfying the second-order transfer function in order to increase the notch frequency of the loop filter, and to adjust resistance values of at least two resistors among the plurality of resistors in order to increase a signal to noise ratio (SNR) of the sigma delta modulation device.

The circuit may include a first resistor to which an input signal of the loop filter is applied at a first end thereof and which is connected at a second end thereof to an input terminal of the operational amplifier; a first capacitor connecting the first resistor and an input terminal of the operational amplifier; a second capacitor connected in series to the first capacitor; a third capacitor connected in series to the second capacitor; a second resistor, a fourth resistor, and a sixth resistor connected at first ends thereof to a first node that is a node between the first capacitor and the second capacitor; and a third resistor, a fifth resistor, and a seventh resistor connected at first ends thereof to a second node that is a node between the second capacitor and the third capacitor.

The circuit may comprise a first switch connected between the first node and the sixth resistor; a second switch connected between the second node and the seventh resistor; a third switch connected to the first node and the input terminal of the operational amplifier and configured in parallel with the first capacitor; and a fourth switch connected between the first node and the second resistor.

The at least one resistor may include the third resistor and a first additional resistor connected to the third resistor in parallel, wherein the circuit includes a fifth switch connected to a first end of the first additional resistor, and wherein the processor may be configured to control turn on the fifth switch when the loop filter is set to satisfy the second-order transfer function.

The at least two resistors may include the fourth resistor, the fifth resistor, a second additional resistor having a resistance value of the same ratio connected to the fourth resistor in series, and a third additional resistor having a resistance value of the same ratio to the fifth resistor connected to the fourth resistor in series. Wherein the circuit may include a sixth switch connected to both ends of the second additional resistor, and a seventh switch connected to both ends of the third additional resistor. Wherein the processor may be configured to control turn off the sixth switch and the seventh switch when the loop filter is set to satisfy the second-order transfer function.

The processor may be configured to control turn on the first switch, the second switch, and the fourth switch and turn off the third switch so as to be represented the signal transfer characteristics of the loop filter for satisfying the third-order transfer function.

The processor may be configured to control turn off the first switch, the second switch, and the fourth switch and turn on the third switch so as to be represented signal characteristics of the loop filter for satisfying the second-order transfer function.

The circuit may comprise a first inverting circuit and a second inverting circuit for expressing differential signals as a single end. Wherein second ends of the second resistor and the third resistor may be connected to a ground, a second end of the fourth resistor may be connected to an output terminal of the operational amplifier, a second end of the fifth resistor may be connected to an output terminal of the second inverting circuit, a second end of the sixth resistor may be connected to an output terminal of the first inverting circuit, and a second end of the seventh resistor may be connected to the third node.

The seventh resistor may be a variable resistor, and the processor may be configured to control a resistance value of the seventh resistor in order to adjust a change in bandwidth according to turning on or off of the plurality of switches.

In accordance with another aspect of the present disclosure, there is provided a sigma delta modulation device capable of switching an order of a loop filter, the device comprises: a loop filter including an operational amplifier, and a circuit including a plurality of capacitors, a plurality of resistors, and a plurality of switches, which are connected to the operational amplifier; a quantization part quantizing and outputting a signal that is output from the loop filter; a feed-back converter converting a digital signal output from the quantization part into an analog signal; a memory configured to store one or more instructions; and a processor configured to execute the one or more instructions stored in the memory, wherein the instructions, when executed by the processor, cause the processor to control turn on or off of the plurality of switches so as to represent signal transfer characteristics of the loop filter for satisfying a third-order transfer function or a second-order transfer, and to adjust resistor values in an equivalent circuit of the loop filter in order to compensate a notch frequency reduced in the loop filter for satisfying the second-order transfer function.

The processor may be configured to control turn on or off of the plurality of switches so as to adjust resistor values to be reduced in the equivalent circuit of the loop filter for satisfying the second-order transfer function in order to increase the notch frequency of the loop filter, and to adjust resistance values of at least two resistors among the plurality of resistors in order to increase an SNR (signal to noise ratio) of the sigma delta modulation device.

The circuit may includes: a first resistor to which an input signal of the loop filter is applied at a first end thereof and which is connected at a second end thereof to an input terminal of the operational amplifier; a first capacitor connecting the first resistor and an input terminal of the operational amplifier; a second capacitor connected in series to the first capacitor; a third capacitor connected in series to the second capacitor; a second resistor, a fourth resistor, and a sixth resistor connected at first ends thereof to a first node that is a node between the first capacitor and the second capacitor; and a third resistor, a fifth resistor, and a seventh resistor connected at first ends thereof to a second node that is a node between the second capacitor and the third capacitor.

The circuit may comprise a first switch connected between the first node and the sixth resistor; a second switch connected between the second node and the seventh resistor; a third switch connected to the first node and the input terminal of the operational amplifier and configured in parallel with the first capacitor; and a fourth switch connected between the first node and the second resistor.

The at least one resistor may include the third resistor and a first additional resistor connected to the third resistor in parallel. Wherein the circuit may include a fifth switch connected to a first end of the first additional resistor, and the processor may be configured to control turn on the fifth switch when the loop filter is set to satisfy the second-order transfer function.

The at least two resistors may include the fourth resistor, the fifth resistor a second additional resistor having a resistance value of the same ratio connected to the fourth resistor in series, and a third additional resistor having a resistance value of the same ratio to the fifth resistor connected to the fourth resistor in series. Wherein the circuit may include a sixth switch connected to both ends of the second additional resistor, and a seventh switch connected to both ends of the third additional resistor, and the processor may be configured to control turn off the sixth switch and the seventh switch when the loop filter is set to satisfy the second-order transfer function.

The processor may be configured to control turn on the first switch, the second switch, and the fourth switch and turn off the third switch so as to be represented the signal transfer characteristics of the loop filter for satisfying the third-order transfer function.

The processor may be configured to control turn off the first switch, the second switch, and the fourth switch and turn on the third switch so as to be represented signal characteristics of the loop filter for satisfying the second-order transfer function.

The circuit may comprise a first inverting circuit and a second inverting circuit for expressing differential circuits as a single end. Wherein second ends of the second resistor and the third resistor may be connected to a ground, a second end of the fourth resistor may be connected to an output terminal of the operational amplifier, a second end of the fifth resistor may be connected to an output terminal of the second inverting circuit, a second end of the sixth resistor may be connected to an output terminal of the first inverting circuit, and a second end of the seventh resistor may be connected to the third node.

The seventh resistor may be a variable resistor, and the processor may be configured to control a resistance value of the seventh resistor in order to adjust a change in bandwidth according to turning on or off of the plurality of switches.

According to an embodiment of the present disclosure, in the case of switching an order of a loop filter from high to low dimensions, a notch frequency of a noise transfer function shifts to a low frequency, overcoming the limitation of not being able to achieve wide bandwidth characteristics despite having a high oversampling ratio (OSR). According to an embodiment of the present disclosure, by implementing a continuous-time sigma delta modulation device that may operate in dual or multiple modes, it is possible to achieve a multi-mode operation by reconfiguring the structure of the loop filter according to a frequency instead of using an existing method of adjusting a time constant by changing a resistor and a capacitor. Thereby, the present disclosure can maximize power efficiency in the sigma delta modulation device.

The advantages and features of the embodiments and the methods of accomplishing the embodiments will be clearly understood from the following description taken in conjunction with the accompanying drawings. However, embodiments are not limited to those embodiments described, as embodiments may be implemented in various forms. It should be noted that the present embodiments are provided to make a full disclosure and also to allow those skilled in the art to know the full range of the embodiments. Therefore, the embodiments are to be defined only by the scope of the appended claims.

Terms used in the present specification will be briefly described, and the present disclosure will be described in detail.

In terms used in the present disclosure, general terms currently as widely used as possible while considering functions in the present disclosure are used. However, the terms may vary according to the intention or precedent of a technician working in the field, the emergence of new technologies, and the like. In addition, in certain cases, there are terms arbitrarily selected by the applicant, and in this case, the meaning of the terms will be described in detail in the description of the corresponding invention. Therefore, the terms used in the present disclosure should be defined based on the meaning of the terms and the overall contents of the present disclosure, not just the name of the terms.

When it is described that a part in the overall specification “includes” a certain component, this means that other components may be further included instead of excluding other components unless specifically stated to the contrary.

In addition, a term such as a “unit” or a “portion” used in the specification means a software component or a hardware component such as FPGA or ASIC, and the “unit” or the “portion” performs a certain role. However, the “unit” or the “portion” is not limited to software or hardware. The “portion” or the “unit” may be configured to be in an addressable storage medium, or may be configured to reproduce one or more processors. Thus, as an example, the “unit” or the “portion” includes components (such as software components, object-oriented software components, class components, and task components), processes, functions, properties, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, database, data structures, tables, arrays, and variables. The functions provided in the components and “unit” may be combined into a smaller number of components and “units” or may be further divided into additional components and “units”.

Hereinafter, the embodiment of the present disclosure will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the present disclosure. In the drawings, portions not related to the description are omitted in order to clearly describe the present disclosure.

A sigma delta modulation device operated in multiple modes is widely used in a wireless communication, a sensor network, and a power conversion system due to its excellent performance. The multi-mode sigma delta modulation device has high-resolution conversion, flexible bandwidth scalability, and improved power efficiency. In order to implement these multiple modes, discrete-time and continuous-time types are being implemented.

The multi-mode operation of the sigma delta modulation device in terms of bandwidth and resolution may generally be implemented by adjusting a sampling frequency. In the discrete-time sigma delta modulation device, the coefficient of a loop filter is scaled according to a change in clock frequency, and the coefficient is set by a capacitor ratio, so it is suitable for the multiple modes. However, the discrete-time sigma delta modulation device has a drawback that much power is consumed in an operational amplifier, so efficiency is low.

Further, the continuous-time sigma delta modulation device exhibits high efficiency due to the low power consumption requirements of the operational amplifier, but has a drawback that resistance and capacitor values should be reset when the clock frequency changes.

Thus, an embodiment of the present disclosure provides a sigma delta modulation device that can support multiple modes by switching an order of a loop filter and can compensate for a notch frequency of a noise transfer function when switching the order.

Further, an embodiment of the present disclosure provides a sigma delta modulation device that can support multiple modes by switching an order of a loop filter and can optimize an SNR.

Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

is a configuration diagram showing a sigma delta modulation device capable of switching the order of a loop filter according to an embodiment of the present disclosure.

As shown in, the sigma delta modulation devicecapable of switching the order of the loop filter according to an embodiment of the present disclosure may include loop filtersand, a summing part, a quantization part, a switching unit, a feed-back converter RZ (or feedback part), and a control unit.

First, the summing partmay transmit a signal u′ obtained by subtracting an output signal of the feed-back converter RZ from an input signal u input from the outside to the first loop filteror the second loop filter.

That is, by transmitting an error between the input signal u and a signal converting the output signal v back to analog to the first loop filteror the second loop filter, the error may be accumulated in the first loop filteror the second loop filterand thereby the error may be corrected.

Here, the loop filtermay integrate and output a difference u′ between the input signal u and the analog signal. For example, the difference u′ between the input signal u and the analog signal may be expressed as the error, and the error may be accumulated through one or more integrators. At this time, the loop filtersandmay include integrators corresponding to a desired order. For example, if the loop filter is implemented as a second-order loop filter, two integrators may be included. If the loop filter is implemented as a third-order loop filter, three integrators may be included. Here, the loop filtersandmay be implemented in a feed-back form but may also be implemented in a feed-forward form.

The loop filtersandmay have conditionally stable characteristics because state stability decreases as the order increases. Thus, as the order increases, stable operation may be made only through a combination of specific sampling frequency (Fs) and specific loop gain coefficients. Therefore, a fixed signal bandwidth may be generally used to maintain state stability.

The quantization partmay quantize and output a signal that is output from each of the loop filtersand, and may quantize the signal according to the sampling frequency Fs. At this time, the quantization partmay compare the output signal of each of the loop filtersandwith a reference value and then output the output signal v.