Memory device and manufacturing method thereof

This application is a continuation of U.S. patent application Ser. No. 17/518,789 filed on Nov. 4, 2021, which claims the benefit of U.S. Provisional Application No. 63/137,383 filed on Jan. 14, 2021 and U.S. Provisional Application No. 63/133,464, filed on Jan. 4, 2021, each application is hereby incorporated by reference.

Magnetic random access memory (MRAM) is one of the leading candidates for next-generation memory technologies that aim to surpass the performance of various existing memories. MRAM offers comparable performance to volatile static random access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random access memory (DRAM). As compared to non-volatile flash memory, MRAM offers much faster access speed and suffers minimal degradation over time. Spin orbit torque MRAM (SOT-MRAM) is a type of MRAM. As compared to spin transfer torque MRAM (STT-MRAM), which is another type of MRAM, SOT-MRAM offers better performance in terms of speed and endurance. Nevertheless, further reducing switching energy of SOT-MRAM is limited.

The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

is a circuit diagram schematically illustrating a memory arrayaccording to some embodiments of the present disclosure.illustrates a write path in a selected unit cellin the memory arrayas shown in.illustrates a read path in a selected unit cellin the memory arrayas shown in.

Referring to, the memory arrayis a magnetic random access memory (MRAM) array. The memory arrayincludes a plurality of the unit cellsarranged along rows and columns. The unit cellsin each row may be arranged along a direction X, while the unit cellsin each column may be arranged along a direction Y. In some embodiments, each column of the unit cellsare coupled to a pair of a write word line WWL and a read word line RWL, and each row of the unit cellsis coupled to a bit line BL as well as a pair of source lines SL. In these embodiments, each unit cellmay be defined between one of the write word lines WWL and one of the read word lines RWL, and between one of the bit lines BL and two of the source lines SL. In addition, the write word lines WWL and the read word lines RWL may extend along the direction Y, and the bit lines BL as well as the source lines SL may extend along the direction X.

Each unit cellincludes a magnetic tunneling junction (MTJ)as a storage element. Magnetization orientations of ferromagnetic layers in the MTJmay determine an electrical resistance of the MTJ. The MTJmay have a low electrical resistance state when the magnetization orientations are at a parallel state, and have a high electrical resistance state when the magnetization orientations are at an anti-parallel state. By altering the magnetization orientations in the MTJ, the MTJcan be programmed to store complementary logic sates (e.g., a logic high state indicating the high electrical resistance state and a logic low state indicating the low electrical resistance state). Further, according to embodiments of the present disclosure, the MTJis configured to be programmed by utilizing a spin Hall effect, and the memory arraymay be referred as a spin orbit torque MRAM (SOT-MRAM) array. A spin hall electrode (SHE), or referred as a spin orbit torque (SOT) layer, lies below each of the MTJs. During a programming operation, an in-plane charge current passing through the SHEmay be converted to a perpendicular spin current via a spin Hall effect. The perpendicular spin current then flows into a ferromagnetic layer in the MTJand switch its magnetization via a spin orbit torque (SOT). In this way, the magnetization orientations of the MTJ(i.e., the electrical resistance of the MTJ) can be altered, and bit data can be programmed into the MTJ. During a read operation, the resistance state of the MTJcan be sensed, and the bit data stored in the MTJcan be read out.

An energy efficiency of the programming operation is highly dependent on a spin Hall conductivity of the SHE. The higher the spin Hall conductivity of the SHE, the less power consumption is required for the programming operation. The spin Hall conductivity of the SHEis defined as a ratio of a spin Hall angle of the SHEover an electrical resistivity of the SHE. The spin Hall angle of the SHEindicates an efficiency of the conversion from the in-plane charge current provided across the SHE, to the perpendicular spin current induced due to the spin Hall effect, and is defined as a ratio of the induced perpendicular spin current over the corresponding in-plane charge current. In other words, the higher the spin Hall angle, the more efficient of the conversion from the in-plane charge current to the perpendicular spin current, and the higher of the spin Hall conductivity. On the other hand, a shunting ratio of the in-plane charge current is affected by the electrical resistivity of the SHE. The shunting ratio is defined as a ratio of a sheet resistance of the SHEover a sheet resistance of a free layer in the MTJ. When the electrical resistivity of the SHEis relatively high, a larger portion of the in-plane charge current may take a low resistance path through the MTJstanding on the SHE, and such portion of the in-plane charge current may not contribute to the generation of the perpendicular spin current. As a result, the conversion from the in-plane charge current to the perpendicular spin current is less efficient. On the other hand, when the electrical resistivity of the SHEis relatively low, a shunting ratio of the in-plane charge current becomes lower, and the conversion from the in-plane charge current to the perpendicular spin current is more efficient. Therefore, in order to improve the spin Hall conductivity of the SHE, the spin Hall angle of the SHEhas to be high, and/or the electrical resistivity of the SHEhas to be low.

According to embodiments of the present disclosure, the SHEis formed of a metal alloy including at least one heavy metal element and at least one light transition metal element, and exhibits superior spin Hall conductivity over other materials for forming a SHE. The heavy metal element may be a metal element with valence electron(s) filling in 5d orbitals, or referred as a 5d metal element. For instance, the at least one heavy metal element may include platinum (Pt), palladium (Pd) or a combination thereof. On the other hand, the light transition metal element may be a transition metal element with valence electron(s) partially filling in 3d orbitals. For instance, the at least one light transition metal element may include scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu) or combinations thereof. Such superior spin Hall conductivity of the SHEmay result from, e.g., the heavy metal element possessing 5d electron bands, which contribute to a strong spin-orbit coupling and result in an effective magnetic field to separate spin-up and down current. In addition, the 3d electrons of the light transition metal element might contribute to the electron scattering center, which results in higher spin Hall angle. There may be other explanations for the superior spin Hall conductivity of the SHE, the present disclosure is not limited to the explanations discussed above. For instance, as another possible explanation, such metal alloy has superior spin Hall conductivity because a 3d-5d hybridization can reduce spin memory loss (or referred as diminish of spin polarization) and spin current back flow.

As an example, the SHEmay be formed of a platinum-chromium alloy, which can be presented as PtCr. A spin Hall angle of the platinum-chromium alloy appears to be raised by increasing chromium content in the platinum-chromium alloy (i.e., reducing platinum content in the platinum-chromium alloy). In addition, an electrical resistivity of the platinum-chromium alloy appears to be reduced by increasing platinum content in the platinum-chromium alloy (i.e., reducing chromium content in the platinum-chromium alloy). An optimum range of the “x” in the PtCrmay be from about 0.5 to about 0.8. If the “x” is less than about 0.5, the electrical resistivity of the platinum-chromium alloy may be significantly compromised. On the other hand, if the “x” is greater than about 0.8, the spin Hall angle of the platinum-chromium alloy may be limited. The spin Hall angle of the platinum-chromium alloy with the optimum x range may be equal to or greater than 0.1, such as ranging from 0.1 to 1.1. The electrical resistivity of the platinum-chromium alloy with the optimum x range may be equal to or lower than 600 μΩ·cm, such as ranging from 30 μΩ·cm to 600 μΩ·cm. Accordingly, the spin Hall conductivity of the platinum-chromium alloy with the optimum x range may be equal to or greater than

such as ranging from

As a result of the superior spin Hall conductivity, requirement of the in-plane charge current for switching the magnetization orientations in the MTJcan be significantly lowered. For instance, the in-plane charge current requirement of the unit cellincluding the SHEformed of the platinum-chromium alloy with the optimum x range may be between 1×10A·cmand 30×10A·cm. As a result of such low requirement of the in-plane charge current, the unit cellincluding the SHEformed of the platinum-chromium alloy with the optimum x range requires much less energy for switching the magnetization orientations in the MTJ(or referred as a switching energy). For instance, switching energy requirement of the unit cellincluding the SHEformed of the platinum-chromium alloy with the optimum×range may be between about 0.1 fJ and 1 fJ. Furthermore, as a result of low electrical resistivity of the platinum-chromium alloy with the optimum x range, the shunting ratio of the unit cellincluding the SHEformed of the platinum-chromium alloy with the optimum x range may be effectively lowered. For instance, the shunting ratio of the unit cellincluding the SHEformed of the platinum-chromium alloy with the optimum x range may be between 0.1 and 0.9.

As another example, the SHEmay be formed of a platinum-vanadium alloy, which can be presented as PtV. Similarly, a spin Hall angle of the platinum-vanadium alloy appears to be raised by increasing vanadium content in the platinum-vanadium alloy (i.e., reducing platinum content in the platinum-vanadium alloy), and an electrical resistivity of the platinum-vanadium alloy appears to be reduced by increasing platinum content in the platinum-vanadium alloy (i.e., reducing vanadium content in the platinum-vanadium alloy). An optimum range of the “y” in the PtVmay be from about 0.7 to about 0.9. If the “y” is less than about 0.7, the electrical resistivity of the platinum-vanadium alloy may be significantly compromised. On the other hand, if the “y” is greater than about 0.9, the spin Hall angle of the platinum-vanadium alloy may be limited. The spin Hall angle of the platinum-vanadium alloy with the optimum y range may be equal to or greater than 0.1, such as ranging from 0.1 to 0.8. The electrical resistivity of the platinum-vanadium alloy with the optimum y range may be equal to or lower than 135 μΩ·cm, such as ranging from 30 μΩ·cm to 135 μΩ·cm. Accordingly, the spin Hall conductivity of the platinum-vanadium alloy with the optimum y range may be equal to or greater than

such as ranging from

As a result of the superior spin Hall conductivity, the in-plane charge current requirement of the unit cellincluding the SHEformed of the platinum-vanadium alloy with the optimum y range may be between 1×10A·cmand×A·cm. As a result of such low requirement of the in-plane charge current, the switching energy requirement of the unit cellincluding the SHEformed of the platinum-vanadium alloy with the optimum y range may be between 0.1 fJ and 1 fJ. Furthermore, as a result of low electrical resistivity of the platinum-vanadium alloy with the optimum y range, the shunting ratio of the unit cellincluding the SHEformed of the platinum-vanadium alloy with the optimum y range may be between 0.04 and 0.18.

Furthermore, more combinations of the heavy metal element and the light transition metal element (e.g., Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Co, Zn) may fall within the scope of the present disclosure. The present disclosure is not limited to the above-described two examples. In addition, in some embodiments, a thickness of the SHEranges from about 0.5 nm to about 10 nm. The spin Hall angle of the SHEmay increase as the thickness of the SHE, and may not saturate until the thickness of the SHEis equal to or greater than about 0.5 nm. Therefore, if the thickness of the SHEis below about 0.5 nm, the spin Hall angle of the SHEmay be limited. On the other hand, if the thickness of the SHEis greater than about 10 nm, requirement of the charge current for a programming operation is significantly increased, thus energy efficiency of the programming operation is compromised.

As shown in, in some embodiments, each unit cellfurther includes a write transistor WT and a read transistor RT. The write transistor WT and the read transistor RT in each unit cellare coupled to the SHE. Particularly, the write transistor WT and the read transistor RT may be coupled to portions of the SHEat opposite sides of the MTJ, such that the MTJcan stand on a write current path (i.e., the in-plane charge current described above) between the write transistor WT and the read transistor RT. Accordingly, the MTJcan be programmed by the write current. The write transistors WT and the read transistors RT may respectively be a three-terminal device. A gate terminal of each write transistor WT may be coupled to one of the write word lines WWL, and a gate terminal of each read transistor RT may be coupled to one of the read word lines RWL. In addition, the write transistor WT and the read transistor RT in each unit cellare respectively coupled to the SHEthrough a source/drain terminal, and respectively coupled to one of the source lines SL through the other source/drain terminal. In some embodiments, the write transistor WT and the read transistor RT in each unit cellare coupled to two of the source lines SL. Further, a terminal of each MTJis coupled to the underlying SHE, and the other terminal of each MTJis coupled to one of the bit lines BL.

A word line driver circuit WD may be coupled to the write word lines WWL and the read word lines RWL, and configured to control switching of the write transistors WT and the read transistors RT through the write word lines WWL and the read word lines RWL. In addition, a current source circuit CS may be coupled to the source lines SL. The current source circuit CS is configured to provide the write current (i.e., the in-plane charge current described above) for programming the MTJsas well as a read current for sensing the resistance states of the MTJs, and may be in conjunction with the word line driver circuit WD. Further, a bit line driver circuit BD may be coupled to the bit lines BL, and configured to sense the read current passing through the MTJs, so as to identify the resistance states of the MTJs.

Referring toand, during a programming operation, the write transistor WT and the read transistor RT of a selected unit cellmay be both turned on, and a write current WP (i.e., the in-plane charge current as described above) may flow through the write transistor WT, the read transistor RT and the SHEin between. As a result of spin orbit interaction, the write current WP flowing through the SHEmay induce a SOT on the MTJ, thus the MTJcan be subjected to programming. The write transistor WT and the read transistor RT are turned on by setting the corresponding write word line WWL and read word line RWL, and the write current WP is provided by setting a voltage difference between the corresponding two of the source lines SL. On the other hand, the bit line BL may be floated.

Referring toand, during a read operation, the read transistor RT of a selected unit cellis turned on while the write transistor WT in the same unit cellmay be kept off. A voltage difference may be set between the bit line BL and the source line SL coupled to the read transistor RT, thus a read current RP can flow through the MTJconnected between the read transistor RT and the bit line BL. Due to a spin orbit coupling effect, different magnetization orientations of the MTJ(i.e., the parallel state and the anti-parallel state) may result a change in an amount of scattering of conduction electrons traveling across the MTJ. Such change leads to difference electrical resistances of the MTJ, and may affect a value of the read current RP or a value of a voltage drop across the MTJ. Therefore, the bit data (i.e., the resistance state) stored in the MTJcan be read out. On the other hand, the source line SL coupled to the write transistor WT may be floated.

is a schematic three-dimensional view illustrating one of the unit cellsshown in.

Referring to, the write transistor WT and the read transistor RT in a unit cellare formed in a front-end-of-line (FEOL) structure FE of a device wafer. A gate terminal of the write transistor WT may be provided by a write word line WWL lying on a semiconductor substrate. Similarly, a gate terminal of the read transistor RT may be provided by a read word line RWL lying on the semiconductor substrate. The write word line WWL and the read word line RWL may be laterally spaced apart from each other, and may both extend along the direction Y. Source and drain terminals (not shown) of the write transistor WT are located at opposite sides of the write word line WWL, and source and drain terminals (not shown) of the read transistor RT are located at opposite sides of the read word line RWL. In those embodiments where the write transistor WT and the read transistor RT are planar-type transistors, the write word line WWL as well as the read word line RWL respectively lie on a planar surface of the substrate, and the source and drain terminals of the write transistor WT and the read transistor RT may be doped regions or epitaxial structures (not shown) formed in a shallow region of the semiconductor substrate. In those embodiments where the write transistor WT and the read transistor RT are fin-type transistors, the write word line WWL and the read word line RWL respectively cover and intersect with a fin structure at a top region of the substrate, and the source and drain terminals of the write transistor WT and the read transistor RT may be epitaxial structures (not shown) in contact (e.g., in lateral contact) with the fin structures. In those embodiments where the write transistor WT and the read transistor RT are gate-all-around (GAA) transistors, stacks of semiconductor sheets over the substrateare respectively wrapped by a write word line WWL or a read word line RWL, and the source and drain terminals of the write transistor WT and the read transistor RT may be epitaxial structures (not shown) in contact (e.g., in lateral contact) with the stacks of semiconductor sheets. Furthermore, contact plugsmay stand on the source/drain terminals of the write transistor WT and the read transistor RT. The contact plugsare electrically connected to these source/drain terminals, in order connect these source/drain terminals to overlying conductive components.

In some embodiments, a dummy word line DWL lies between the write word line WWL and the read word line RWL. The dummy word line DWL, the write word line WWL and the read word line RWL may extend along the same direction, such as the direction Y. By disposing the dummy word line DWL, a parasitic transistor may be formed between the write transistor WT and the read transistor RT. The parasitic transistor may be structurally identical with the write transistor WT and the read transistor RT. A gate terminal of the parasitic transistor may be provided by the dummy word line DWL. The write transistor WT and the read transistor RT each share one of its source/drain terminals with the parasitic transistor. In some embodiments, the dummy word line DWL is configured to receive a gate voltage that can ensure an off state of the parasitic transistor, thus the interference between the write transistor WT and the read transistor RT can be effectively avoided. Accordingly, the parasitic transistor including the dummy word line DWL may also be referred as an isolation transistor DT.

The source lines SL, the SHE, the MTJand the bit line BL may be integrated in a back-end-of-line (BEOL) structure BE formed above the FEOL structure FE. In some embodiments, the source lines SL coupled to the write transistor WT and the read transistor RT are portions of a bottom metallization layer in the BEOL structure BE, and may extend along the direction X. The source lines SL are connected to some of the source/drain terminals of the write transistor WT and the read transistors RT through the contact plugsextending in between. In some embodiments, others source/drain terminals of the write transistor WT and the read transistor RT are connected to landing padsalso formed in the bottom metallization layer of the BEOL structure BE, by the contact plugsextending in between. Moreover, the SHEand the MTJmay be formed over the bottom metallization layer. The SHEmay be electrically connected to the landing padsin the bottom metallization layer by bottom viasextending in between. In other words, the SHEmay be coupled to source or drain terminals of the write transistor WT and the read transistor RT through the underlying bottom vias, landing padsand contact plugs. The MTJstands on the SHE, and may be located between the bottom vias, so as to be standing on a path of the write current flowing between the bottom vias. Further, the bit line BL may be formed in another metallization layer over the MTJ, and may extend along the direction X. In some embodiments, the bit line BL is electrically connected to the MTJthrough a top via.

throughare schematic cross-sectional views respectively illustrating a MTJ standing on a SHE, according to some embodiments of the present disclosure.

Referring to, the MTJstanding on the SHEmay be a multilayer structure, and at least includes a free layer, a reference layerand a barrier layersandwiched between the free layerand the reference layer. In some embodiments, the free layerand the reference layerrespectively include at least one ferromagnetic layer, while the barrier layerincludes at least one insulating layer. A magnetization direction of the reference layeris pinned, and a magnetization direction of the free layercan be altered by, for example, the spin Hall effect as described above. When the magnetization directions of the free layerand the reference layerare in the parallel state, the MTJis in the low electrical resistance state. On the other hand, when the magnetization directions of the free layerand the reference layerare in the anti-parallel state, the MTJis in the high electrical resistance state. In addition, the insulating barrier layerprovides isolation between the free layerand the reference layer, while being thin enough to be tunneled through by the read current. In some embodiments, the free layeris formed of a cobalt-iron-boron (CoFeB) alloy, a cobalt-palladium (CoPd) alloy, a cobalt-iron (CoFe) alloy, a cobalt-iron-boron-tungsten (CoFeBW) alloy, a nickel-iron (NiFe) alloy, ruthenium, the like or combinations thereof. In some embodiments, the reference layeris formed of the CoFeB alloy. Moreover, in some embodiments, the barrier layeris formed of magnesium oxide, aluminum oxide, aluminum nitride, the like or combinations thereof. However, those skilled in the art may select other suitable materials for the free layer, the reference layerand the barrier layeraccording to design or process requirements, the present disclosure is not limited thereto.

In some embodiments, the MTJfurther includes a pinning layer. The pinning layermay be disposed on the reference layer, and is configured to pin the magnetization direction in the reference layerby exchange coupling with the reference layer. In some embodiments, the pinning layeris formed of an anti-ferromagnetic material. For instance, the anti-ferromagnetic material may include IrMn, PtMn, or NiMn(0.1<x<0.5). Furthermore, in some embodiments, a synthetic antiferromagnets (SAF) structure (not shown) is further disposed on the reference layer. In these embodiments, the SAF structure may be located between the pinning layerand the reference layer. The SAF structure may enhance the pinning of the magnetization direction in the reference layer, and may include anti-ferromagnetic layers separated by a nonmagnetic spacer layer. For instance, the anti-ferromagnetic layers may respectively include cobalt/platinum (Co/Pt) multilayers, cobalt/palladium (Co/Pd) multilayers or the like, while the spacer layer is such as a ruthenium layer. In alternative embodiments, the MTJincludes the SAF structure for pinning the magnetization direction in the reference layer, while the pinning layeris omitted.

Furthermore, in some embodiments, the MTJfurther includes a capping layeras an outermost layer (e.g., a topmost layer) in the MTJ. In those embodiments where the reference layeris covered by the pinning layer, the capping layermay be disposed on the pinning layer. The capping layermay protect the underlying layer(s) from etching damage and/or oxidation. According to some embodiments, the capping layeris formed of a conductive material, such as tantalum, tantalum nitride, titanium, titanium nitride, the like or combinations thereof. In alternative embodiments, the capping layeris formed of an insulating material. The insulating material may be substantially oxygen-free, and may include silicon nitride.

Referring to, a MTJis similar to the MTJdescribed with reference to, except that the MTJfurther includes an additional free layerand a free layer spacer. The additional free layermay be disposed between the free layerand the barrier layer, and the free layer spacerlies between the free layerand the additional free layer. The magnetization directions in the free layerand the additional free layermay be interlocked with each other. In other words, the magnetization direction in the free layermay be aligned with the magnetization direction in the additional free layer, and the magnetization directions in the free layeras well as the additional free layershould be altered at the same time. Accordingly, the free layerand the additional free layershould be both programmed during a programming operation. Furthermore, as a result of the interlocked magnetization directions in the free layers,, the magnetization directions in the free layers,may be less likely to be accidentally switched when the MTJis not selected to be programmed. Therefore, the MTJmay have an improved data retention ability. As similar to the free layer, the additional free layermay include at least one ferromagnetic layer. The ferromagnetic material for forming the additional free layermay be identical with or different from the ferromagnetic material for forming the free layer, the present disclosure is not limited thereto. In addition, the free layer spacermay be formed of a non-magnetic conductive material. For instance, the non-magnetic conductive material may include tungsten, ruthenium, the like or combinations thereof. Further, the free layer spacermay be formed with a crystalline phase similar to or identical with an expected crystalline phase (e.g., body-centered cubic (BCC) phase) of an overlying free layer (e.g., the additional free layer), so as to provide a preferable growth template for such overlying free layer. Accordingly, this overlying free layer may be formed with improved crystallinity.

Referring to, a MTJincludes two pairs of additional free layerand free layer spacerbetween the free layerand the barrier layer. The pairs of additional free layerand free layer spacermay be stacked on the free layer, and may be covered by the barrier layer. As described above, by further incorporating the additional free layersand the free layer spacers, the MTJmay have an even improved data retention ability.

Referring to, in some embodiments, a diffusion barrieris disposed between the SHEand a MTJ, which may be the MTJas described with reference to, the MTJas described with reference toor the MTJas described with reference to. The diffusion barrieris configured to prevent inter-diffusion between the free layerand the SHE, and may be formed of a non-magnetic conductive material, such as molybdenum.

throughare schematic plan views each illustrating a MTJ standing on a SHE, according to some embodiments of the present disclosure.

Referring to, in some embodiments, a major axis of the MTJis substantially aligned or substantially parallel with a major axis of the SHE, along which a write path is directed. In these embodiments, a magnetization direction M of the free layer(as described with reference to) in the MTJmay also be substantially aligned or substantially parallel with the major axis of the SHE. As an example illustrated in, the major axis of the SHEand the directed write path between the bottom viasare along an in-plane direction D, and the major axis of the MTJas well as the magnetization direction M of the free layerin the MTJare along the in-plane direction Das well. A ratio of a dimension Lof the MTJalong the in-plane direction Dover a dimension Wof the MTJalong another in-plane direction Dperpendicular to the in-plane direction Dmay, for example, range from about 1.5 to about 5.

Referring to, in some embodiments, a major axis of the MTJis intersected with (e.g., perpendicular with) a major axis of the SHE, along with a write path is directed. In these embodiments, a magnetization direction M′ of the free layerin the MTJ, which is substantially aligned with the major axis of the MTJ, may also be intersected with (e.g., perpendicular with) the major axis of the SHE. As an example illustrated in, the major axis of the SHEand the directed write path between the bottom viasare along the in-plane direction D, while the major axis of the MTJas well as the magnetization direction M′ of the free layerin the MTJare along the in-plane direction D. A ratio of the dimension Lof the MTJalong the in-plane direction Dover the dimension Wof the MTJalong the in-plane direction Dmay, for example, range from about 1.5 to about 5.

Referring to, in some embodiments, the MTJis formed in a substantially symmetrical shape. In these embodiments, a magnetization direction M″ of the free layerin the MTJmay be along an out-of-plane direction Dthat is substantially normal to a surface of the SHEin contact with the MTJ. In addition, a ratio of the dimension Lof the MTJalong the in-plane direction Dover the dimension Wof the MTJalong the in-plane direction Dmay be close to or identical with 1.

It should be noted that, the MTJis exemplarily taken for elaborating various configurations of the SHEand a MTJ standing on the SHE. The SHEand the MTJas described with reference tomay have the variations shown inthroughas well. Similarly, the SHEand the MTJas described with reference tomay also have the variations shown inthrough.

throughare schematic cross-sectional views respectively illustrating an intermediate structure for forming the SHE, according to some embodiments of the present disclosure.

Referring to, in some embodiments, a method for forming the SHEincludes depositing a layerby using a co-sputtering process. The as-deposited layercontains the alloy having the heavy metal element and the light transition metal element. During the co-sputtering process, a sputtering target including the heavy metal element and another sputtering target including the light transition metal element are used. By adjusting, for example, power inputs, for the sputtering targets, a composition (e.g., Pt/Cr ration, Pt/V ratio etc.) of the as-deposited layermay be altered. A thermal treatment, such as an annealing process, may be subsequently performed on the as-deposited layer, for forming the SHE. In some embodiments, a process temperature of the thermal treatment ranges from 250° C. to 450° C., and a process time of the thermal treatment ranges from 10 minutes to 60 minutes.

Referring to, in some embodiments, a method for forming the SHEincludes a first sputtering process and a second sputtering process. A first layeris formed by the first sputtering process, and a second layeris formed on the first layerby the second sputtering process. The first layeras well as a sputtering target used in the first sputtering process may include the heavy metal element, while the second layeras well as a sputtering target used in the second sputtering process may include the light transition metal element. Alternatively, the first layeras well as the sputtering target used in the first sputtering process may include the light transition metal element, while the second layeras well as the sputtering target used in the second sputtering process may include the heavy metal element. After deposition of the first and second layers,, a thermal treatment (e.g., an annealing process) may be performed on the first and second layers,, such that the heavy metal element and the light transition metal element in the first and second layers,may inter-diffuse to form the SHE. In some embodiments, a process temperature of the thermal treatment ranges from 250° C. to 450° C., and a process time of the thermal treatment ranges from 10 minutes to 60 minutes. Further, a ratio of a thickness of the first layerover a thickness of the second layermay be adjusted for altering a composition (e.g., Pt/Cr ration, Pt/V ratio etc.) of the SHE, the present disclosure is not limited to the thickness of each of the layers,.

Referring to, in some embodiments, three sputtering processes are performed for forming the SHE. A first layeris formed by a first sputtering process, a second layeris formed on the first layerby a second sputtering process, and a third layeris formed on the second layerby a third sputtering process. The first and third layers,as well as the sputtering targets used in the first and third sputtering processes may include the heavy metal element, while the second layeras well as the sputtering target used in the second sputtering process may include the light transition metal element. Alternatively, each of the layers,,as well as the sputtering target used in the corresponding sputtering process may include the heavy metal element or the light transition metal element, as long as at least one of the layers,,is formed with the heavy metal element and at least one of the layers,,is formed with the light transition metal element. After formation of a stacking structure including the layers,,, a thermal treatment (e.g., an annealing process) may be performed on the stacking structure, such that the heavy metal element and the light transition metal element in the layers,,may inter-diffuse to form the SHE. In some embodiments, a process temperature of the thermal treatment ranges from 250° C. to 450° C., and a process time of the thermal treatment ranges from 10 minutes to 60 minutes. Further, a thickness of each of the layers,,may be adjusted for altering a composition (e.g., Pt/Cr ration, Pt/V ratio etc.) of the SHE, the present disclosure is not limited to the thickness of each of the layers,,.

Referring to, in some embodiments, four sputtering processes are performed for forming the SHE. A first layeris formed by a first sputtering process, a second layeris formed on the first layerby a second sputtering process, a third layeris formed on the second layerby a third sputtering process, and a fourth layeris formed on the third layerby a fourth sputtering process. The first and third layers,as well as the sputtering targets used in the first and third sputtering processes may include the heavy metal element, while the second and fourth layers,as well as the sputtering target used in the second and fourth sputtering processes may include the light transition metal element. Alternatively, each of the layers,,,as well as the sputtering target used in the corresponding sputtering process may include the heavy metal element or the light transition metal element, as long as at least one of the layers,,,is formed with the heavy metal element and at least one of the layers,,,is formed with the light transition metal element. After deposition of a stacking structure including the layers,,,, a thermal treatment (e.g., an annealing process) may be performed on the stacking structure, such that the heavy metal element and the light transition metal element in the layers,,,may inter-diffuse to form the SHE. In some embodiments, a process temperature of the thermal treatment ranges from 250° C. to 450° C., and a process time of the thermal treatment ranges from 10 minutes to 60 minutes. Further, a thickness of each of the layers,,,may be adjusted for altering a composition (e.g., Pt/Cr ration, Pt/V ratio etc.) of the SHE, the present disclosure is not limited to the thickness of each of the layers,,,.

Alternatively, more layers may be formed as initial layers to be interfused to form the SHE. A gradient of the heavy metal element/light transition metal element may vary, according to an amount of the layers for forming the SHE, a thickness of each of these initial layers and/or process temperature/time of the thermal treatment, the present disclosure is not limited thereto. Further, the co-sputtering process or each of the sputtering processes mentioned above may be performed at room temperature. Alternatively, the co-sputtering process or each of the sputtering processes may be performed at elevated temperature.

is a flow diagram illustrating a method for manufacturing adjacent ones of the unit cellseach described with reference to, according to some embodiments of the present disclosure.throughare schematic cross-sectional views illustrating intermediate structures during the manufacturing process as shown in. Particularly,throughare enlarged schematic views illustrating intermediate structures for forming and passivating the SHEand the MTJin a unit cell.throughare schematic plan views of the intermediate structures shown inthrough.

Referring toand, step Sis performed, and the write transistors WT as well as the read transistors RT are formed on a surface region of the substrate. As described with reference toand, each of the unit cellsmay include one of the write transistors WT and one of the read transistors RT. In those embodiments where these transistors are planar-type transistors, the write transistor WT includes a write word line WWL formed over a planar surface of the substrate, and source/drain structuresformed in a shallow region of the substrate. Similarly, the read transistor RT includes a read word line RWL formed over a planar surface of the substrate, and source/drain structuresformed in the shallow region of the substrate. The write word line WWL and the read word line RWL are respectively separated from the substrateby a gate dielectric layer. In some embodiments, the isolation transistors DT are formed along with the write transistor WT and the read transistor RT. In these embodiments, the dummy word lines DWL are respectively formed between a write transistor WT and an adjacent read transistor RT, and respectively separated from the substrateby a gate dielectric layer.

It should be noted that, the write transistors WT, the read transistors RT and the isolation transistors DT are described herein as the planar-type transistors. However, as described with reference to, the write transistors WT, the read transistors RT and the isolation transistors DT may be alternatively formed as fin-type transistors or GAA transistors, and the structures of the elements in the write transistors WT, the read transistors RT and the isolation transistors DT may be modified accordingly.

Referring toand, step Sis performed, and a dielectric layeras well as the contact plugsare formed on the current structure. The dielectric layermay cover the write transistors WT, the read transistors RT and the isolation transistors DT. The contact plugsmay penetrate through the dielectric layerto establish electrical connection with the source/drain structures. In some embodiments, the dielectric layerand the contact plugsare formed by a damascene process (e.g., a single damascene process).

Referring toand, step Sis performed, and a dielectric layeras well as the source lines SL and the landing padsare formed on the dielectric layer. The dielectric layermay laterally surround the source lines SL and the landing pads, and the source lines SL as well as the landing padsare overlapped and electrically connected to the contact plugs. A pair of source line SL and landing padare connected to the source/drain structuresof each write transistor WT through the contact plugsin between. Similarly, a pair of source line SL and landing padare connected to the source/drain structuresof each read transistor RT through the contact plugsin between. In some embodiments, a method for forming the dielectric layer, the source lines SL and the landing padsincludes a damascene process.

Referring toand, step Sis performed, and a dielectric layeras well as the bottom viasare formed on the dielectric layer. The bottom viasmay penetrate through the dielectric layer, to establish electrical connection with the landing pads. In this way, one of the source/drain structuresof each write transistor WT is connected to a source line SL, while the other is connected to a bottom viathrough the landing padand contact plugin between. Similarly, one of the source/drain structuresof each read transistor RT is connected to a source line SL, while the other is connected to a bottom viathrough the landing padand contact plugin between. In some embodiments, a method for forming the dielectric layerand the bottom viasincludes a damascene process (e.g., a single damascene process).

Referring toand, step Sis performed, and a spin Hall material layeris globally formed on the dielectric layer. The spin Hall material layerwill be patterned to form the SHEsas described with reference toand, and is formed of the alloy having the heavy metal element and the light transition metal element. As described with reference tothrough, a method for forming the spin Hall material layermay include a single co-sputtering process or multiple sputtering processes, and may include a subsequent thermal treatment.