Package structure and manufacturing method thereof

This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 18/162,671, filed on Jan. 31, 2023, which is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/192,816, filed on Mar. 4, 2021 and issued as U.S. Pat. No. 11,587,916. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.

Semiconductor devices and integrated circuits are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for the wafer level packaging.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In addition, terms, such as “first”, “second”, “third” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

toare schematic cross-sectional views of various stages in a manufacturing method of a package structure according to some exemplary embodiments of the present disclosure. In exemplary embodiments, the manufacturing method is part of a wafer level packaging process. It is to be noted that the process steps described herein cover a portion of the manufacturing processes used to fabricate a package structure. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.are schematic top views illustrating the antenna patterns according to some exemplary embodiments of the present disclosure.

Into, two dies are shown to represent plural dies of the wafer, and one or more package structures are shown to represent plural (semiconductor) package structures obtained following the (semiconductor) manufacturing method, the disclosure is not limited thereto.

Referring to, in some embodiments, a carrieris provided. In some embodiments, the carrieris a glass carrier or any suitable carrier for the semiconductor manufacturing. Referring to, the carrieris provided with a buffer layercoated thereon. In some embodiments, the buffer layermay include a die attach film made of a polymer-based dielectric material, such as epoxy adhesives. In some embodiments, the buffer layeralso includes a debonding layer made of any material suitable for bonding and debonding the carrierfrom the above layer(s) or any wafer(s) disposed thereon. In some embodiments, the buffer layerincludes an epoxy-based thermal-release material, which loses its adhesive property when being heated, such as a light-to-heat-conversion (LTHC) release coating film. In alternative embodiments, the buffer layerincludes an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. In some embodiments, the buffer layermay be dispensed as a liquid and cured, or may be a laminate film laminated onto the carrier, or the like. A top surface of the buffer layer, which is opposite to a bottom surface contacting the carrier, may have a high degree of coplanarity. In some embodiments, the buffer layeris, a LTHC layer with good chemical resistance, and such layer enables room temperature debonding from the carrierby applying laser irradiation.

In, in some embodiments, antenna substrate structureis provided and disposed on the carrier. The antenna substrate structureis attached to the carrierthrough the buffer layer. In some embodiments, the antenna substrate structureincludes an antenna patternhaving multiple antenna elementsformed in a circuit substrate. In some embodiments, the circuit substrateis a print circuit board (PCB), a flexible PCB or any suitable laminated circuit substrate. The circuit substrateof the antenna substrate structureincludes a bottom laminated layeron the carrier, a core layeron the bottom laminated layer, and a top laminated layeron the core layer. The bottom laminated layerand the top laminated layermay also be referred to as the build-up layers.

In some embodiments, the core layeris or includes one or more layers of pre-preg (e.g., a fiberglass matrix injected with an epoxy resin, such as FR-4). For example, the pre-preg layer includes metal foils (e.g., copper foil) on both opposing surfaces, and through-holes are formed through the pre-preg layer and plated with a metal (e.g., copper) to form through vias. The metal foils on the two opposing surfaces may be etched or patterned using photolithographic and etch processes to form metallization layers,respectively on the two opposing surfaces of the core layer. In some embodiments, the metallization layers,include metal lines. The through viasof the core layerelectrically connect the metallization layers,on opposing surfaces of the core layer

As illustrated in, the bottom laminated layerand the top laminated layerare formed on the metallization layers,at the two opposite surfaces of the core layer. The bottom laminated layerand the top laminated layer, in some examples, are Ajinomoto Build-up Films (ABF) or the like, and are laminated or formed by another process on the metallization layers,of the core layer

In some embodiments, the bottom laminated layeris formed with a metallic antenna patternof multiple antenna elements. In some embodiments, the material of the antenna elementsincludes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the antenna elementsmay include patch antennas. For example, as shown in, the antenna elementsinlaid in the bottom laminated layerare referred as broadside radiation antennas. In some embodiments, the antenna elements emit and/or receive the electromagnetic waves long the Z direction (polarizing in the Z direction). As the antenna substrate structureis attached to the buffer layerwith the bottom laminated layerfacing the carrier, the antenna patterndirectly contacts the buffer layer.

are schematic top views showing the antenna patternsof the antenna substrate structureaccording to various embodiments. In some embodiments, the antenna elementsare arranged in arrays, such as the N×M array or N×N arrays (N, M are positive integers, N may or may not be equal to M). For example, in, the antenna elementsare arranged as an 1×4 array, and in, the antenna elementsare arranged as a 2×2 array. In some embodiments, the shape of the antenna elementsmay be designed to be square, rectangular, hexagonal or any suitable polygonal shape according to the desired properties of the antenna. The size of the array for the antenna elementscan be designated and selected based on the desired properties.

As shown in, the metallization layerlocated on the lower surface of the core layeris formed with patternscorresponding to the antenna pattern. As shown in, in some embodiments, the locations of the patternsin the metallization layervertically align with or at least overlap with the locations of the antenna elements. In some embodiments, the metallization layerlocated on the upper surface of the core layeris formed with patterns. For example, some patternsare connected with the through vias, and the through viasare connected with the patternsat locations vertically aligned with the antenna pattern. In some embodiments, the antenna elementsare electrically coupled with the metallization layer, and further with the metallization layerand the through vias. In other words, the metallization layermay serve as a ground plate, and the metallization layerand the through viasmay serve as feed-lines for the antenna elements.

In, in some embodiments, conductive pillarsare formed on the top surface of the top laminated layerand are connected with the metallization layer. For example, the conductive pillarsmay be considered as contacts or contact terminals for the antenna substrate structure. In some embodiments, the material of the conductive pillarsincludes copper, copper alloys or the like, and may be formed by electroplating, for example. In some embodiments, the conductive pillarsare electrically connected with the metallization layers,and the through vias.

Referring to, in some embodiments, an insulating encapsulantis formed over the carrierand on the buffer layer. The insulating encapsulantis formed to laterally wrap the antenna substrate structure(i.e. cover sidewalls of the antenna substrate structureand surround the antenna substrate structure). In some embodiments, the insulating encapsulantis formed by a molding process or an over-molding process. For example, the insulating encapsulantis formed over the top laminated layerand the conductive pillarsto cover the conductive pillars, and then planarized to expose the conductive pillars. In some embodiments, sidewallsof the conductive pillarsare surrounded and covered by the insulating encapsulant, and the top surfacesof the conductive pillarsare exposed. In, in some embodiments, the top surfacesof the conductive pillarsare substantially levelled with and coplanar to the top surfacesof the insulating encapsulant. The planarizing process may include, for example, performing a mechanical grinding or polishing process or a chemical mechanical polishing (CMP) process to the over-molded insulating encapsulant. In some embodiments, during the planarizing process, portions of the conductive pillarsmay also be removed. After the planarizing process, a cleaning step may be optionally performed, for example, to clean and remove the residue generated from the planarizing step.

In some embodiments, the insulating encapsulant, for example, is a molding compound made of a polymeric material (such as epoxy resins, phenolic resins, silicon-containing resins, or other suitable resins), a dielectric material having low permittivity (Dk) and low loss tangent (Df) properties, or other suitable materials. In some embodiments, a dielectric material having low permittivity (Dk) and low loss tangent (Df) properties refers to a dielectric material having a Dk value smaller than or substantially equal to 4, and a Df value smaller than or substantially equal to 0.009. Depending on the frequency range of the high-speed applications, suitable materials of the insulating encapsulantmay be selected based on the required electrical properties of the package structure. In some embodiments, the insulating encapsulantmay further include inorganic filler or inorganic compound (e. g. silica, clay, etc.) as additive added therein to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulant. In some embodiments, the material of the insulating encapsulantis different from the material of the core layer

Referring to, in some embodiments, a redistribution layeris formed on the insulating encapsulantand the conductive pillars. In some embodiments, the redistribution layeris formed on the top surface of the insulating encapsulantand the top surfaces the conductive pillars. In some embodiments, the redistribution layeris mechanically and electrically connected with the conductive pillars, as shown in.

In some embodiments, the formation of the redistribution layerincludes sequentially forming one or more dielectric layersand one or more metallization layersin alternation. The number of the dielectric layers and the metallization layers is determined according to the desired properties of the package structure. In some embodiments, the metallization layersare illustrated to be embedded in the dielectric layers. In some embodiments, the metallization layer(s) includes metal viasand metal routingsinterconnected through the metal vias. In some embodiments, the metallization layersare electrically and mechanically connected to the conductive pillarsthrough one or more metal vias. For example, in, the metal viasof the lower metallization layerare physically connected to the conductive pillars. The number of the metal viasconnects to each of the conductive pillarsmay be one or more than one, according to the desired properties of the package structure. In some embodiments, the metal viasin the topmost layer of the metallization layersmay be exposed by the topmost layer of the dielectric layersfor further connecting later-formed elements.

In some embodiments, the material of the dielectric layersincludes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable poly-based dielectric material. The dielectric layers may be formed by deposition. In some embodiments, the material of the metallization layersincludes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The metallization layersmay be formed by electroplating or deposition.

Referring to, in some embodiments, a seed layeris formed on the redistribution layerand conductive viasare formed on the seed layer. In some embodiments, the conductive viasmay be through integrated fan-out (InFO) vias (TIV). The conductive viasand the seed layerare electrically connected with the redistribution layer. For simplification, only four conductive viasare presented infor illustrative purposes, however, the number of the conductive viasmay be selected based on the product requirements.

In some embodiments, the formation of the seed layerincludes blanketly forming one or more layers of metal or metal alloy materials over the redistribution layerand covering the redistribution layer. In some embodiments, the seed layeris a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layermay include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the seed layermay include a titanium layer and a copper layer over the titanium layer. The seed layermay be formed by using, for example, chemical vapor deposition (CVD), sputtering, or physical vapor deposition (PVD).

In some embodiments, the formation of the conductive viasincludes forming a patterned photoresist layer (not shown) with opening on the seed layer, where portions of the seed layerare exposed by the openings of the patterned photoresist layer. Later, the conductive viasare formed within the openings of the patterned photoresist layer respectively. In some embodiments, the conductive viasare formed by forming a metallic material filling the openings to form the conductive viasby plating or deposition. In some embodiments, the material of the conductive viasmay include a metal material such as copper or copper alloys, or the like.

After the conductive viasare formed, the patterned photoresist layer is removed by performing an ashing or stripping process using an oxygen plasma, for example. In some embodiments, during the removal of the patterned photoresist layer, the uncovered seed layeris also removed. In some embodiments, following the removal of the patterned photoresist layer, the seed layerthat is not covered by the conductive viasis removed. In some embodiments, the seed layeris etched off by using the conductive viasas an etching mask. In some embodiments, the etching process may include a dry etching process or a wet etching process. In some embodiments, the remained portions of the seed layersare located below the conductive viasand are mechanically and electrically connected to the respective conductive vias.

Referring to, in some embodiments, semiconductor diesare provided onto the redistribution layer. In some embodiments, the semiconductor dieis disposed on the redistribution layerthrough a die attach film. In some embodiments, the die attach filmmay be applied to a backside surfaceof the semiconductor die, then the backside surfaceof the semiconductor dieis attached to the redistribution layerby placing the die attach filmbetween the semiconductor dieand the redistribution layer. With the die attach film, a better adhesion between the semiconductor dieand the redistribution layeris ensured. For example, in, the redistribution layeris located at the backside surfaceof the semiconductor die, so that the redistribution layermay be referred as a back-side redistribution layer relative to the semiconductor dies. In some embodiments, the conductive viassurround the positioning location(s) of the semiconductor die(s).

In some embodiments, the semiconductor dieincludes an active surfaceand the backside surfaceopposite to the active surface. Also, the semiconductor dieincludes padsdistributed on the active surface, a passivation layercovering the active surfaceand exposing portions of the pads, conductive pillarsconnected to the exposed portions of the pads, a protection layercovering the passivation layerbut exposing the conductive pillars

Referring to, the padsare partially exposed by the passivation layer, and the conductive pillarsare disposed on and electrically connected to the pads. The protection layercovers the passivation layerand the conductive pillars

In some embodiments, the padsmay be aluminum pads or other suitable metal pads. In some embodiments, the conductive pillarsare copper pillars, copper alloy pillars or other suitable metal pillars, for example. In some embodiments, the passivation layerand/or the protection layermay be a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable polymers. In some alternative embodiments, the passivation layerand/or the protection layermay be made of inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. In certain embodiments, the materials of the passivation layerand the protection layermay be the same or different.

In some embodiments, the semiconductor diedescribed herein may be referred as a chip or an integrated circuit (IC). In certain embodiments, the semiconductor dieincludes one or more digital chips, analog chips or mixed signal chips, such as application-specific integrated circuit (“ASIC”) chips, sensor chips, wireless and radio frequency (RF) chips, memory chips, logic chips or voltage regulator chips. In certain embodiments, the semiconductor diemay further include additional semiconductor chip(s) of the same type or different types. In some embodiments, the semiconductor dieincludes at least a radio frequency integrated circuit (RFIC) or a RF chip configured to process and/or generate the RF signals received and/or received from the antenna elements.

Referring to, in some embodiments, an insulating encapsulantis formed to laterally wrap the conductive viasand the semiconductor dies(i.e. cover side walls of the conductive viasand the semiconductor diesand surround the conductive viasand the semiconductor dies). The formation methods and materials of the insulating encapsulantare similar to the methods and materials for forming the insulating encapsulantas described in, and shall not be repeated herein.

In some embodiments, the insulating encapsulantat least fills up the gaps between the conductive vias, the gaps between the conductive viasand the semiconductor die, the gaps between the semiconductor dies, and covers the topmost layer of the dielectric layersnot covered by the conductive viasand the semiconductor dies. In some embodiments, a material of the insulating encapsulantmay be substantially the same as the material of the insulating encapsulant. In an alternative embodiment, the material of the insulating encapsulantmay be different from the material of the insulating encapsulant.

Similarly, in some embodiments, the insulating encapsulantmay be planarized until the conductive viasand the conductive pillarsof the semiconductor diesare exposed from the insulating encapsulant. In some embodiments, as shown in, after the planarization, top surfacesof the conductive viasand top surfacesof the conductive pillarsof the semiconductor diesbecome substantially levelled with and coplanar with the top surfaceof the insulating encapsulant. That is, for example, the top surfaces of the conductive pillarsand the protection layerof the semiconductor dieand the top surfacesof the conductive viasare levelled with the top surfaceof the insulating encapsulant.

Referring to, in some embodiments, a redistribution layeris formed on the insulating encapsulant. In certain embodiments, the redistribution layeris formed over and covers the conductive vias, the semiconductor diesand the insulating encapsulant. As shown in, the semiconductor diesand the conductive viasare sandwiched between the redistribution layerand the redistribution layer, and the conductive viaselectrically connect the redistribution layerand the redistribution layer. In some embodiments, the redistribution layeris electrically connected with the semiconductor diesand the conductive vias, as shown in. In some embodiments, the semiconductor diesare electrically connected with the redistribution layerand the redistribution layerthrough the conductive viasand the seed layer. The redistribution layerand the redistribution layerfunction as electrical connection structures. In some embodiments, the redistribution layeris electrically connected to the antenna substrate structurethrough the conductive vias, the seed layer, the redistribution layer. In some embodiments, the redistribution layeris electrically connected to the semiconductor diethrough the conductive pillars

In some embodiments, the redistribution layerincludes one or more dielectric layersand one or more metallization layersarranged in alternation. In certain embodiments, one or more the metallization layersmay include metal viasand metal routingsmechanically and electrically interconnected through the metal vias. In some embodiments, the metallization layeris sandwiched between the dielectric layers, but the top surface of the metallization layeris exposed by the topmost layer of the dielectric layersand the lowest layer of the metallization layeris exposed by the lowest layer of the dielectric layersto connect the conductive viasand the conductive pillars. The number of the dielectric layersand the metallization layersincluded in the redistribution layeris determined according to the desired properties of the package structure. In some embodiments, the materials of the dielectric layersand the dielectric layersmay be the same or different. In some embodiments, the materials of the metallization layersand the metallization layersmay be the same or different.

Referring to, in some embodiments, under-ball metallurgy (UBM) patternsmay be formed on the top surface of the topmost layer of the metallization layersexposed by the topmost layer of the dielectric layersfor electrically connecting with conductive elements (such as conductive balls) or other additional semiconductor element (e.g., passive components or active components)). In some embodiments, the materials of the UBM patternsmay include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed by an electroplating process, for example. The number of the UBM patternscorresponds to the number of portions of the top surface of the topmost layer of the metallization layersexposed by the topmost layer of the dielectric layers.

Referring to, after the redistribution layerand the UBM patternsare formed, a plurality of conductive elementsare formed on the redistribution layerand are electrically connected to the redistribution layerthrough the UBM patterns. In some embodiments, the redistribution layeris located between the insulating encapsulantand the conductive elements, between the semiconductor dieand the conductive elements, and between the conductive viasand the conductive elements. As shown in, the conductive elementsare mechanically and electrically connected to the UBM patterns. In some embodiments, the conductive elementsmay be disposed on the UBM patternsby ball placement process or reflow process. In some embodiments, the conductive elementsare, for example, solder balls or ball grid array (BGA) balls.

In some embodiments, the conductive elementsare electrically connected to the redistribution layerthrough the UBM patterns. In some embodiments, some of the conductive elementsare electrically connected to the semiconductor diethrough the UBM patterns, the redistribution layerand the conductive pillars. In some embodiments, the conductive elementsare electrically connected to some of the conductive viasthrough the UBM patternsand the redistribution layer. In some embodiments, some of the conductive elementsare electrically connected to the redistribution layerthrough the UBM patterns, the redistribution layer, and some of the conductive vias. In some embodiments, the conductive elementsare electrically connected to the antenna substrate structurethrough the UBM patterns, the redistribution layer, some of the conductive vias, and the redistribution layer.

Referring to, in some embodiments, the carrieris debonded from the antenna substrate structureand the insulating encapsulant. In some embodiments, the antenna substrate structureand the insulating encapsulantare easily separated from the carrierdue to the buffer layer. In some embodiments, the carrieris detached from the antenna substrate structureand the insulating encapsulantthrough a debonding process, and the carrieris removed. The antenna substrate structureand the insulating encapsulantare covered by the buffer layer. As shown in, the bottom surfaces of the insulating encapsulantand the antenna substrate structureare covered by the buffer layer. That is, the bottom surfaces of the antenna elementsare not covered by the insulating encapsulant. In alternative embodiments, the carrieris detached from the antenna substrate structureand the carrierand the buffer layerare removed, so that the antenna substrate structureand the insulating encapsulantare exposed.

In some embodiments, the debonding process is a laser debonding process. During the debonding step, a holding device may be utilized to secure the package and the package may be held by the side where the conductive elementsreside. In some embodiments, the holding device may be an adhesive tape, a carrier film or a suction pad (not shown). Continued on, in some embodiments, a dicing process is performed to cut the wafer into individual and separated package structure. In some embodiments, the dicing process is a wafer dicing process including mechanical blade sawing or laser cutting or any suitable dicing process.

The package structurecomprises an antenna substrate structure, and a semiconductor die, wherein semiconductor dieis placed on the antenna substrate structure. The antenna substrate structurecomprises antenna elementsplaced on the bottom laminated layer. The semiconductor dieis covered by the insulating encapsulant. The semiconductor dieelectrically connects to the antenna substrate structurethrough the conducive pillars, the redistribution layer, the conductive vias, and the redistribution layer. Since the antenna elementsare arranged on the antenna substrate structure, by arranging the antenna substrate structureon the InFO package comprising the semiconductor die, the conductive vias, the thickness of the InFO package may be reduced and cost of production may also be reduced.

Referring to, the package structureis similar to the package structureillustrated in. The difference between the package structureand the package structure I lies in that the package structurefurther includes conductive viasbeing formed on the seed layerand disposed aside the semiconductor die. The conductive viasform dipole antennas. The formation method and material of the conductive viasare similar to the process and materials for forming the conductive viasas described in. As shown in, when the patterned photoresist layer is formed on the seed layer, portions of the seed layerare exposed by the openings of the patterned photoresist layer. Later, the conductive viasandare formed within the openings of the patterned photoresist layer respectively. In some embodiments, the conductive viasandare formed by plating process or any other suitable method, which the plating process may include electroplating or electroless plating, or the like. In some embodiments, the conductive viasandare formed by forming a metallic material filling the openings to form the conductive viasandby plating or deposition. In some embodiments, the material of the conductive viasandmay include a metal material such as copper or copper alloys, or the like.

After the conductive viasandare formed, the patterned photoresist layer is removed by performing an ashing or stripping process using an oxygen plasma, for example.

In some embodiments, following the removal of the patterned photoresist layer, the seed layerthat is not covered by the conductive viasorare removed. In some embodiments, the seed layeris etched off by using the conductive viasoras etching masks. In some embodiments, the etching process includes a dry etching process or a wet etching process. In some embodiments, the remained portions of the seed layersare located below the conductive viasandand are mechanically and electrically connected to the conductive viasand.

Referring to, in some embodiments, the conductive viasinclude conductive viasand/or. The conductive viasconstitute the antenna element ATNv, which form a dipole antenna, where a part of the redistribution layeror a part of the redistribution layerserves as a feed line of the antenna element ATNv, and the other one is electrically grounded or floated. The conductive viasconstitute the antenna element ATNh, which form a dipole antenna, where a part of the redistribution layeror a part of the redistribution layerserves as a feed line of the antenna element ATNh, and the other one is electrically grounded or floated.

For example, as shown in, the package structuremay include one or more antenna elements ATNv formed by the conductive vias, as shown in, and one or more antenna elements ATNh formed by the conductive vias, as shown in. The antenna elements ATNv are referred as an end-fire radiation antenna with a polarization direction, for example, along a direction Y, as shown in. The antenna elements ATNh are referred as an end-fire radiation antenna with a polarization direction, for example, along a direction Y, as shown in). That is, the polarization of electromagnetic waves emitted from the antenna element is perpendicular to emitting surface(s) of the antenna element.

Referring to, in some embodiments, the antenna elements ATNv are configured as two strips arranged parallel with different lengths and are arranged beside the semiconductor die. The two conductive viasused to constitute one antenna element ATNv are in rectangular shape. Along the X direction, one of the two conductive viasused to constitute one antenna element ATNv has a length Land the other one has a length L, where the conductive viahaving the length Lis between the semiconductor dieand the conductive viahaving the length L. The length Lis smaller than length L. In some embodiments, the conductive viawith length Lis electrically connected to a part of the redistribution layeror a part of the redistribution layer, which serves as a feed line of the antenna element ATNv; and the conductive viawith length Lis electrically grounded or floated, and is referred as a ground plate/line of the antenna element ATNv. For example, as shown in, the antenna elements ATNv are referred as end-fire radiation antennas of vertical polarization (e.g. polarizing in the Y direction). The polarization of the electromagnetic waves emitted by the antenna elements ATNv (polarizing in the Y direction) is perpendicular to the polarization of the electromagnetic waves emitted by the patch antennas of the antenna elements(polarizing in the Z direction).

Referring to, in some embodiments, from the top view of the package structure, the package structureincludes one or more antenna elements ATNh along the X direction, and each antenna element ATNh includes two conductive viasand is located aside of the semiconductor die(the location of the semiconductor dieis shown in dotted line in). From the top view, the two conductive viasare L-shaped and are arranged with short sides facing each other. In some embodiments, one of the two conductive viasof the antenna element ATNh is electrically connected to a part of the redistribution layeror a part of the redistribution layer, which serves as a feed line of the antenna element ATNh; and the other conductive via, which is electrically connected to the other one of a part of the redistribution layeror a part of the redistribution layerand is electrically grounded, serves as a ground plate/line of the antenna element ATNh. For example, as shown in, the antenna elements ATNh are referred as end-fire radiation antennas of horizonal polarization (e.g. polarizing in the X direction). The polarization of the electromagnetic waves emitted by the antenna elements ATNh (polarizing in the Y direction) is perpendicular to the polarization of the electromagnetic waves emitted by the patch antennas of the antenna elements(polarizing in the Z direction).

In some embodiments, the antenna elements ATNv and the antenna elements ATNh are located beside the semiconductor dieand located at two opposite sides of the semiconductor die. The arrangement and numbers of the antenna elements ATNv and the antenna elements ATNh may be adjusted according to the desired properties to what is illustrated in. In some embodiments, the antenna elements ATNv and the antenna elements ATNh may be arranged together according to the desired properties.

By arranging the antenna elements ATNv and ATNh in the desired direction and positions, the antenna elements ATNv and ATNh together may emit/receive electromagnetic waves covering all directions in the XY plane. Furthermore, since the antenna elementsof the antenna substrate structureemitting/receiving the electromagnetic waves along the Z direction, a coverage range of the electromagnetic waves in the package structureis increased, and thus the efficiency of the antenna application of the package structureis enhanced.