Average current regulation for DC-DC power converters

The disclosure relates generally to integrated circuit technology, and particularly to current regulation for DC-DC power converter circuits.

Switching power converters can be used to create a direct current (“DC”) output from a regulated or unregulated voltage source by switching current through a magnetic element such as an inductor. DC-DC power converters may receive a regulated or unregulated DC voltage from an upstream power supply, and provide a regulated DC output current and/or DC output voltage to a load. In automotive lighting applications, for example, a DC-DC power converter may receive an unregulated DC voltage from a battery, and may provide a regulated DC output current to a set of light-emitting diodes (LEDs) coupled in series with each other. In such automotive lighting applications, different LEDs from within the set may be disabled at a given time by a pixel controller. The pixel controller may selectively control the projection of light from the set of LEDs by controlling switches that may short circuit certain selected LEDs at a given time.

The inventors of embodiments of the present disclosure have recognized that changing load conditions, including a changing number of LEDs coupled in series, may result in changes to the output voltage. The inventors of embodiments of the present disclosure have also recognized that a current regulation loop utilized to maintain the average current through a set of LEDs must respond quickly to such changes to the load and the output voltage conditions to avoid unwanted flickering. Embodiments of the present disclosure may address one or more of these challenges.

Details of one or more embodiments are set forth in the description below and the accompanying drawings. Other features will be apparent from the description, drawings, and from the claims. The embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art understands that the following description has broad application, and the discussion of any embodiment is meant to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Various terms are used to refer to particular system components. Different companies may refer to a component by different names, and this disclosure does not intend to distinguish between components that differ in name but not form and function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “coupled” is intended to mean either an indirect or direct connection. Thus, if a first device couples to, or is coupled to, a second device, that connection between the first device and the second device may be through a direct connection or through an indirect connection via other devices and connections.

1 FIG. 1 FIG. 1 FIG. 100 100 100 102 104 104 106 108 108 104 104 a n a n a n illustrates a schematic diagram of an LED lighting systemin accordance with embodiments of the present disclosure. LED lighting systemmay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, LED lighting systemmay include a LED driver, a plurality of LEDs-coupled in series with each other, and a pixel controllerincluding a plurality of pixel switches-coupled in series with each other and in parallel to the respective LEDs-as shown in.

102 104 104 102 10 40 10 10 40 10 40 10 40 10 40 10 40 104 104 40 10 40 a n a n 1 FIG. 1 FIG. LED drivermay include one or more DC-DC power converter stages, which may operate together to provide a regulated output current IOUT to drive the plurality of LEDs-at a desired brightness. For example, LED drivermay include boost converterand buck converter. The input of boost convertermay be coupled to the battery voltage supply VBAT. Boost convertermay be a step-up converter and may provide an output voltage higher than VBAT. As shown in, buck convertermay have an input VIN coupled to the output of boost converter. Buck convertermay be a step-down converter, and may provide a regulated output current IOUT at an output voltage VOUT level lower than the voltage level of VIN. Although the embodiment illustrated inincludes both boost converterand buck converter, some embodiments may omit boost converterand may couple the input VIN of buck converterdirectly to the battery voltage supply VBAT. For example, in automotive applications with a 12 volt battery, boost convertermay be utilized to step-up the 12 volt battery voltage to a higher voltage level suitable to provide buck converterthe head room to regulate the output current IOUT at a high enough output voltage VOUT level to turn on the plurality of LEDs-. As another example, in automotive applications with a 48 volt battery, the 40 volt battery output may provide sufficient head room for buck converter. In such other applications, boost convertermay be omitted, and the input VIN of buck convertermay be coupled directly to the battery voltage supply VBAT.

10 10 11 12 13 14 15 16 11 21 12 12 21 14 13 21 30 10 14 12 15 12 16 16 30 10 15 10 16 12 10 1 FIG. Boost convertermay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, boost convertermay include inductor, switch, diode, sense resistor, sense circuit, and boost controller. Inductormay be coupled in series between a battery voltage supply VBAT and switching node. In some embodiments, switchmay be an n-type metal-oxide semiconductor field-effect transistor (“n-type MOSFET” or “NMOS transistor”). Switchmay have a drain coupled to switching node, and a source coupled in series with sense resistorto ground GND. Diodemay have an anode coupled to switching node, and a cathode coupled to capacitorat the output of boost converter. The resistance of sense resistormay generate a sense voltage representative of the current through switch. Sense circuitmay sense the sense voltage, and thereby the current through switch, and provide an output representative of the sensed current to boost controller. As shown in, boost controllermay also receive a feedback signal representative of the boost output voltage provided to capacitorat the output of boost converter. In response to the current feedback from sense circuitand the output voltage feedback from the output of boost converter, boost controllermay control the duty cycle and the frequency at which switchis turned on and off to regulate the voltage and/or current that is transferred to the output of boost converter.

40 40 30 10 1 FIG. Buck convertermay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, and as shown in, buck convertermay include an input VIN coupled to capacitorand the output of boost converter. And as described above, in other embodiments, VIN may be coupled directly to the battery voltage supply VBAT.

40 41 42 43 44 46 41 42 41 40 51 42 51 43 51 52 40 44 52 40 Buck convertermay include high-side transistor, low-side transistor, inductor, output capacitor, and buck controller. In some embodiments, high-side transistorand low-side transistormay be implemented at NMOS transistors. High-side transistormay have a drain coupled to the input VIN of buck converterand a source coupled to switching node. Low-side transistormay include a drain coupled to switching nodeand a source coupled to ground GND. Inductormay be coupled between switching nodeand an output nodeof buck converter. Output capacitormay be coupled between the output nodeof buck converterand ground GND.

1 FIG. 1 FIG. 46 41 42 46 41 42 41 42 41 42 46 41 46 42 46 41 42 104 104 a n. As shown in, buck controllermay be coupled to drive the gates of high-side transistorand low-side transistor. Buck controllermay drive high-side transistorin an opposite manner as low-side transistor. For example, when high-side transistoris driven in an on-state, low-side transistormay be driven in an off-state. Similarly, when high-side transistoris driven in an off-state, low-side transistormay be driven in an on-state. As shown in, buck controllermay receive an high-side current-sense signal ISENSE_HS indicative of the current through high-side transistor. Buck controllermay also receive a low-side current-sense signal ISENSE_LS indicative of the current through low-side transistor. Buck controllermay in turn control the duty cycle and the frequency at which high-side transistorand low-side transistorare respectively switched on and off to regulate the output current IOUT at a desired level according to the desired brightness of the plurality of LEDs-

1 FIG. 1 FIG. 2 9 FIGS.A- 100 104 104 40 106 108 108 104 104 108 108 104 104 104 104 106 104 104 108 108 104 104 104 104 46 a n a n a n a n a n a n a n a n a n a n As shown in, LED lighting systemmay include an N number of LEDsthroughcoupled in series between the output of buck converterand ground GND. Pixel controllermay similarly include an N number of pixel switches-, each corresponding to one of the N number of LEDs-. As shown in, each of the pixel switches-may be coupled in parallel to a respective one of the LEDs-, and may thus be configured to selectively short circuit a respective one of the LEDs-to turn that particular LED off. For example, in automotive headlamp applications, pixel controllermay dynamically guide the light collectively emitted by LEDs-by selectively turning pixel switches-on and off to dynamically enable and disable different LEDs from among the plurality of LEDs-. In addition, any one or more of LED-may be pulsed on and off at a high-frequency to control the effective brightness of the respective LED. When the number of enabled LEDs changes, the required output voltage VOUT to drive the enabled LEDs at the desired output current IOUT may change. As described in further detail below with reference to, a buck controller such as buck controllermay be configured to respond quickly to changes at the output, and thereby maintain regulation of the output current IOUT (and the resulting brightness of the enabled LEDs) at a desired level despite transient output voltage VOUT changes.

2 FIG.A 2 FIG.A 2 FIG.A 1 FIG. 200 200 200 201 43 44 104 104 106 200 a n illustrates a schematic diagram of LED lighting systemin accordance with embodiments of the present disclosure. LED lighting systemmay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, LED lighting systemmay include DC-DC converter circuit, inductor, output capacitor, as well as a plurality of LEDs-. For the sake of simplicity, pixel controlleris omitted from, but may also be included in LED lighting systemin a similar manner as described above with reference to.

201 201 46 41 42 201 202 41 42 41 42 201 202 41 42 201 201 201 41 42 43 44 40 43 44 201 201 1 FIG. 2 FIG.A 2 FIG.A 1 FIG. DC-DC converter circuitmay be implemented in any suitable fashion according to the operation described in the present disclosure. DC-DC converter circuitmay represent an embodiment of buck controllertogether with high-side transistorand low-side transistoras described above with reference to. As shown in, DC-DC converter circuitmay include control circuit, high-side transistor, and low-side transistor. In some embodiments, high-side transistorand low-side transistormay be implemented in the same monolithic integrated circuit as other components of DC-DC converter circuitincluded within control circuit. Thus, as illustrated in, high-side transistorand low-side transistormay be considered part of DC-DC converter circuitalong with the other elements of DC-DC converter circuitdescribed herein. DC-DC converter circuit, including high-side transistorand low-side transistor, along with inductorand output capacitormay form a DC-DC converter that may collectively serve as an embodiment of buck converterdescribed above with reference to. Inductormay be coupled between the switching node VSW and an output of the DC-DC converter, while capacitormay be coupled to the output of the DC-DC converter. In some embodiments, DC-DC converter circuitmay be utilized in an application to drive LEDs, and thus may also be referred to herein as an LED driver circuit. However, DC-DC converter circuitis not limited to LED driver circuit applications and may be utilized in any other suitable DC-DC converter application to provide a regulated output current.

202 41 42 201 202 41 42 41 42 202 41 42 201 41 42 202 202 Control circuitmay be configured to drive high-side transistorand low-side transistorto regulate the average current of DC-DC converter circuit. As described below, control circuitprovide, for example, a hysteretic control over high-side transistorand low-side transistor, whereby high-side transistorand low-side transistorare controlled in response to the high-side current and the low-side current crossing peak and valley thresholds respectively. Control circuitmay thus also be referred to as a hysteretic control circuit configured to drive high-side transistorand low-side transistorin response to the peak threshold and a valley threshold to regulate an average current of DC-DC converter circuit. In some embodiments, the switching frequency of high-side transistorand low-side transistormay be allowed to vary as a function of the hysteretic control. In other embodiments, control circuitmay include additional control features, that in addition to the hysteretic operation of control circuit, may control and/or limit the switching frequency to a desired range.

2 FIG.A 202 212 214 216 220 230 240 251 252 261 262 270 41 42 As shown in, control circuitmay include timer circuit, peak-and-valley controller, curvature compensation circuit, peak-and-valley reference generator, average-current reference generator, pulse-width modulation (PWM) circuit, peak comparator, valley comparator, high-side comparator, low-side comparator, buck comparator, as well as high-side transistorand low-side transistor.

41 42 41 42 High-side transistormay be coupled between a first input supply node, such as VIN, and a switching node VSW. Low-side transistormay be coupled between the switching node VSW, and a second input supply node, such as ground GND. High-side transistorand low-side transistormay be turned on and off to regulate the average output current IOUT of the buck converter.

240 251 252 41 42 240 41 42 41 41 43 251 41 220 251 240 41 42 42 43 42 252 42 220 252 240 42 41 PWM circuitmay be configured to receive a peak signal CP from peak comparator, receive a valley signal from valley comparator, and drive high-side transistorand low side transistorin response to the peak signal CP and the valley signal CV. For example, at the beginning of a switching cycle, PWM circuitmay drive high-side transistorin an on-state and low-side transistorin an off-state. During the on-time of high-side transistor, the high-side current through high-side transistorand inductorwill rise. Peak comparatormay be configured to compare the high-side current through high-side transistoragainst a peak threshold provided by peak-and-valley reference generator. When the high-side current reaches and crosses above the peak threshold, peak comparatormay assert a peak signal CP to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. During the on-time of low-side transistor, the low-side current through inductorand low-side transistormay decrease from a value at or near the peak threshold. Valley comparatormay be configured to compare the low-side current through low-side transistoragainst a valley threshold provided by peak-and-valley reference generator. When the low-side current reaches and crosses below the valley threshold, valley comparatormay assert a valley signal CV to instruct PWM circuitto turn off low-side transistorand to turn on high-side transistorto start a new switching cycle.

201 201 201 214 220 251 252 212 DC-DC converter circuitmay regulate the average output current IOUT by setting the peak threshold and the valley threshold at respective levels that may be equal or similar magnitudes above and below the desired average current. For example, DC-DC converter circuitmay receive an average-current setting IAVG from the application in which DC-DC converter circuitis implemented. Based on the average-current setting IAVG, peak-and-valley controllermay determine an initial peak-threshold setting PEAK_THR and an initial valley-threshold setting VALLEY_THR. The initial peak-threshold setting PEAK_THR and initial valley-threshold setting VALLEY_THR may be provided to peak-and-valley reference generator, which may in turn provide the peak threshold to peak comparatorand the valley threshold to valley comparator. As described in further detail below, the peak-threshold setting PEAK_THR and the valley-threshold setting VALLEY_THR may be further controlled according to inputs from timer circuitto provide a fast and accurate regulation of the average output current IOUT.

201 201 261 41 262 42 261 262 212 212 2 FIG.C 3 3 FIGS.A-D To improve the accuracy of the control loop for DC-DC converter circuit, DC-DC converter circuitmay utilize high-side comparatorto continuously compare the high-side current during the on-time of high-side transistorto an average-current threshold, as well as low-side comparatorto continuously compare the low-side current during the on-time of low-side transistorto the average-current threshold. High-side comparatormay be configured to compare the high-side current against an average-current threshold and to generate a high-side comparison signal CAHS accordingly. Similarly, low-side comparatormay be configured to compare the low-side current against the average-current threshold and to generate a low-side comparison signal CALS accordingly. The high-side comparison signal CAHS and the low-side comparison signal CALS may be provided to timer circuit. As described in further detail below with reference toand, timer circuitmay utilize the high-side comparison signal CAHS and the low-side comparison signal CALS to adjust the peak-threshold setting PEAK_THR and the valley-threshold setting VALLEY_THR, thereby maintaining accurate average current regulation.

2 FIG.A 2 FIG.B 212 270 270 270 212 41 42 41 42 In some embodiments, and as shown in, timer circuitmay also receive a buck signal CBCK from buck comparator. Buck comparatormay compare the voltage at the switching node VSW against a reference VREF, which may equal for example one-half of VIN. The buck signal CBCK from buck comparatormay thus provide an indication to timer circuitas to when high-side transistorand low-side transistortransition between respective on-states and off-states. As described below with reference to, other techniques may also be utilized suitable to detect the transitions of high-side transistorand low-side transistorbetween respective on-states and off-states.

2 FIG.B 2 FIG.B 2 FIG.A 2 FIG.B 2 FIG.A 200 271 272 270 271 272 212 212 41 42 illustrates a schematic diagram of LED lighting systemin accordance with embodiments of the present disclosure. As shown in, comparatorand comparatormay be utilized in place of the instance of buck comparatorillustrated in. Comparatormay compare the voltage at the switching node VSW against a reference VREF_HI, which may be for example ninety percent of VIN, and may generate a buck-high signal CBCK_H. Comparatormay compare the voltage at the switching node VSW against a reference VREF_LO, which may be for example ten percent of VIN, and may generate a buck-low signal CBCK_L. As shown in, CBCK_H and CBCK_L may also be provided to timer circuitin place of, or in addition to, the CBCK signal described above with reference toas an indication to timer circuitas to when high-side transistorand low-side transistortransition between respective on-states and off-states.

2 FIG.C 2 FIG.C 2 FIG.A 200 43 41 41 43 41 42 43 on off illustrates a waveform of an inductor current signal IL within LED lighting systemin accordance with embodiments of the present disclosure. The inductor current signal IL inmay represent the current through inductordescribed above with reference to. During the on-time (t) of high-side transistor, the rising high-side current flows through high-side transistorand inductor. And during the off-time (t) of high-side transistor, when the low-side transistor is in an on-state, the falling low-side current flows through low-side transistorand inductor. Thus, the rising portion of IL may represent the high-side current, and the falling portion of IL may represent the low-side current.

2 FIG.C As shown in, the time period during which the rising portion of IL (representative of the high-side current) is below the average-current threshold may be tabbed as time t1. And the time period during which the rising portion of IL (representative of the high-side current) is above the average-current threshold may be tabbed as time t2. Further, the time period during which the falling portion of IL (representative of the low-side current) is above the average-current threshold may be tabbed as time t3. And the time period during which the falling portion of IL (representative of the low-side current) is below the average-current threshold may be tabbed as time t4. Inventors of embodiments of the present disclosure have recognized that if the total time that IL is above the average-current threshold is equal to the total time that IL is below the average-current threshold, then the average output current IOUT may be equal to the average-current threshold. Accordingly, when the sum of t2 plus t3 is equal to the sum of t1 plus t4, the average output current IOUT may be equal to the average-current threshold set according to the desired average output current of the buck converter.

2 FIG.A 212 41 42 240 42 41 212 41 212 240 41 42 212 42 212 Returning to, timer circuitmay calculate t1, t2, t3, and t4 based on, for example, a clock signal CLK, the high-side comparison signal CAHS, the low-side comparison signal CALS, as well as the peak signal CP and the valley signal CV, which may respectively indicate when high-side transistorand low-side transistorare in respective on-states and off-states. As described above, the valley signal CV may be asserted to instruct PWM circuitto turn off low-side transistorand to turn on high-side transistor. Thus, the valley signal CV may indicate to timer circuitthat high-side transistoris in an on-state. In turn, timer circuitmay be configured to measure the first time period (t1) during which the high-side current is less than the average-current threshold, and to measure the second time period (t2) during which the high-side current is greater than the average-current threshold, based on the clock signal CLK and the high-side comparison signal CAHS. As also described above, the peak signal CP may be asserted to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. Thus, the peak signal CP may indicate to timer circuitthat low-side transistoris in an on-state. In turn, timer circuitmay be configured to measure the third time period (t3) during which the low-side current is greater than the average-current threshold, and to measure the fourth time period (t4) during which the low-side current is less than the average-current threshold, based on the clock signal CLK and the low-side comparison signal CALS.

212 212 212 214 214 220 251 252 Timer circuitmay also adjust the peak threshold and the valley threshold in response to the first time period (t1), second time period (t2), third time period (t3), and fourth time period (t4). Specifically, timer circuitmay be configured to adjust the peak threshold and the valley threshold based on a comparison of a sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3). For example, to the extent that the sum of t1 plus t4 differs from the sum of t2 plus t3, timer circuitmay provide a peak adjustment signal P_ADJ and/or a valley adjustment signal V_ADJ to peak-and-valley controller. In turn, peak-and-valley controllermay adjust one or both of the peak threshold setting PEAK_THR and the valley threshold setting VALLEY_THR provided to peak-and-valley reference generator, which provides the peak threshold and the valley threshold to peak comparatorand valley comparatorrespectively. The adjustment to the peak threshold and/or the valley threshold may be targeted to bring the sum of t1 plus t4 in alignment with the sum of t2 plus t3, such that the average output current of the buck converter may accurately track the desired average output current.

3 FIG.A 212 212 212 302 304 306 308 illustrates a schematic diagram of timer circuitin accordance with embodiments of the present disclosure. Timer circuitmay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, timer circuitmay include high-side counter, low-side counter, offset-compensation circuit, and time-comparison circuit.

302 302 302 240 42 41 240 41 42 41 302 302 3 FIG.A 2 FIG.A High-side countermay be implemented in any suitable fashion according to the operation described in the present disclosure. High-side countermay be configured to measure the first time period (t1) and the second time period (t2) based on the high-side comparison signal CAHS and the clock signal CLK. For example, as shown in, high-side countermay be configured to receive the valley signal CV, the peak signal CP, as well as the high-side comparison signal CAHS and the clock signal CLK. As described above with reference to, the valley signal CV may be asserted to instruct PWM circuitto turn off low-side transistorand to turn on high-side transistor. Further, the peak signal CP may be asserted to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. Thus, the time between the assertion of the valley signal CV and the subsequent assertion of the peak signal CP may correspond to the on-time of high-side transistor. To measure the first time period (t1), high-side countermay count the number of clock pulses when high-side comparison signal CAHS indicates that the high-side current is less than the average-current threshold in the time between the assertion of the valley signal CV and assertion of the peak signal CP. Likewise, to measure the second time period (t2), high-side countermay count the number of clock pulses when high-side comparison signal CAHS indicates that the high-side current is greater than the average-current threshold in the time between the assertion of the valley signal CV and the subsequent assertion of the peak signal CP.

304 304 304 240 41 42 240 42 41 42 41 304 304 3 FIG.A 2 FIG.A Low-side countermay be implemented in any suitable fashion according to the operation described in the present disclosure. Low-side countermay be configured to measure the third time period (t3) and the fourth time period (t4) based on the low-side comparison signal CALS and the clock signal CLK. For example, as shown in, low-side countermay be configured to receive the valley signal CV, the peak signal CP, as well as the low-side comparison signal CALS and the clock signal CLK. As described above with reference to, the peak signal CP may be asserted to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. Further, the valley signal CV may be asserted to instruct PWM circuitto turn off low-side transistorand to turn on high-side transistor. Thus, the time between the assertion of the peak signal CP and assertion of the valley signal CV may correspond to the on-time of low-side transistor(and the off-time of high-side transistor). To measure the third time period (t3), low-side countermay count the number of clock pulses when low-side comparison signal CALS indicates that the low-side current is greater than the average-current threshold in the time between the assertion of the peak signal CP and the subsequent assertion of the valley signal CV. Likewise, to measure the fourth time period (t4), low-side countermay count the number of clock pulses when low-side comparison signal CALS indicates that the low-side current is less than the average-current threshold in the time between the assertion of the peak signal CP and the subsequent assertion of the valley signal CV.

302 304 41 42 302 304 41 42 The clock frequency of the clock signal CLK utilized by high-side counterand low-side countermay be greater than the switching frequency of high-side transistorand low-side transistor, by a ratio of at least 10:1, for example. The higher the ratio of the clock frequency relative to the switching frequency, the higher the resolution of the adjustments that may be made to the peak threshold and the valley threshold according to the counts measured by high-side counterand low-side counter. The clock signal CLK may thus be set to a clock frequency higher than the switching frequency of high-side transistorand low-side transistorby a ratio of at least 10:1, 20:1, 40:1, 100:1, 1000:1, or more.

308 302 304 308 308 212 308 308 212 214 Time-comparison circuitmay receive the respective counts for t1, t2, t3, and t4 from high-side counterand low-side counter. The respective counts may represent the time values of the respective time periods. Time-comparison circuitmay then compare the sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3). Time-comparison circuitof timer circuitmay in turn adjust the peak threshold and the valley threshold in response to the first time period (t1), second time period (t2), third time period (t3), and fourth time period (t4). Specifically, time-comparison circuitmay be configured to adjust the peak threshold and the valley threshold based on the comparison of a sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3). For example, to the extent that the sum of t1 plus t4 differs from the sum of t2 plus t3, time-comparison circuitof timer circuitmay provide a peak adjustment signal P_ADJ and/or a valley adjustment signal V_ADJ to peak-and-valley controller. The adjustment to the peak threshold and/or the valley threshold may be targeted to bring the sum of t1 plus t4 in alignment with the sum of t2 plus t3, such that the average output current of the buck converter may accurately track the desired average output current.

2 FIG.A 240 41 42 240 42 41 41 302 304 41 42 41 42 308 42 41 308 As described above with reference to, the peak signal CP may be asserted instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. Further, the valley signal CV may be asserted to instruct PWM circuitturn off low-side transistorand to turn on high-side transistor. For both transitions, there may be a delay between when CP or CV are asserted and when high-side transistorand low-side transistor respectively turn on or off. The peak signal CP and the valley signal CV may nonetheless be utilized under certain conditions to indicate to high-side counterand low-side counterwhether high-side transistoror low-side transistorare in the on-state. For example, to the extent that a delay from the assertion of the peak signal CP to the time that high-side transistorturns off and low-side transistorturns on causes an over-counting for t2 and an under-counting for t3, the associated errors may cancel during the summation of t2 and t3 by time-comparison circuit. Likewise, to the extent that a delay form the assertion of the valley signal CV to the time that low-side transistorturns off and high-side transistorturns on causes an over-counting for t4 and an under-counting for t1, the associated errors may cancel out during the summation of t1 and t4 by time-comparison circuit.

302 304 41 251 212 212 302 302 240 42 41 240 302 In some embodiments, high-side counterand low-side countermay respectively use a high-side blanking period and a low-side blanking period when determining the counts for t1 and t3. For example, when high-side transistorturns on at the beginning of a switching cycle, the output of peak comparatormay be invalid for a period of time until the transistor is fully switched on and also until any transient noise spikes settle. To prevent errors during the turn-on time and/or due to transient noise spikes, timer circuitmay be configured to blank the high-side comparison signal CAHS during a high-side blanking period. For example, timer circuit, and high-side counterin particular, may utilize a high-side blanking period during which high-side counterignores the high-side comparison signal CAHS. The high-side blanking period may begin, for example, in response to the valley signal CV that instructs PWM circuitto turn off low-side transistorand turn on high-side transistor. The duration of the high-side blanking period may thus be set to account not only for the delay within PWM circuit, but also for the expected settling time of the transient switching noise. During the high-side blanking period, high-side countermay still count pulses of the clock signal CLK and assign those to the first time period t1 as the high-side current may be expected to be lower than the average-current threshold during the high-side blanking period.

41 42 252 42 212 212 304 304 240 41 42 240 304 Similarly, when high-side transistorturns off and low-side transistorturns on in the middle of a switching cycle, the output of valley comparatormay be invalid for a period of time until low-side transistoris fully switched on and any transient noise spikes settle. To prevent errors during the turn on time and/or due to transient noise spikes, timer circuitmay be configured to blank the low-side comparison signal during a low-side blanking period. For example, timer circuit, and low-side counterin particular, may utilize a low-side blanking period during which low-side counterignores the low-side comparison signal CALS. The low-side blanking period may begin, for example, in response to the peak signal CP that instructs PWM circuitto turn off high-side transistorand turn on low-side transistor. The duration of the low-side blanking period may be set to account not only for the delay within PWM circuit, but also for the expected settling time of the transient noise spikes. During the low-side blanking period, low-side countermay still count pulses of the clock signal CLK and assign those to the third time period t3 as the low-side current may be expected to be higher than the average-current threshold during the low-side blanking period.

3 FIG.B 3 FIG.B 3 FIG.A 200 41 41 on b-hs b-hs illustrates waveforms of signals within LED lighting systemin accordance with embodiments of the present disclosure. Specifically,illustrates inductor current IL during the on-time (t) of high-side transistor, as well as the clock signal CLK and the high-side comparison signal CAHS. As described above with reference to, high-side counter may use a high-side blanking period (t), during which the pulses of the clock signal CLK are counted and assigned to the first time period (t1). After the high-side blanking period (t), a sampling time (ton_sampling) may commence during which the clock pulses may be counted and assigned to either the first time period (t1) or the second time period (t2) depending on the state of the high-side comparison signal CAHS. Further clock pulses counted after the blanking period but before the high-side current crosses the average-current threshold may be added to the count for the first time period (t1). Subsequently, after the high-side current crosses the average-current threshold, the remainder of pulses of the clock signal CLK during the on-time of the high-side transistormay be counted and assigned to the second time period (t2).

261 261 262 261 262 3 FIG.B In some embodiments, noise at the input of high-side comparatormay cause a flickering of the high-side comparison signal CAHS when the high-side current is close to the average-current threshold. Nonetheless, the counting of the pulses of the clock signal CLK, and the assignment of those pulses to either the first time period (t1) or the second time period (t2) based on the high-side comparison signal, may provide a time-based averaging of error caused by noise at the input of high-side comparator. Although not illustrated in, noise at the input of low-side comparatormay cause a similar flickering of the low-side comparison signal CALS with the low-side current is close to the average current threshold. And in a similar manner as described directly above for high-side comparator, the counting of the pulses of the clock signal CLK, and the assignment of those pulses to either the third time period (t3) or the fourth time period (t4) based on the low-side comparison signal, may provide a time-based averaging of error caused by noise at the input of low-side comparator.

3 3 FIGS.C andD 3 FIG.C 2 FIG.A 200 43 41 41 43 41 42 43 on off illustrate waveforms of an inductor current signal IL within LED lighting systemin accordance with embodiments of the present disclosure. The inductor current signal IL inmay represent the current through inductordescribed above with reference to. During the on-time (t) of high-side transistor, the rising high-side current flows through high-side transistorand inductor. And during the off-time (t) of high-side transistor, when the low-side transistor is in an on-state, the falling low-side current flows through low-side transistorand inductor. Thus, the rising portion of IL may represent the high-side current, and the falling portion of IL may represent the low-side current.

41 42 41 212 212 308 on on off b-hs b-hs b-hs 3 FIG.C 3 FIG.C For the purposes of the present disclosure, the duty cycle of a transistor, such as high-side transistoror low-side transistor, may refer to the ratio of the on-time (t) to the sum of the on-time and the off-time (t+t) for a given on-and-off switching cycle of that transistor.illustrates the inductor current signal IL in a operating condition where the duty cycle of high-side transistoris very low. As shown in, when the duty cycle is very low, the high-side blanking period tmay be greater than the first time period (t1) during which the high-side current is less than the average-current threshold. Under such conditions, timer circuitmay ignore the counts for the first time period (t1) and the second time period (t2), and instead perform a comparison directly between the counts for the third time period (t3) and the fourth time period (t4). For example, timer circuit, including time-comparison circuitin particular, may be configured to adjust the peak threshold and the valley threshold in a similar manner as described above, but based on a comparison of the third time period (t3) and the fourth time period (t4) when the first time period (t1) is less than the high-side blanking period t. Under such conditions, the third time period (t3) and the fourth time period (t4) may represent a large majority of the overall switching cycle. Thus, comparison for the third time period (t3) and the fourth time period (t4) may provide for an accurate detection of the average current under such duty cycle conditions where the high-side blanking period tis greater than the first time period (t1).

3 FIG.D b-ls b-ls b-ls 212 212 308 As shown in, when the duty cycle is very high, the low-side blanking period tmay be greater than the third time period (t3) during which the low-side current is greater than the average-current threshold. Under such conditions, timer circuitmay ignore the counts for the third time period (t3) and the fourth time period (t4), and instead perform a comparison directly between the counts for the first time period (t1) and the second time period (t2). For example, timer circuit, including time-comparison circuitin particular, may be configured to adjust the peak threshold and the valley threshold in a similar manner as described above, but based on a comparison of the first time period (t1) and the second time period (t2) when the third time period (t3) is less than the low-side blanking period t. Under such conditions, the first time period (t1) and the second time period (t2) may represent a large majority of the overall switching cycle. Thus, comparison of the first time period (t1) and the second time period (t2) may provide for an accurate detection of the average current under such duty cycle conditions where the low-side blanking period (t) is greater than the third time period (t3).

3 FIG.C 3 FIG.D 2 FIG.A 41 42 212 302 304 270 270 41 42 When comparing the third time period (t3) against the fourth time period (t4) during low duty cycle conditions as described above with reference to, or when comparing the first time period (t1) against the second time period (t2) during high duty cycle conditions as described above with reference to, the measurements of the individual time periods may benefit from an accurate determination of when high-side transistorand low-side transistorturn on and off. Thus, in some embodiments, timer circuit, and in particular high-side counterand low-side counter, may utilize the CBCK signal from buck comparator. As described above with reference to, buck comparatormay compare the voltage at the switching node against a reference voltage, for example set to one-half of VIN, and may thus provide an accurate determination of when high-side transistorand low-side transistortransition between respective on-states and off-states opposite to each other.

212 302 304 271 272 271 272 41 42 212 41 42 2 FIG.B 2 FIG.B In other embodiments, timer circuit, and in particular high-side counterand low-side counter, may utilize the CBCK_H and CBCK_L signals from comparatorand comparatordescribed above with reference to. As described above with reference to, comparatormay compare the voltage at the switching node VSW against a reference VREF_HI, which may be for example ninety percent of VIN, and may generate a buck-high signal CBCK_H. Comparatormay compare the voltage at the switching node VSW against a reference VREF_LO, which may be for example ten percent of VIN, and may generate a buck-low signal CBCK_L. During a low-to-high or high-to-low transition of VSW due to the switching on and off of high-side transistorand low-side transistorrespectively, timer circuitmay receive the CBCK_L and CBCK_H signal and may tab the half-way point between the respective transitions of CBCK_L and CBCK_H as the time for when high-side transistorand low-side transistortransition between respective on-states and off-states opposite to each other.

4 FIG.A 4 FIG.A 201 220 240 251 252 illustrates a schematic diagram for portions of DC-DC converter circuitin accordance with embodiments of the present disclosure. Specifically,illustrates additional details of peak-and-valley reference generator, PWM circuit, peak comparator, and valley comparator.

2 FIG.A 4 FIG.A 220 214 220 251 220 252 As described above with reference to, peak-and-valley reference generatormay receive the peak-threshold setting PEAK_THR and the valley-threshold setting VALLEY_THR from peak-and-valley controller. As shown in, peak-and-valley reference generatormay provide the peak threshold to peak comparatorin the form of a reference current proportional to the peak threshold. Similarly, peak-and-valley reference generatormay provide the valley threshold to valley comparatorin the form of a reference current proportional to the valley threshold.

251 251 441 451 441 41 41 41 220 441 41 441 41 441 41 441 41 Peak comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, peak comparatormay be implemented with high-side sense transistorand voltage comparator. In some embodiments, high-side sense transistormay be configured as an NMOS sense FET for high-side transistor, with a drain coupled to the drain of high-side transistor, a gate coupled to the gate of high-side transistor, and a source coupled to peak-and-valley reference generatorto receive the sink current signal proportional to the peak threshold. High-side sense transistormay be configured to have a size that is smaller than high-side transistor. For example, high-side sense transistormay be configured to have a size that is smaller than high-side transistorby a ratio of 1:100, 1:1000, 1:2000, 1:4000, 1:10000, or greater. In some embodiments, high-side sense transistormay be implemented, for example, by one finger of a multiple-finger layout for high-side transistor. Accordingly, high-side sense transistormay match high-side transistorat the designed ratio.

220 441 41 441 41 451 441 41 41 41 441 451 4 FIG.A In some embodiments, the reference current provided by peak-and-valley reference generatormay have the same ratio relative to the peak threshold as the respective sizes for high-side sense transistorand high-side transistor. Accordingly, the drain-to-source voltage drop across high-side sense transistordue to the reference current may equal the voltage drop across high-side transistorat the peak threshold. Thus, as shown in, voltage comparatormay compare the voltages at the respective sources of high-side sense transistorand high-side transistorto generate the peak signal CP. For example, when the high-side current through high-side transistorexceeds the peak threshold, the voltage at the source of high-side transistormay cross below the voltage at the source of high-side sense transistor, and voltage comparatormay thus assert the peak signal CP.

252 252 442 452 442 42 442 42 42 220 442 42 442 42 442 42 442 42 4 FIG.A Valley comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, valley comparatormay be implemented with low-side sense transistorand voltage comparator. In some embodiments, low-side sense transistormay be configured as an NMOS sense FET for low-side transistor. For example, as shown in, low-side sense transistormay have a gate coupled to the gate of low-side transistor, a drain coupled to the drain of low-side transistor, and a source coupled to peak-and-valley reference generatorto receive the reference current proportional to the valley threshold. Low-side sense transistormay be configured to have a size that is smaller than low-side transistor. For example, low-side sense transistormay be configured to have a size that is smaller than low-side transistorby a ratio of 1:100, 1:1000, 1:2000, 1:4000, 1:10000, or greater. In some embodiments, low-side sense transistormay be implemented, for example, by one finger of a multiple-finger layout for low-side transistor. Accordingly, low-side sense transistormay match low-side transistorat the designed ratio.

220 442 42 442 42 452 442 42 42 42 442 452 4 FIG.A In some embodiments, the reference current provided by peak-and-valley reference generatormay have the same ratio relative to the valley threshold as the respective sizes for low-side sense transistorand low-side transistor. Accordingly, the drain-to-source voltage drop across low-side sense transistordue to the reference current may equal the voltage drop across low-side transistorat the peak threshold. Thus, as shown in, voltage comparatormay compare the voltages at the respective sources of low-side sense transistorand low-side transistorto generate the valley signal CV. For example, when the low-side current through low-side transistordrops below the valley threshold, the voltage at the source of low-side transistormay cross below the voltage at the source of low-side sense transistor, and voltage comparatormay thus assert the valley signal CV.

441 442 41 42 41 42 441 442 As described above, high-side sense transistorand low-side sense transistormay be implemented as sense FETs for the respective high-side transistorand low-side transistor. Accordingly, the current through high-side transistorand low-side transistormay be measured without adding an additional resistive element, such as a sense resistor, in the high-side or low-side current path. High-side sense transistorand low-side sense transistormay thus avoid efficiency loss and heat generation that would otherwise be associated with using sense resistors in the high-side and low-side current paths to detect the high-side and low-side currents.

441 442 441 442 41 42 41 441 Although the embodiments above describe high-side sense transistorand low-side sense transistoras NMOS sense FETs, high-side sense transistorand low-side sense transistormay be implemented with any suitable transistor type to match the respective high-side transistorand low-side transistor. For example, in embodiments where high-side transistoris implemented with a PMOS transistor, high-side sense transistormay likewise be implemented as a PMOS sense FET.

240 41 42 240 404 406 402 240 41 42 402 404 41 406 42 402 42 41 251 240 41 42 402 406 42 404 41 402 41 42 PWM circuitmay be implemented in any suitable fashion according to the operation described in the present disclosure. PWM circuit may commute control of high-side transistorand low-side transistor. In some embodiments, PWM circuitmay include high-side driver, low-side driver, as well as logic circuit. At the beginning of a switching cycle, PWM circuitmay drive high-side transistorin an on-state and low-side transistorin an off-state. For example, in response to an assertion of the valley signal CV, logic circuitmay control high-side driverto drive high-side transistorin an on-state, and may control low-side driverto drive low-side transistorin an off-state. Logic circuitmay include non-overlap logic to ensure that low-side transistoris turned off before high-side transistoris turned on to prevent any shoot-through current from VIN to ground GND. When the high-side current reaches and crosses above the peak threshold, peak comparatormay assert the peak signal CP to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. For example, in response to an assertion of the peak signal CP, logic circuitmay control low-side driverto drive low-side transistorin an on-state, and may control high-side driverto drive high-side transistorin an off-state. Logic circuitmay include non-overlap logic to ensure that high-side transistoris turned off before low-side transistoris turned on to prevent any shoot-through current from VIN to ground GND.

240 402 240 251 252 240 402 240 41 42 240 41 42 240 42 41 240 251 252 240 41 42 4 FIG.A In some embodiments, PWM circuit, and in particular the logic circuitof PWM circuit, may include a digital filter configured to digitally filter the peak signal CP from peak comparatorand to digitally filter the valley signal CV from valley comparator. For example, as shown in, PWM circuitand logic circuitin particular may receive a clock signal CLK. The digital filter may require that the peak signal CP be asserted for two, three, four, or any suitable N number of clock cycles before PWM circuitturns off high-side transistorand turns on low-side transistor. For example, the digital filter may require that the peak signal CP be asserted for two, three, four, or any suitable N number of consecutive clock cycles before PWM circuitturns off high-side transistorand turns on low-side transistor. Similarly, the digital filter may require that the valley signal CV be asserted for two, three, four, or any suitable N number of clock cycles before PWM circuitturns off low-side transistorand turns on high-side transistor. By filtering the peak signal CP and/or the valley signal CV, PWM circuitmay prevent noise incurred at the inputs of peak comparatorand valley comparatorfrom improperly triggering PWM circuitto change the respective on-state or off-state of high-side transistorand low-side transistorbefore the peak threshold or valley threshold have been reached. Such filtering may cause the high-side current to overshoot above the set peak threshold, and similarly cause the low-side current to undershoot below the set valley threshold. Nonetheless, such overshoot and/or undershoot may be fully compensated by the average current regulation loop as a whole and may thus have either no impact, or only a minimal impact, on the required average output current.

4 FIG.B 4 FIG.B 4 FIG.B 2 FIG.A 402 240 43 41 41 43 on illustrates waveforms of signals within an LED lighting system in accordance with embodiments of the present disclosure. Specifically,illustrates how logic circuitwithin PWM circuitmay digitally filter the peak signal CP, and similarly the valley signal CV. The inductor current signal IL inmay represent the current through inductordescribed above with reference to. During the on-time (t) of high-side transistor, the rising high-side current flows through high-side transistorand inductor. Thus, the rising portion of IL may represent the high-side current.

4 FIG.B 4 FIG.B 4 FIG.B 4 FIG.B 402 402 As shown in, logic circuitmay generate a peak-signal count CP_COUNT in response to the peak signal CP and the clock signal CLK. The peak-signal count CP_COUNT may increase by one for every clock pulse, triggered by either the rising edge and/or the falling edge of the clock signal CLK, during which the peak signal CP is asserted at a logic-high value. The peak-signal count CP_COUNT may also be reset to zero if the peak signal CP is unasserted at a logic-low value. In turn, the filtered peak signal CP_FILT may be asserted only when the peak-signal count CP_COUNT reaches a set value, of for example, two, three, four, or any suitable number N. Accordingly, as shown in, disturbances in the peak signal CP prior to the inductor current IL reaching the peak threshold may be filtered out. Although not expressly shown in, logic circuitmay also digitally filter the valley signal CV in the same manner as described above and as shown in.

4 FIG.C 4 FIG.A 4 FIG.C 4 FIG.A 4 FIG.C 4 FIG.A 201 240 251 221 253 220 252 illustrates a schematic diagram for portions of DC-DC converter circuitin accordance with embodiments of the present disclosure. Similar to,illustrates additional details of PWM circuitand peak comparator, both of which may operate in a similar manner as described above with reference to. In addition,illustrates additional details of peak-and-valley reference generatorand valley comparator, which may serve as alternative embodiments for peak-and-valley reference generatorand valley comparatordescribed above with reference to.

200 41 42 221 253 In some applications of the LED lighting system, the magnitude of the ripple of the inductor current IL may exceed the average output current. In such applications, the inductor current IL may reverse and go negative during a portion of the off-time of high-side transistorwhen low-side transistoris in an on-state. To accommodate such applications, peak-and-valley reference generatorand valley comparatormay be configured to compare the valley threshold against a negative current.

4 FIG.C 253 492 482 472 482 42 1 221 492 42 2 221 482 492 42 472 482 492 As shown in, valley comparatormay include sense transistor, sense transistor, and voltage comparator. Sense transistormay be an NMOS transistor with a gate and a drain coupled to the respective gate and drain of low-side transistor, and a source coupled to receive a reference current IREFfrom peak-and-valley reference generator. Sense transistormay be an NMOS transistor with a gate coupled to the gate of low-side transistor, a drain coupled to ground GND, and a source coupled to receive a reference current IREFfrom peak-and-valley reference generator. Sense transistorand sense transistormay be configured to have the same size as each other, and to both have a size that is smaller than low-side transistorby a ratio of 1:100, 1:1000, 1:2000, 1:4000, 1:10000, or greater. Voltage comparatormay have a first input coupled to the source of sense transistorand a second input coupled to the source of sense transistor.

1 2 2 492 482 492 472 482 1 42 42 42 492 482 472 To sense positive currents, IREFmay be set to a value proportional to the valley threshold and IREFmay be set to zero. With IREFat zero, the voltage drop across the drain to source of sense transistormay equal zero. Thus, by comparing the voltages at the respective sources of sense transistorand sense transistor, voltage comparatormay effectively compare the voltage drops across sense transistordue to IREFagainst the voltage drop across low-side transistordue to the low-side current. For example, when the low-side current through low-side transistordrops below the valley threshold, the voltage at the source of low-side transistor(and at the source of sense transistor) may cross below the voltage at the source of sense transistor, and voltage comparatormay thus assert the valley signal CV.

1 2 1 482 482 492 472 492 2 42 42 42 42 482 492 472 To sense reverse currents, IREFmay be set to zero and the IREFmay be set to a value proportional to the valley threshold. With IREFat zero, the voltage drop across sense transistormay equal zero. Thus, by comparing the voltages at the respective sources of sense transistorand sense transistor, voltage comparatormay effectively compare the voltage drops across sense transistordue to IREFagainst the voltage drop across low-side transistordue to the negative low-side current flowing from drain to source to low-side transistor. For example, when the low-side current through low-side transistordrops below the valley threshold, the voltage at the drain of low-side transistor(and thus at the source of sense transistor) may cross above the voltage at the source of sense transistor, and voltage comparatormay thus assert the valley signal CV.

5 FIG.A 5 FIG.A 201 230 261 262 illustrates a schematic diagram for portions of DC-DC converter circuitin accordance with embodiments of the present disclosure. Specifically,illustrates additional details of average-current reference generator, high-side comparator, and low-side comparator.

2 FIG.A 8 FIG. 230 215 215 261 262 201 As shown in, average-current reference generatormay receive a compensated average-current threshold IAVG_COMP from curvature compensation controller. The curvature compensation applied to the average current setting IAVG by curvature compensation controlleris described in further detail below with reference to. But for the purposes of describing the operation of high-side comparatorand low-side comparator, the compensated average-current threshold IAVG_COMP may represent a compensated version of the average current setting IA VG provided to DC-DC converter circuit.

5 FIG.A 230 261 230 262 As shown in, average-current reference generatormay provide the average current threshold to high-side comparatorin the form of a high-side average current reference IAVG_HS proportional to the average current threshold. Similarly, average-current reference generatormay provide the average current threshold to low-side comparatorin the form of a low-side average current reference IAVG_LS proportional to the average current threshold.

261 261 541 551 541 41 41 41 230 541 41 541 41 541 41 541 41 High-side comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, high-side comparatormay be implemented with high-side sense transistorand voltage comparator. In some embodiments, high-side sense transistormay be configured as an NMOS sense FET for high-side transistor, with a drain coupled to the drain of high-side transistor, a gate coupled to the gate of high-side transistor, and a source coupled to average-current reference generatorto receive a sink current signal in the form of high-side average current reference IAVG_HS. High-side sense transistormay be configured to have a size that is smaller than high-side transistor. For example, high-side sense transistormay be configured to have a size that is smaller than high-side transistorby a ratio of 1:100, 1:1000, 1:2000, 1:4000, 1:10000, or greater. In some embodiments, high-side sense transistormay be implemented, for example, by one finger of a multiple-finger layout for high-side transistor. Accordingly, high-side sense transistormay match high-side transistorat the designed ratio.

230 541 41 541 41 551 541 41 41 41 541 551 41 41 541 551 5 FIG.A In some embodiments, the high-side average current reference IAVG_HS provided by average-current reference generatormay have the same ratio relative to the average-current threshold as the respective sizes for high-side sense transistorand high-side transistor. Accordingly, the drain-to-source voltage drop across high-side sense transistordue to the high-side average current reference IAVG_HS may equal the voltage drop across high-side transistorat the average-current threshold. Thus, as shown in, voltage comparatormay compare the voltages at the respective sources of high-side sense transistorand high-side transistorto generate the high-side comparison signal CAHS. For example, when the high-side current through high-side transistoris less than the average-current threshold, the voltage at the source of high-side transistormay be greater than the voltage at the source of high-side sense transistor, and voltage comparatormay output a logic-low value for the high-side comparison signal CAHS. Conversely, when the high-side current through high-side transistorexceeds the average-current threshold, the voltage at the source of high-side transistormay cross below the voltage at the source of high-side sense transistor, and voltage comparatormay output a logic-high value for the high-side comparison signal CAHS.

262 262 542 552 542 42 542 42 42 230 542 42 542 42 542 42 542 42 5 FIG.A Low-side comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, low-side comparatormay be implemented with low-side sense transistorand voltage comparator. In some embodiments, low-side sense transistormay be configured as an NMOS sense FET for low-side transistor. For example, as shown in, low-side sense transistormay have a gate coupled to the gate of low-side transistor, a drain coupled to the drain of low-side transistor, and a source coupled to average-current reference generatorto receive the low-side average current reference IAVG_LS. Low-side sense transistormay be configured to have a size that is smaller than low-side transistor. For example, low-side sense transistormay be configured to have a size that is smaller than low-side transistorby a ratio of 1:100, 1:1000, 1:2000, 1:4000, 1:10000, or greater. In some embodiments, low-side sense transistormay be implemented, for example, by one finger of a multiple-finger layout for low-side transistor. Accordingly, low-side sense transistormay match low-side transistorat the designed ratio.

230 542 42 542 42 552 542 42 42 42 542 452 42 42 542 452 5 FIG.A In some embodiments, the low-side average current reference IAVG_LS provided by average-current reference generatormay have the same ratio relative to the average-current threshold as the respective sizes for low-side sense transistorand low-side transistor. Accordingly, the drain-to-source voltage drop across low-side sense transistordue to the low-side average current reference IAVG_LS may equal the voltage drop across low-side transistorat the average-current threshold. Thus, as shown in, voltage comparatormay compare the voltages at the respective sources of low-side sense transistorand low-side transistorto generate the low-side comparison signal CALS. For example, when the low-side current through low-side transistoris above the average-current threshold, the voltage at the source of low-side transistormay be greater than the voltage at the source of low-side sense transistor, and voltage comparatormay output a logic-high value for the low-side comparison signal CALS. Conversely, when the low-side current through low-side transistordrops below the average-current threshold, the voltage at the source of low-side transistormay cross below the voltage at the source of low-side sense transistor, and voltage comparatormay output a logic-low value for the low-side comparison signal CALS.

541 542 41 42 41 42 41 42 As described above, high-side sense transistorand low-side sense transistormay be implemented as sense FETs for the respective high-side transistorand low-side transistor. Accordingly, the current through high-side transistorand low-side transistormay be measured without adding an additional resistive element, such as a sense resistor, in the high-side or low-side current path. Sensing the respective high-side current and low-side current directly on high-side transistorand low-side transistormay thus avoid efficiency loss and heat generation that would otherwise be associated with using sense resistors in the high-side and low-side current paths to detect the high-side and low-side currents.

541 542 541 542 41 42 41 541 Although the embodiments above describe high-side sense transistorand low-side sense transistoras NMOS sense FETs, high-side sense transistorand low-side sense transistormay be implemented with any suitable transistor type to match the respective high-side transistorand low-side transistor. For example, in embodiments where high-side transistoris implemented with a PMOS transistor, high-side sense transistormay likewise be implemented as a PMOS sense FET.

261 262 261 262 551 261 552 262 261 262 261 262 551 261 552 262 2 FIG.A 5 FIG.A 2 FIG.A 5 FIG.A 6 6 FIGS.A-B 7 7 FIGS.A-B In some embodiments, high-side comparatormay be a chopper-stabilized high-side comparator. Likewise, low-side comparatormay be a chopper-stabilized low-side comparator. As shown inand, high-side comparatorand low-side comparatormay receive a chopper signal CHP to control chopper circuits included within voltage comparatorof high-side comparatorand within voltage comparatorof low-side comparator, respectively. In some embodiments, such as shown inand, high-side comparatorand low-side comparatormay receive the same common chopper signal such as chopper signal CHP. In other embodiments, high-side comparatorand low-side comparatormay receive separate high-side and low-side chopper signals. As described in further detail below with reference to, a chopper circuit may be configured to alternate, during a first phase and a second phase, an input polarity of the input stage as well as an output polarity of an output stage internal to the voltage comparatorwithin high-side comparator. And as similarly described in further detail below with reference to, a chopper circuit may be configured to alternate, during a first phase and a second phase, an input polarity of the input stage as well as an output polarity of an output stage internal to the voltage comparatorwithin low-side comparator.

551 261 552 262 212 551 261 552 262 Thus, any input offset present in the voltage comparatorof high-side comparatoror in the voltage comparatorof low-side comparator, due to semiconductor process variation for example, may have an equal or substantially equal magnitude and opposite polarity during the first and second phases. For example, if a −10 mV offset is present during the first phase when the chopper signal CHP is in a first state, a +10 mV offset may be present during the second phase when the chopper signal CHP is in a second state. And as described below, timer circuitmay monitor the high-side comparison signal CAHS and the low-side comparison signal CALS during the first phase and the second phase, and may provide a coarse offset compensation for one or both of the voltage comparatorwithin high-side comparatoror the voltage comparatorwithin low-side comparator.

5 FIG.B 5 FIG.B 2 FIG.A 200 43 41 41 43 41 42 43 on off illustrates waveforms of signals within LED lighting systemin accordance with embodiments of the present disclosure. The inductor current signal IL inmay represent the current through inductordescribed above with reference to. During the on-time (t) of high-side transistor, the rising high-side current flows through high-side transistorand inductor. And during the off-time (t) of high-side transistor, when the low-side transistor is in an on-state, the falling low-side current flows through low-side transistorand inductor. Thus, the rising portion of IL may represent the high-side current, and the falling portion of IL may represent the low-side current.

5 FIG.B As shown in, the time period during which the rising portion of IL (representative of the high-side current) is below the average-current threshold may be tabbed as time t1. And the time period during which the rising portion of IL (representative of the high-side current) is above the average-current threshold may be tabbed as time t2. Further, the time period during which the falling portion of IL (representative of the low-side current) is above the average-current threshold may be tabbed as time t3. And the time period during which the falling portion of IL (representative of the low-side current) is below the average-current threshold may be tabbed as time t4.

5 FIG.B 41 42 551 261 262 552 262 41 42 41 42 As also shown in, the chopper signal CHP may have a first phase and a second phase. For example, the chopper signal CHP may be at a logic-high level during the first phase and at a logic-low level during the second phase. The chopper signal CHP, including the first phase and the second phase, may have a phase frequency aligned to the switching frequency of high-side transistorand low-side transistor. For example, the chopper signal CHP controlling the phases of high-side comparator (in particular the voltage comparatorwithin high-side comparator) and low-side comparator(in particular the voltage comparatorwithin low-side comparator) may have a frequency that is half of the switching frequency of high-side transistorand low-side transistor. Accordingly, the first phase and the second phase may each align with a full switching cycle of high-side transistorand low-side transistor.

261 302 302 302 261 261 3 FIG.A High-side comparatormay compare the high-side current against the average-current threshold. And as described above with reference to, high-side countermay be configured to measure the first time period (t1) and the second time period (t2) based on the high-side comparison signal CAHS and the clock signal CLK. To measure the first time period (t1), high-side countermay count the number of clock pulses when the high-side comparison signal CAHS indicates that the high-side current is less than the average-current threshold. Likewise, to measure the second time period (t2), high-side countermay count the number of clock pulses when high-side comparison signal CAHS indicates that the high-side current is greater than the average-current threshold. An input offset present in high-side comparatormay induce an error around the transition point for the high-side comparison signal CAHS. Thus, the input offset present in high-side comparatormay induce errors in the respective counts for the first time period (t1) and the second time period (t2) proportional to the input offset. As described above, the input offset may have an equal or substantially equal magnitude and opposite polarity during the first and second phases of the chopper signal CHP. Thus, if a −10 mV offset is present during the first phase when the chopper signal CHP is in a first state, a +10 mV offset may be present during the second phase when the chopper signal CHP is in a second state. Accordingly, the error for the respective counts for the first time period (t1) and the second time period (t2) during the second phase may be of equal magnitude and opposite polarity as compared to the corresponding errors during the first phase.

262 304 304 304 262 262 3 FIG.A Low-side comparatormay compare the low-side current against the average-current threshold. And as described above with reference to, low-side countermay be configured to measure the third time period (t3) and the fourth time period (t4) based on the low-side comparison signal CALS and the clock signal CLK. To measure the third time period (t3), low-side countermay count the number of clock pulses when low-side comparison signal CALS indicates that the low-side current is greater than the average-current threshold. Likewise, to measure the fourth time period (t4), low-side countermay count the number of clock pulses when the low-side comparison signal CALS indicates that the low-side current is less than the average-current threshold. An input offset present in low-side comparatormay induce an error around the transition point for the low-side comparison signal CALS. Thus, the input offset present in low-side comparatormay induce errors in the respective counts for the third time period (t3) and the fourth time period (t4) proportional to the input offset. As described above, the input offset may have an equal or substantially equal magnitude and opposite polarity during the first and second phases of the chopper signal CHP. Thus, if a −10 mV offset is present during the first phase when the chopper signal CHP is in a first state, a +10 mV offset may be present during the second phase when the chopper signal CHP is in a second state. Accordingly, the error for the respective counts for the third time period (t3) and the fourth time period (t4) during the second phase may be of equal magnitude and opposite polarity as compared to the corresponding errors during the first phase.

In some embodiments, the clock signal CLK may have a clock frequency that is higher than a phase frequency of the first phase and the second phase. For example, to provide higher resolution for the first count and the second count for each of the first time period (t1), the second time period (t2), the third time period (t3), and the fourth time period (t4), the clock signal CLK may have a clock frequency that is higher than a phase frequency of the first phase and the second phase by a ratio of a least 20:1, 40:1, 100:1, 1000:1, 2000:1, or more.

3 FIG.A 306 302 304 306 302 304 Referring back to, offset-compensation circuitmay be coupled to high-side counterand low-side counter. For example, offset-compensation circuitmay be coupled to receive from high-side counterand low-side countera first count corresponding to the first phase for each of the first time period (t1), second time period (t2), third time period (t3), and fourth time period (t4), as well as a second count corresponding to the second phase for each of the first time period (t1), second time period (t2), third time period (t3), and fourth time period (t4).

261 261 306 261 261 306 306 261 The difference between the first count during the first phase and the second count during the second phase for the first time period (t1) may be proportional to the input offset for high-side comparator. Thus, to compensate for the input offset of high-side comparator, offset-compensation circuitmay generate a high-side offset-compensation signal HS_OFFSET that may adjust the input offset of high-side comparatorat a level that is proportional to the difference between the first count and the second count of the first time period (t1). The difference between the first count during the first phase and the second count during the second phase for the second time period (t2) may likewise be proportional to the input offset for high-side comparator. Thus, offset-compensation circuitmay also use the difference between the first count and the second count for the second time period (t2) to generate the high-side offset-compensation signal HS_OFFSET. For example, offset-compensation circuitmay generate the high-side offset-compensation signal HS_OFFSET that may adjust the input offset of high-side comparatorat a level that is proportional to the difference between the first count and the second count of the second time period (t2).

262 262 306 262 262 306 306 262 The difference between the first count during the first phase and the second count during the second phase for the third time period (t3) may be proportional to the input offset for low-side comparator. Thus, to compensate for the input offset of low-side comparator, offset-compensation circuitmay generate a low-side offset-compensation signal LS_OFFSET that may adjust the input offset of low-side comparatorat a level that is proportional to the difference between the first count and the second count of the third time period (t3). The difference between the first count during the first phase and the second count during the second phase for the fourth time period (t4) may likewise be proportional to the input offset for low-side comparator. Thus, offset-compensation circuitmay also use the difference between the first count and the second count for the fourth time period (t4) to generate the low-side offset-compensation signal LS_OFFSET. For example, offset-compensation circuitmay generate the low-side offset-compensation signal LS_OFFSET that may adjust the input offset of low-side comparatorat a level that is proportional to the difference between the first count and the second count of the fourth time period (t4).

212 308 212 308 In some embodiments, timer circuitmay be configured to adjust the peak threshold and the valley threshold in response to a first average of the first time period (t1) across two or more chopper phases, a second average of the second time period (t2) across the two or more chopper phases, a third average of the third time period (t3) across the two or more chopper phases, and/or a fourth average of the fourth time period (t4) across the two or more chopper phases. For example, the time-comparison circuitwithin timer circuitmay account for multiple measurements of the first time period (t1), the second time period (t2), the third time period (t3), and/or the fourth time period (t4) across the first and second chopper phases, when generating the P_ADJ and V_ADJ signals to adjust the peak threshold and the valley threshold as described above. Time-comparison circuitmay average first and second measurements for each of the first time period (t1), the second time period (t2), the third time period (t3), and the fourth time period (t4) across the first and second chopper phases, when determining any adjustments to the peak threshold and the valley threshold. By averaging the measurements for each of t1, t2, t3, and t4 across two or more chopper phases, the chopper operation may provide a further fine offset cancellation of any offset remaining after application of the coarse offset compensation provided by the high-side offset-compensation signal HS_OFFSET and the low-side offset-compensation signal LS_OFFSET.

261 262 261 262 Thus, in some embodiments, continued operation of the chopper circuit within high-side comparatorand the chopper circuit within low-side comparatormay provide a further fine offset cancellation in addition to the coarse offset compensation provided by the high-side offset-compensation signal HS_OFFSET and the low-side offset-compensation signal LS_OFFSET. Given the initial coarse offset compensation provided by HS_OFFSET and LS_OFFSET, noise generated by the continued chopper operation may be reduced as the difference between the first phase and the second phase may be reduced by the coarse offset compensation. Nonetheless, in some embodiments, to reduce or eliminate noise associated with continued chopper operation, high-side comparatorand/or low-side comparatormay be configured to disable chopping after the initial setting of the high-side offset-compensation signal HS_OFFSET and the low-side offset-compensation signal LS_OFFSET.

6 FIG.A 6 FIG.A 551 551 551 630 640 650 602 612 622 illustrates a schematic diagram of voltage comparatorin accordance with embodiments of the present disclosure. Voltage comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, voltage comparatormay include input stage, output stage, high-side offset controller, and a chopper circuit collectively formed by pass gates,, and.

630 631 632 631 632 631 635 632 636 633 631 632 650 630 633 635 636 630 637 631 638 632 637 638 637 638 637 638 631 632 631 632 631 632 6 FIG.A Input stagemay include first transistorand second transistorconfigured together as a differential pair. In some embodiments, first transistorand second transistormay be NMOS transistors. As shown in, the source of first transistormay be coupled to a first current source, and the source of second transistormay be coupled to a second current source. Resistormay be coupled between the respective sources of first transistorand second transistor. Accordingly, and as described in further detail below with reference to high-side offset controller, input offset compensation may be injected into input stagebased on the resistance value of resistorand the difference between the bias currents provided by first current sourceand second current source. Input stagemay further include a current sourcecoupled to the drain of first transistorand current sourcecoupled to the drain of second transistor. In some embodiments, the bias currents provided by current sourceand current sourcemay match each other. For example, in some embodiments, current sourceand current sourcemay be implemented by matching output branches of a current mirror such that the bias current provided by current sourcematches the bias current provided by current source. With first transistorand second transistorbeing configured together as a differential pair, first transistorand second transistormay amplify any difference in voltage signals received at the respective gates of first transistorand second transistor.

640 630 640 641 642 641 642 641 622 631 632 622 640 641 630 641 6 FIG.A Output stagemay be coupled to input stageand may be configured to generate the high-side comparison signal CAHS. Output stagemay include output transistorand current source. In some embodiments, output transistor may be a PMOS transistor. As shown in, output transistormay have a source coupled to a supply voltage and a drain coupled to current source. The gate of output transistormay be coupled, via pass gate, to the drain of either first transistoror second transistordepending on the state of pass gate. Output stage, and output transistorin particular, may thus further amplify the output of input stage. In some embodiments, output transistormay generate the high-side comparison signal CAHS at its drain.

630 640 551 602 612 622 630 640 In addition to input stageand output stage, voltage comparatormay include a chopper circuit collectively formed by pass gates,, and. The chopper circuit may be configured to alternate an input polarity of input stageduring a first phase and a second phase of the chopper signal CHP. The chopper circuit may also be configured to alternate an output polarity of output stageduring the first phase and the second phase of the chopper signal CHP.

6 FIG.A 601 602 612 622 As shown in, invertermay invert the chopper signal CHP to create an additional inverse chopper signal CHP_BAR. Pass gates,, andmay utilize CHP and CHP_BAR to selectively pass a signal from one of two pass-gate inputs to the pass-gate output.

602 604 605 607 602 603 606 607 612 602 612 614 615 617 612 613 616 617 622 602 612 622 624 625 627 622 623 626 627 602 612 622 602 612 622 602 612 622 6 FIG.A 6 FIG.A 6 FIG.A Pass gatemay include a first pass transistorhaving a drain coupled to a first pass-gate input, a gate driven by the chopper signal CHP, and a source coupled to the pass-gate output. Pass gatemay also include a second pass transistorhaving a drain coupled to a second pass-gate input, a gate driven by the inverse chopper signal CHP_BAR, and a source coupled to the pass-gate output. Pass gatemay be configured in a similar manner as pass gate. For example, pass gatemay include a first pass transistorhaving a drain coupled to a first pass-gate input, a gate driven by the chopper signal CHP, and a source coupled to the pass-gate output. Pass gatemay also include a second pass transistorhaving a drain coupled to a second pass-gate input, a gate driven by the inverse chopper signal CHP_BAR, and a source coupled to the pass-gate output. Pass gatemay also be configured in a similar manner as pass gateand pass gate. For example, pass gatemay include a first pass transistorhaving a drain coupled to a first pass-gate input, a gate driven by the chopper signal CHP, and a source coupled to the pass-gate output. Pass gatemay also include a second pass transistorhaving a drain coupled to a second pass-gate input, a gate driven by the inverse chopper signal CHP_BAR, and a source coupled to the pass-gate output. Although the individual pass transistors of pass gate, pass gate, and pass gateare illustrated inas being implemented by NMOS transistors, the individual pass transistors of pass gates,, andmay alternatively be implemented by, for example, PMOS transistors. In such alternative embodiments utilizing PMOS transistors instead of NMOS transistors, the individual pass transistors of pass gates,, andmay be driven by the opposite signal from among CHP and CHP_BAR than is shown into achieve the same functionality as the NMOS-based pass gates shown in.

6 FIG.A 602 631 551 631 551 612 632 551 632 551 602 612 630 As shown in, pass gatemay couple the gate of first transistorto the negative input terminal VIN− of voltage comparatorduring a first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of first transistorto the positive input terminal VIN+ of voltage comparatorduring a second phase when the inverse chopper signal CHP_BAR is in a logic-high state. In a similar manner, pass gatemay couple the gate of second transistorto the positive input terminal VIN+ of voltage comparatorduring the first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of second transistorto the negative input terminal VIN− of voltage comparatorduring the second phase when the inverse chopper signal CHP_BAR is in a logic-high state. Passs gateand pass gatemay thus alternate the input polarity of input stageduring the first phase and the second phase.

6 FIG.A 630 640 640 622 641 632 641 631 622 640 As also shown in, the chopper circuit may be further configured to alternate the coupling between input stageand output stageduring the first phase and the second phase to alternate an output polarity of output stageduring the first phase and the second phase. For example, pass gatemay couple the gate of output transistorto the drain of second transistorduring a first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of output transistorto the drain of first transistorduring a second phase when the inverse chopper signal CHP_BAR is in a logic-high state. Pass gatemay thus alternate the output polarity of output stageduring the first phase and the second phase.

650 551 650 635 636 631 632 630 635 636 631 632 650 635 636 635 636 633 635 636 630 650 551 306 High-side offset controllermay be configured to adjust an input offset of voltage comparatorbased on HS_OFFSET. For example, high-side offset controllermay be configured to control the first current sourceand second current sourcerespectively coupled to bias first transistorand second transistorof input stage. In some embodiments, first current sourceand second current sourcemay be configured to match when in a default state and to thereby provide equal bias currents to first transistorand second transistor. Based on HS_OFFSET, high-side offset controllermay then adjust first current sourceand/or second current sourceto cause the respective currents provided by first current sourceand/or second current sourceto be different from each other. The resistance of resistormultiplied by half the difference between the bias currents respectively provided by first current sourceand second current sourcewill inject an input offset into input stage. Accordingly, as described above, high-side offset controllermay adjust the input offset of voltage comparatorbased on the HS_OFFET, to compensate for an offset detected by offset-compensation circuitas described above.

6 FIG.A 650 635 636 551 551 650 633 631 632 650 637 638 551 637 638 637 638 650 631 632 Although the embodiment shown inutilizes high-side offset controllerto control first current sourceand second current sourceto adjust the input offset of voltage comparator, any other scheme suitable to adjust the input offset of voltage comparatormay be utilized and controlled for example by high-side offset controller. For example, in some embodiments, resistormay be omitted and the sources of first transistorand second transistormay be coupled directly together and to a single current source. In such embodiments, the input offset may be adjusted by other suitable techniques. For example, high-side offset controllermay be configured to vary the respective bias currents of current sourceand current sourceto adjust the input offset of voltage comparator. In such example embodiments, current sourceand current sourcemay include matching output branches of a current mirror as described above, in addition to small adjustable current sources and/or current-mirror outputs configured to controllably adjust the total bias currents provided by current sourceand current source. As another example, high-side offset controllermay be configured to adjust a voltage drop directly at the gate of first transistorand/or at the gate of second transistor.

551 630 640 630 640 630 640 6 FIG.A Further, although the embodiment of voltage comparatorshown inincludes input stageand output stage, other embodiments may include other circuit topologies for input stageand output stage. Moreover, other embodiments may include additional intermediate stages between input stageand output stage. In such other embodiments, the output stage may be considered to be coupled to the input stage via the further intermediate stages.

6 FIG.B 5 FIG.A 6 FIG.A 6 FIG.B 6 FIG.A 561 561 551 561 561 551 630 650 601 602 612 630 650 601 602 612 551 illustrates a schematic diagram of voltage comparatorin accordance with embodiments of the present disclosure. Voltage comparatormay represent an alternate embodiment of voltage comparatordescribed above with reference toand. Voltage comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, voltage comparatormay include certain components similar to voltage comparatordescribed above with reference to, including input stage, high-side offset controller, inverter, pass gate, and pass gate. Each of input stage, high-side offset controller, inverter, pass gate, and pass gatemay operate in a similar manner as described above for voltage comparator.

561 645 640 551 645 641 642 641 642 645 640 551 642 641 630 641 630 632 630 645 561 6 FIG.B Voltage comparatormay also include output stage. Similar to output stageof voltage comparator, output stagemay include output transistorand current source. Output transistorand current sourcemay operate in a similar manner within output stageas described above for output stageof voltage comparator. For example, current sourcemay bias output transistor, which may further amplify the output of input stage. As shown in, the gate of output transistormay be coupled to the output of input stageat the drain of second transistor. Thus, the coupling between input stageand output stagein voltage comparatormay remain the same across the first phase and the second phase of the chopper operation.

645 646 645 641 646 646 646 645 646 646 646 645 646 646 645 602 612 646 Output stagemay utilize logic gateto logically alternate the output polarity of output stageduring the first phase and the second phase of the chopper operation. For example, the drain of output transistormay be coupled to a first logic input of logic gate. One of the chopper signal CHP or the inverse chopper signal CHP_BAR may be coupled to a second logic input of logic gate. Logic gatemay thus utilize a logic operation to alternate the output polarity of output stageacross the first phase and the second phase of the chopper operation. For example, in some embodiments where the chopper signal CHP is coupled to the second logic input of logic gate, logic gatemay be implemented as an XNOR logic gate to generate the high-side comparison signal CAHS. In other embodiments, logic gatemay be implemented as other types of logic gates suitable to alternate the output polarity of output stagedepending on the polarities of the signals coupled to the first logic input and the second logic input of logic gate. Further, for the purposes of the present disclosure, logic gatemay be considered part of output stageand/or part of the chopper circuitry collectively formed by pass gateand pass gate. Accordingly, the chopper circuit including logic gatemay be configured to logically alternate the output polarity of the output stage during the first phase and the second phase of the chopper operation.

7 FIG.A 7 FIG.A 552 552 552 730 740 750 602 612 622 illustrates a schematic diagram of voltage comparatorin accordance with embodiments of the present disclosure. Voltage comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, voltage comparatormay include input stage, output stage, low-side offset controller, and a chopper circuit collectively formed by pass gates,, and.

730 731 732 731 732 731 735 732 736 733 731 732 750 730 733 735 736 730 737 731 738 732 737 738 737 738 737 738 731 732 731 732 731 732 7 FIG.A Input stagemay include first transistorand second transistorconfigured together as a differential pair. In some embodiments, first transistorand second transistormay be PMOS transistors. As shown in, the source of first transistormay be coupled to a first current source, and the source of second transistormay be coupled to a second current source. Resistormay be coupled between the respective sources of first transistorand second transistor. Accordingly, and as described in further detail below with reference to low-side offset controller, input offset compensation may be injected into input stagebased on the resistance value of resistorand the difference between the bias currents provided by first current sourceand second current source. Input stagemay further include a current sourcecoupled to the drain of first transistorand current sourcecoupled to the drain of second transistor. In some embodiments, the bias currents provided by current sourceand current sourcemay match each other. For example, in some embodiments, current sourceand current sourcemay be implemented by matching output branches of a current mirror such that the bias current provided by current sourcematches the bias current provided by current source. With first transistorand second transistorbeing configured together as a differential pair, first transistorand second transistormay amplify any difference in voltage signals received at the respective gates of first transistorand second transistor.

740 730 740 741 742 741 742 741 722 731 732 722 740 741 730 741 7 FIG.A Output stagemay be coupled to input stageand may be configured to generate the low-side comparison signal CALS. Output stagemay include output transistorand current source. In some embodiments, output transistor may be an NMOS transistor. As shown in, output transistormay have a source coupled to ground GND and a drain coupled to current source. The gate of output transistormay be coupled, via pass gate, to the drain of either first transistoror second transistordepending on the state of pass gate. Output stage, and output transistorin particular, may thus further amplify the output of input stage. In some embodiments, output transistormay generate the low-side comparison signal CALS at its drain.

730 740 552 602 612 622 730 740 In addition to input stageand output stage, voltage comparatormay include a chopper circuit collectively formed by pass gates,, and. The chopper circuit may be configured to alternate an input polarity of input stageduring a first phase and a second phase of the chopper signal CHP. The chopper circuit may also be configured to alternate an output polarity of output stageduring the first phase and the second phase of the chopper signal CHP.

7 FIG.A 601 602 612 622 As shown in, invertermay invert the chopper signal CHP to create an additional inverse chopper signal CHP_BAR. Pass gates,, andmay utilize CHP and CHP_BAR to selectively pass a signal from one of two pass-gate inputs to the pass-gate output.

7 FIG.A 602 731 552 731 552 612 732 552 732 552 602 612 730 As shown in, pass gatemay couple the gate of first transistorto the negative input terminal VIN− of voltage comparatorduring a first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of first transistorto the positive input terminal VIN+ of voltage comparatorduring a second phase when the inverse chopper signal CHP_BAR is in a logic-high state. In a similar manner, pass gatemay couple the gate of second transistorto the positive input terminal VIN+ of voltage comparatorduring the first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of second transistorto the negative input terminal VIN− of voltage comparatorduring the second phase when the inverse chopper signal CHP_BAR is in a logic-high state. Passs gateand pass gatemay thus alternate the input polarity of input stageduring the first phase and the second phase of the chopper operation.

7 FIG.A 730 740 740 622 741 732 741 731 622 740 As also shown in, the chopper circuit may be further configured to alternate the coupling between input stageand output stageduring the first phase and the second phase to alternate an output polarity of output stageduring the first phase and the second phase. For example, pass gatemay couple the gate of output transistorto the drain of second transistorduring a first phase when the chopper signal CHP is in a logic-high state, and may alternatively couple the gate of output transistorto the drain of first transistorduring a second phase when the inverse chopper signal CHP_BAR is in a logic-high state. Pass gatemay thus alternate the output polarity of output stageduring the first phase and the second phase.

750 552 750 735 736 731 732 730 735 736 731 732 750 735 736 735 736 733 735 736 730 750 552 306 Low-side offset controllermay be configured to adjust an input offset of voltage comparatorbased on LS_OFFSET. For example, low-side offset controllermay be configured to control first current sourceand second current sourcerespectively coupled to bias first transistorand second transistorof input stage. In some embodiments, first current sourceand second current sourcemay be configured to match when in a default state and to thereby provide equal bias currents to first transistorand second transistor. Based on the LS_OFFSET signal, low-side offset controllermay then adjust first current sourceand/or second current sourceto cause the respective currents provided by first current sourceand/or second current sourceto be different from each other. The resistance of resistormultiplied by the difference between the bias currents respectively provided by first current sourceand second current sourcewill inject an input offset into input stage. Accordingly, as described above, low-side offset controllermay adjust the input offset of voltage comparatorbased on the LS_OFFSET signal, to compensate for an offset detected by offset-compensation circuitas described above.

7 FIG.A 750 735 736 552 552 750 733 731 732 750 737 738 552 737 738 737 738 750 731 732 Although the embodiment shown inutilizes low-side offset controllerto control first current sourceand second current sourceto adjust the input offset of voltage comparator, any other scheme suitable to adjust the input offset of voltage comparatormay be utilized and controlled for example by low-side offset controller. For example, in some embodiments, resistormay be omitted and the sources of first transistorand second transistormay be coupled directly together and to a single current source. In such embodiments, the input offset may be adjusted by other suitable techniques. For example, low-side offset controllermay be configured to vary the respective bias currents of current sourceand current sourceto adjust the input offset of voltage comparator. In such example embodiments, current sourceand current sourcemay include matching output branches of a current mirror as described above, in addition to small adjustable current sources and/or current-mirror outputs configured to controllably adjust the total bias currents provided by current sourceand current source. As another example, low-side offset controllermay be configured to adjust a voltage drop directly at the gate of first transistorand/or at the gate of second transistor.

552 730 740 730 740 730 740 7 FIG.A Further, although the embodiment of voltage comparatorshown inincludes input stageand output stage, other embodiments may include other circuit topologies for input stageand output stage. Moreover, other embodiments may include additional intermediate stages between input stageand output stage. In such other embodiments, the output stage may be considered to be coupled to the input stage via the further intermediate stages.

7 FIG.B 5 FIG.A 7 FIG.A 7 FIG.B 7 FIG.A 562 562 552 562 562 552 730 750 601 602 612 730 750 601 602 612 551 illustrates a schematic diagram of voltage comparatorin accordance with embodiments of the present disclosure. Voltage comparatormay represent an alternate embodiment of voltage comparatordescribed above with reference toand. Voltage comparatormay be implemented in any suitable fashion according to the operation described in the present disclosure. As shown in, voltage comparatormay include certain components similar to voltage comparatordescribed above with reference to, including input stage, low-side offset controller, inverter, pass gate, and pass gate. Each of input stage, low-side offset controller, inverter, pass gate, and pass gatemay operate in a similar manner as described above for voltage comparator.

562 745 740 552 745 741 742 741 742 745 740 552 742 741 730 741 730 732 730 745 562 7 FIG.B Voltage comparatormay also include output stage. Similar to output stageof voltage comparator, output stagemay include output transistorand current source. Output transistorand current sourcemay operate in a similar manner within output stageas described above for output stageof voltage comparator. For example, current sourcemay bias output transistor, which may further amplify the output of input stage. As shown in, the gate of output transistormay be coupled to the output of input stageat the drain of second transistor. Thus, the coupling between input stageand output stagein voltage comparatormay remain the same across the first phase and the second phase of the chopper operation.

745 746 745 741 746 746 746 745 746 746 746 745 746 746 745 602 612 746 Output stagemay utilize logic gateto logically alternate the output polarity of output stageduring the first phase and the second phase of the chopper operation. For example, the drain of output transistormay be coupled to a first logic input of logic gate. One of the chopper signal CHP or the inverse chopper signal CHP_BAR may be coupled to a second logic input of logic gate. Logic gatemay thus utilize a logic operation to alternate the output polarity of output stageacross the first phase and the second phase of the chopper operation. For example, in some embodiments where the chopper signal CHP is coupled to the second logic input of logic gate, logic gatemay be implemented as an XNOR logic gate to generate the low-side comparison signal CALS. In other embodiments, logic gatemay be implemented as other types of logic gates suitable to alternate the output polarity of output stagedepending on the polarities of the signals coupled to the first logic input and the second logic input of logic gate. Further, for the purposes of the present disclosure, logic gatemay be considered part of output stageand/or part of the chopper circuit collectively formed by pass gateand pass gate. Accordingly, the chopper circuit including logic gatemay be configured to logically alternate the output polarity of the output stage during the first phase and the second phase of the chopper operation.

8 FIG.A 8 FIG.A 2 FIG.A 200 43 41 41 43 41 42 43 on off illustrates a waveform of an inductor current signal IL in the DC-DC converter of LED lighting systemin accordance with embodiments of the present disclosure. The inductor current signal IL inmay represent the current through inductordescribed above with reference to. During the on-time (t) of high-side transistor, the rising high-side current flows through high-side transistorand inductor. And during the off-time (t) of high-side transistor, when the low-side transistor is in an on-state, the falling low-side current flows through low-side transistorand inductor. Thus, the rising portion of IL may represent the high-side current, and the falling portion of IL may represent the low-side current.

2 FIG.C As described above with reference to, if the total time that IL is above the average-current threshold is equal to the total time that IL is below the average-current threshold, then the average output current IOUT may be equal to the average-current threshold. Accordingly, when the sum of t2 plus t3 is equal to the sum of t1 plus t4, the average output current IOUT may be equal to the average-current threshold set according to the desired average output current of the buck converter.

41 42 43 104 104 41 41 41 42 43 104 104 43 41 42 216 a n a n 8 FIG.A 8 FIG.B 8 FIG.C 8 FIG.D Under some conditions, parasitic resistances in the DC-DC converter, such as the on-state resistances of high-side transistorand low-side transistor, the series resistance of inductor, and/or the series resistance of the plurality of LEDs-, may cause the inductor current signal IL to include a curvature, such as shown in. When high-side transistoris switching at a fifty percent duty cycle, the curvature of the rising slope and the falling slope may effectively cancel each other out, and average output current IOUT may remain equal to the average-current threshold when the sum of t2 plus t3 is equal to the sum of t1 plus t4. However, at duty cycles less than or greater than fifty percent, the curvature of IL may introduce an error between the average output current IOUT and the average-current threshold when the sum of t2 plus t3 is equal to the sum of t1 plus t4. In some embodiments, the error for a given embodiment may depend specifically on the duty cycle at which high-side transistoris operating. For example, as the duty cycle increases further above fifty percent, or decreases further below fifty percent, the IL waveform may be predominated more by one of the rising slope or the falling slope of IL. Thus, under certain conditions, the error may become greater with larger duty cycles further above fifty percent, or with smaller duty cycles further below fifty percent. The error may also depend on a number of factors affecting the rising and falling slopes of IL. For example, the error may depend on the input voltage VIN and output voltage VOUT, as well as the combined parasitic resistance including the on-state resistances of high-side transistorand low-side transistor, the series resistance of inductor, and/or the series resistance of the plurality of LEDs-. As another example, and as described below with reference to, the error may also depend on the inductance value of inductor. As yet another example, and as described below with reference to, the error may depend on the switching frequency of high-side transistorand low-side transistorAnd as described below with reference to, curvature compensation circuitmay account for one or more of these factors when compensating for curvature-induced errors.

8 FIG.B 8 FIG.B 43 201 43 44 41 42 202 851 852 851 852 illustrates plot diagrams of a curvature error in accordance with embodiments of the present disclosure. Specifically,illustrates plot diagrams demonstrating the effect that the inductance value of inductormay have on the curvature error for the DC-DC converter formed by DC-DC converter circuit, inductor, and capacitor. As described above, in some embodiments, the switching frequency of high-side transistorand low-side transistormay vary or may be controlled and/or held constant by control circuit. Plotand plotillustrate the current error for the average-current regulation caused by the curvature of IL under a fixed switching frequency, of for example 500 kHz, and with varied inductor values. For example, plotillustrates the current error for the average-current regulation caused by the curvature of IL with an inductor value of 44 μH, and plotillustrates the current error for the average-current regulation caused by the curvature of IL with an inductor value of 22 μH.

8 FIG.B 8 FIG.B 41 852 851 As shown in, the curvature-induced error in the average-current regulation may be zero when the duty cycle of high-side transistoris at fifty percent. The error may then vary as the duty cycle varies above or below fifty percent. As shown by plotrelative to plotin, a smaller inductance value may cause the error curve to have a different shape and a greater magnitude across duty cycles greater and lesser than fifty percent. The smaller inductance value may result in a greater curvature-induced error due to the larger ripple on the IL curve that may be present at a given switching frequency and average-current setting due to the smaller inductance value.

8 FIG.C 8 FIG.C 41 42 201 43 44 41 42 202 861 862 861 202 862 202 illustrates plot diagrams of a curvature error in accordance with embodiments of the present disclosure. Specifically,illustrates plot diagrams demonstrating the effect that the switching frequency of high-side transistorand low-side transistormay have on the curvature error for the DC-DC converter formed by DC-DC converter circuit, inductor, and capacitor. As described above, in some embodiments, the switching frequency of high-side transistorand low-side transistormay vary or may be controlled and/or held constant by control circuit. Plotand plotillustrate the current error for the average-current regulation caused by the curvature of IL under different switching frequency conditions. For example, plotillustrates the current error for the average current regulation caused by the curvature of IL when control circuitholds the switching frequency at 500 kHz for example, and plotillustrates the current error for the average-current regulation caused by the curvature error of IL when the switching frequency is uncontrolled and thus follows the hysteretic operation of control circuit.

8 FIG.C 8 FIG.C 8 FIG.D 41 862 861 216 As shown in, the curvature-induced error in the average-current regulation may be zero when duty cycle of high-side transistoris at fifty percent. The error may then vary as the duty cycle varies above or below fifty percent. As shown by plotrelative to plotin, the varied switching frequency may cause the error curve to have a different shape and a greater magnitude, particularly at small duty cycles below twenty-five percent and large duty cycles above seventy-five percent. As described below with reference to, curvature compensation circuitmay account for these factors, and other factors, when compensating for curvature-induced errors.

8 FIG.D 216 216 216 802 804 806 808 810 illustrates a schematic block diagram of curvature compensation circuitin accordance with embodiments of the present disclosure. Curvature compensation circuitmay be implemented in any suitable fashion according to the operation described in the present disclosure. In some embodiments, curvature compensation circuitmay include compensator, compensation table, serial-resistance scaler, analog-to-digital converter (ADC), and ripple scaler.

216 201 41 216 201 41 41 42 201 43 201 216 200 2 FIG.A Curvature compensation circuitmay be configured to adjust an average-current regulation of DC-DC converter circuitshown inin response to the duty cycle of high-side transistorand a set of compensation coefficients. Specifically, curvature compensation circuitmay be configured to adjust the average current of DC-DC converter circuitin response to the duty cycle of high-side transistorand a set of compensation coefficients that may compensate for the error induced by the curvature of IL. As described above, the respective high-side and low-side currents through high-side transistorand low-side transistorof DC-DC converter circuitmay collectively represent the inductor current IL of inductor, and thus also the output current IOUT. By adjusting the average current or the average-current regulation of DC-DC converter circuit, curvature compensation circuitmay thus adjust the average output current for the buck converter within LED lighting systemas a whole.

802 41 802 308 308 41 308 802 216 802 2 FIG.A 8 FIG.D 3 FIG.A In some embodiments, compensatormay store a set of compensation coefficients to be applied to adjust the average-current regulation based on the duty cycle of high-side transistor. As shown collectively inand, compensatormay receive a duty cycle signal DUTY from time-comparison circuit. As described above with reference to, time-comparison circuitmay receive counts for each of the first time period (t1), the second time period (t2), the third time period (t3), and the fourth time period (t4). The duty cycle is the ratio of the on-time (t1+t2) divided by the sum of the on-time plus the off-time (t1+t2+t3+t4) for high-side transistor. Thus, time-comparison circuitmay calculate the duty cycle and send the duty cycle signal DUTY representative of the duty cycle to the compensatorwithin curvature compensation circuit. Based on the duty cycle, compensatormay select and apply a corresponding compensation coefficient to the average-current regulation.

802 216 802 216 802 In some embodiments, the set of compensation coefficients may be fixed values dependent on the duty cycle. For example, the compensation coefficients may be selected from predefined curves based on the duty cycle. Compensatormay, in some embodiments, include a look-up table that may store a compensation coefficient for each of a plurality of duty cycles. Thus, in some embodiments, curvature compensation circuit, and compensatorin particular, may be configured to select the compensation coefficient from the look-up table based on the duty cycle. In other embodiments, curvature compensation circuit, and compensatorin particular, maybe configured to provide the compensation coefficient based on a programmed compensation-function that outputs a coefficient-value as a function of the duty cycle. In such embodiments, the programmed compensation-function may approximate the required curvature compensation as a function of the duty cycle.

802 308 201 200 Compensatormay thus receive the duty cycle information from time-comparison circuitand provide the corresponding compensation coefficient from a compensation-function or select the corresponding compensation coefficient from a look-up table. In some embodiments, the look-up table may be programmable. For example, the look-up table may be populated with fixed and/or programmed values for the compensation coefficients. In some embodiments, DC-DC converter circuitand/or LED lighting systemas a whole may be tested under varied conditions and the look-up table may be programmed based on the results of the measured output current IOUT versus the average-current setting IAVG across different duty cycles.

216 201 216 202 41 216 41 802 216 41 216 230 261 262 2 FIG.A 2 FIG.A 5 FIG.A Curvature compensation circuitmay be configured to adjust the average-current regulation of DC-DC converter circuitshown inin one or more ways. In some embodiments, curvature compensation circuitmay be configured to provide the compensated average-current threshold IAVG_COMP to control circuitin response to an average-current setting IAVG and a compensation coefficient that is based at least in part on the duty cycle of high-side transistor. For example, curvature compensation circuitmay be configured to adjust the average-current threshold based on a set of compensation coefficients and the duty cycle of high-side transistor. The compensatorwithin curvature compensation circuitmay select a compensation coefficient, for example from a look-up table, based on the duty cycle of high-side transistor, and may apply the selected compensation coefficient to the average-current setting IAVG to generate the compensated average-current threshold IAVG_COMP. As described above with reference toand, curvature compensation circuitmay in turn provide the compensated average current threshold IAVG_COMP to average-current reference generator, which may provide the high-side average current reference IAVG_HS and the low-side average current reference IAVG_LS to high-side comparatorand to low-side comparatorrespectively.

202 201 216 216 202 Although control circuitis described above as a hysteretic control circuit that regulates the average current of DC-DC converter circuitand the average current of DC-DC converter as a whole, curvature compensation circuitmay in some embodiments also provide curvature compensation for other types of average-current regulation controls circuits. For example, curvature compensation circuitmay provide a compensated average-current threshold IAVG_COMP based on the average-current setting IAVG and the selected and/or scaled compensation coefficient to control circuits that, for example, utilize a fixed switching frequency and modulate the on-time and/or off-time of the high-side transistor to regulate the average current, or as another example utilize a fixed on-time and/or off-time of the high-side transistor and modulate the switching frequency to regulate the average current. In such other embodiments, the curvature compensation may operate in the same manner as described herein with reference to embodiments involving the hysteretic control of control circuit.

216 802 216 41 802 308 212 308 308 Curvature compensation circuitmay also, in some embodiments, be configured to scale a comparison of a sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3) based on a set of compensation coefficients and the duty cycle. The compensatorwithin curvature compensation circuitmay select a compensation coefficient, for example from a look-up table, based on the duty cycle of high-side transistor, and may generate a scaling factor. Compensatormay then send a compensation signal CV_COMP, indicating the scaling factor, to the time-comparison circuitwithin timer circuit. Time-comparison circuitmay then scale comparison of the sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3) when determining adjustments to the peak threshold and the valley threshold and outputting P_ADJ and V_ADJ accordingly. For example, according to the scaling factor, time-comparison circuitmay target adjustments to the peak threshold and/or the valley threshold to make the sum of t1 plus t4 either less or more than the sum of t2 plus t3 by an amount that may compensate against the curvature error and bring the average output current in line with the average-current setting IAVG.

216 216 806 802 41 42 43 104 104 802 806 a n In some embodiments, curvature compensation circuitmay be configured to adjust the average-current regulation of the DC-DC converter based at least in part on a serial parasitic resistance associated with the DC-DC converter. For example, the compensation coefficient provided by curvature compensation circuitmay be based on a parasitic serial resistance value associated with the DC-DC converter. Serial-resistance scalermay provide information to compensatorregarding serial parasitic resistance present in the DC-DC converter. As described above, the serial parasitic resistance of the DC-DC converter may include one or more of the on-state resistances of high-side transistorand low-side transistor, the series resistance of inductor, and/or the series resistance of the plurality of LEDs-. As also described above, the curvature error induced by the serial parasitic resistance may depend on the serial parasitic resistance, with larger serial parasitic resistance causing larger curvature error. Thus, to account for the serial parasitic resistance, compensatormay select the compensation coefficient and/or scale the compensation coefficient, for a given duty cycle, based on an input from serial-resistance scaler.

806 216 806 41 806 802 806 808 806 806 201 802 806 2 FIG.A 8 FIG.D In some embodiments, the parasitic serial resistance value may be programmable. For example, serial-resistance scalermay be programmed with an expected or measured serial parasitic resistance value. In other embodiments, curvature compensation circuit, and serial-resistance scalerin particular, may be configured to calculate the parasitic serial resistance value based on the input voltage VIN, the output voltage VOUT, the duty cycle of high-side transistor, and the average-current setting IAVG. The serial parasitic resistance may be calculated, for example, by dividing the difference between the ideal output voltage and the actual output voltage VOUT by the output current IOUT. For a buck-topology DC-DC converter, such as shown in, the ideal output voltage may equal VIN times the duty cycle. Thus, the parasitic resistance may be calculated based on the input voltage VIN, the actual output voltage VOUT, the duty cycle, and the output current IOUT. As shown in, serial-resistance scalermay receive the duty cycle information via the DUTY signal received by compensator. Further, serial-resistance scalermay utilize the average-current setting IAVG as an approximation of the actual average output current IOUT. In addition, ADCmay measure VIN and VOUT and provide measurement signals VIN_MEAS and VOUT_MEAS to serial-resistance scaler. Accordingly, based on the input voltage VIN, the actual output voltage VOUT, the duty cycle, and an approximation of the output current IOUT, serial-resistance scalermay calculate the serial-parasitic resistance present in the DC-DC converter in which DC-DC converter circuitis implemented. And as described directly above, compensatormay select the compensation coefficient and/or scale the compensation coefficient, for a given duty cycle, based on the serial-parasitic resistance information from serial-resistance scaler.

216 41 42 216 41 42 802 308 308 41 308 802 216 2 FIG.A 8 FIG.D 3 FIG.A 8 FIG.D In some embodiments, curvature compensation circuitmay be configured to adjust the average-current regulation of the DC-DC converter based at least in part on the switching frequency of high-side transistorand/or low-side transistor. For example, the compensation coefficient provided by curvature compensation circuitmay be based on the switching frequency of high-side transistorand/or low-side transistor. As shown collectively inand, compensatormay receive a duty cycle signal DUTY from time-comparison circuit. As described above with reference to, time-comparison circuitmay receive counts for each of the first time period (t1), the second time period (t2), the third time period (t3), and the fourth time period (t4). The duty cycle is the ratio of the on-time (t1+t2) divided by the sum of the on-time plus the off-time (t1+t2+t3+t4) for high-side transistor. And as described above with reference to, time-comparison circuitmay calculate the duty cycle and send the duty cycle signal DUTY representative of the duty cycle to the compensatorwithin curvature compensation circuit.

41 42 308 802 802 41 42 Additionally, the sum of t1, t2, t3, and t4 may represent the switching period of high-side transistorand low-side transistor, which is the inverse of the switching frequency thereof. Accordingly, time-comparison circuitmay calculate the switching frequency and send the switching frequency information to compensatoras part of the DUTY signal, or via a separate signal dedicated to communicating the switching frequency. Based on the switching frequency, compensatormay select and/or scale the compensation coefficients to adjust the average-current regulation according to the switching frequency of high-side transistorand/or low-side transistor.

216 216 201 810 802 802 810 In some embodiments, curvature compensation circuitmay be configured to adjust the average-current regulation of the DC-DC converter based at least in part on a current ripple of the DC-DC converter. For example, the compensation coefficient provided by curvature compensation circuitmay be based on a current-ripple value for DC-DC converter circuit. Ripple scalermay provide information to compensatorregarding current ripple present in the DC-DC converter. As described above, the curvature error may depend in part on the amount ripple in the inductor current IL during a given switching cycle, with larger current ripples causing larger curvature error. Thus, to account for the current ripple of IL, compensatormay either select the compensation coefficient or scale a compensation coefficient, for a given duty cycle, based on the input from ripple scaler.

810 810 810 251 252 810 802 8 FIG.D In some embodiments, ripple scalermay be programmed with an expected or measured current ripple value. In other embodiments, ripple scalermay calculate the current ripple present in the DC-DC converter. For example, though not shown in, ripple scalermay receive information regarding the peak threshold and the valley threshold used by peak comparatorand valley comparator. Ripple scalermay then calculate the current ripple based on the difference between the peak threshold and the valley threshold, and provide the calculated current ripple to compensator. In such embodiments, the current-ripple value may represent a difference between the peak current of the DC-DC converter circuit and a valley current of the DC-DC converter circuit.

43 216 43 41 42 201 201 810 802 41 41 42 42 810 43 802 L The amount of current ripple in the DC-DC converter may depend, for example, on the inductance of inductor. Thus, in some embodiments, the compensation coefficient provided by curvature compensation circuitmay be based on an inductance value representative of the inductance of inductor. In some embodiments, the inductance value may be programmable. In other embodiments, curvature compensation circuit may be configured to calculate the inductance value based on one of a high-side on-time of high-side transistorand a low-side on-time of low-side transistorand based on a difference between a peak current of DC-DC converter circuitand a valley current of DC-DC converter circuit. The inductance value may be calculated and used as a scaler in place of or in addition to the current ripple information provided by ripple scalerto compensator. Inductance (L) may be calculated for example by the voltage applied across the inductor divided by the rate of change in the current (L=V/(di/dt)). During the on-time of high-side transistor, the voltage across the inductor may be equal to the input voltage VIN minus the output voltage VOUT. Further, the rate of change of the rising current (di/dt) during the on-time of high-side transistormay be the difference between the valley threshold and the peak threshold divided by the sum of the first time period (t1) and the second time period (t2). Conversely, during the on-time of low-side transistor, the voltage across the inductor may be equal to zero minus the output voltage VOUT. Further, the rate of change of the falling current (di/dt) during the on-time of low-side transistormay be the difference between the peak threshold and the valley threshold divided by the sum of the third time period (t3) and the fourth time period (t4). Thus, based on the aforementioned inputs, ripple scalermay calculate the inductance value for inductorand provide the inductance value to compensatorfor selecting and/or scaling the compensation coefficients.

9 FIG. 9 FIG. 9 FIG. 900 900 201 900 900 900 illustrates an example methodfor operating a DC-DC converter circuit in accordance with embodiments of the present disclosure. Methodmay be performed by any suitable mechanism, such as the elements of DC-DC converter circuitdescribed herein. Methodmay be performed with fewer or more steps than shown in. Moreover, steps of methodmay be omitted, repeated, performed in parallel, performed in a different order than shown in, or performed recursively. One or more steps of method, although shown in an order, may be performed at the same time or in a re-ordered manner.

902 251 41 2 FIG.A Stepmay include comparing a high-side current through a high-side transistor against a peak threshold to generate a peak signal. For example, as described above with reference to, peak comparatormay compare the high-side current through high-side transistoragainst a peak threshold to generate peak signal CP.

904 252 42 2 FIG.A Stepmay include comparing a low-side current through a low-side transistor against a valley threshold to generate a valley signal. For example, as described above with reference to, valley comparatormay compare the low-side current through low-side transistoragainst a valley threshold to generate valley signal CV.

906 240 41 42 240 41 42 41 41 43 251 240 41 42 42 43 42 252 240 42 41 2 FIG.A Stepmay include driving a high-side transistor and a low-side transistor of the DC-DC converter in response to the peak signal and the valley signal. For example, as described above with reference to, PWM circuitmay drive high-side transistorand low-side transistorin response to the peak signal CP and the valley signal CV. At the beginning of a switching cycle, PWM circuitmay drive high-side transistorin an on-state and low-side transistorin an off-state. During the on-time of high-side transistor, the high-side current through high-side transistorand inductorwill rise. When the high-side current reaches and crosses above the peak threshold, peak comparatormay assert the peak signal CP to instruct PWM circuitto turn off high-side transistorand to turn on low-side transistor. During the on-time of low-side transistor, the low-side current through inductorand low-side transistormay decrease from a value at or near the peak threshold. When the low-side current reaches and crosses below the valley threshold, valley comparatormay assert the valley signal CV to instruct PWM circuitto turn off low-side transistorand to turn on high-side transistorto start a new switching cycle.

908 910 212 302 212 302 2 FIG.A 3 FIG.A Stepmay include measuring a first time period during which the high-side current is less than an average-current threshold. And stepmay include measuring a second time period during which the high-side current is greater than the average-current threshold. For example, as described above with reference toand, timer circuitmay be configured to measure the first time period (t1) during which the high-side current is less than the average-current threshold, and to measure the second time period (t2) during which the high-side current is greater than the average-current threshold, based on the clock signal CLK and the high-side comparison signal CAHS. To measure the first time period (t1), high-side counterwithin timer circuitmay count the number of clock pulses when high-side comparison signal CAHS indicates that the high-side current is less than the average-current threshold. Likewise, to measure the second time period (t2), high-side countermay count the number of clock pulses when high-side comparison signal CAHS indicates that the high-side current is greater than the average-current threshold.

912 914 212 304 212 304 2 FIG.A Stepmay include measuring a third time period during which the low-side current is greater than the average-current threshold. And stepmay include measuring a fourth time period during which the low-side current is less than the average-current threshold. For example, as described above with reference to, timer circuitmay be configured to measure the third time period (t3) during which the low-side current is greater than the average-current threshold, and to measure the fourth time period (t4) during which the low-side current is less than the average-current threshold, based on the clock signal CLK and the low-side comparison signal CALS. To measure the third time period (t3), low-side counterwithin timer circuitmay count the number of clock pulses when low-side comparison signal CALS indicates that the low-side current is greater than the average-current threshold. Likewise, to measure the fourth time period (t4), low-side countermay count the number of clock pulses when low-side comparison signal CALS indicates that the low-side current is less than the average-current threshold.

916 212 308 212 308 212 214 2 FIG.A 3 FIG.A Stepmay include adjusting the peak threshold and the valley threshold in response to the first time period, second time period, third time period, and fourth time period. In some embodiments, the adjusting may specifically include adjusting the peak threshold and the valley threshold based on a comparison of a sum of the first time period and the fourth time period against a sum of the second time period and the third time period. For example, as described above with reference toand, timer circuit, and in particular the time-comparison circuitof timer circuit, may be configured to adjust the peak threshold and the valley threshold based on the comparison of a sum of the first time period (t1) and the fourth time period (t4) against a sum of the second time period (t2) and the third time period (t3). For example, to the extent that the sum of t1 plus t4 differs from the sum of t2 plus t3, time-comparison circuitof timer circuitmay provide a peak adjustment signal P_ADJ and/or a valley adjustment signal V_ADJ to peak-and-valley controller. The adjustment to the peak threshold and/or the valley threshold may be targeted to bring the sum of t1 plus t4 in alignment with the sum of t2 plus t3, such that the average output current of the buck converter may accurately track the desired average output current.

Although examples have been described above, other modifications and variations may be made from this disclosure without departing from the spirit and scope of these examples. The above descriptions of various embodiments illustrate the principles of the invention. Numerous variations and modifications will become apparent to those skilled in the art based on the above disclosure. The following claims are intended to embrace all such variations and modifications.