Display device

This application claims priority to Korean Patent Application No. 10-2022-0088806, filed on Jul. 19, 2022, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

The disclosure herein relates to a display device, and more particularly, to a display device with an appearance that changes based on an operation mode.

Electronic devices such as smart phones, tablet computers, laptop computers, automotive navigation system units, and smart televisions are being developed. Such electronic devices are typically provided with a display device to provide information.

In order to improve user experience and user interface, display devices are being developed in various shapes. Among the display devices, flexible display devices are being actively developed.

Embodiments of the disclosure provide a display device which has improved impact resistance properties, and which may prevent the occurrence of visibility limitations at a boundary portion thereof.

An embodiment of the invention provides a display device including a support plate including a first region, a second region adjacent to the first region, and a third region adjacent to the second region, where a plurality of first openings is defined in the third region, and the third region includes a first support portion between adjacent first openings of the plurality of first openings, and a display panel divided into a first display region overlapping the first region, a second display region overlapping the second region, and a third display region overlapping the third region, where the display panel including a plurality of light emitting elements and a plurality of pixel circuits. In such an embodiment, the second display region includes a first partial region in which a first pixel circuit, a second pixel circuit, and a first light emitting element are disposed, and a second partial region in which a second light emitting element is disposed. In such an embodiment, the third display region includes a third partial region in which a third pixel circuit, a fourth pixel circuit, and a third light emitting element are disposed and which overlaps at least a portion of the first support portion, and a fourth partial region in which a fourth light emitting element is disposed, and which overlaps each of the plurality of first openings. In such an embodiment, a first separation distance between the second pixel circuit and the second light emitting element is less than a second separation distance between the fourth pixel circuit and the fourth light emitting element.

In an embodiment, the first region and the second region may be defined by flat portions of the support plate, which are integrally formed with each other as a single unitary and indivisible part.

In an embodiment, a plurality of second openings may be defined in the second region, the second region may include a second support portion between adjacent second openings of the plurality of second openings, and a width of each of the plurality of second openings in a first direction may be less than a width of each of the plurality of first openings in the first direction.

In an embodiment, the first partial region may overlap at least a portion of the second support portion, and the second partial region may overlap each of the plurality of second openings.

In an embodiment, the plurality of pixel circuits may further include a fifth pixel circuit and a fifth light emitting element electrically connected to the fifth pixel circuit, and the fifth pixel circuit and the fifth light emitting element may be disposed in the first display region.

In an embodiment, the planar area of the fifth pixel circuit may be substantially the same as the planar area of each of the first pixel circuit to the fourth pixel circuit.

In an embodiment, an arrangement of light emitting elements in the first display region may be substantially the same as an arrangement of light emitting elements in the second display region and an arrangement of light emitting elements in the third display region.

In an embodiment, a density of pixel circuits in the first display region is defined as a first circuit density, a density of pixel circuits in the first partial region is defined as a second circuit density, a density of pixel circuits in the second partial region is defined as a third circuit density, and the first circuit density may be less than the second circuit density, and greater than the third circuit density.

In an embodiment, a density of pixel circuits in the third partial region is defined as a fourth circuit density, a density of pixel circuits in the fourth partial region is defined as a fifth circuit density, and the first circuit density may be less than the fourth circuit density, and greater than the fifth circuit density.

In an embodiment, the display panel may further include a first dummy pixel circuit disposed in the second partial region, and a second dummy pixel circuit disposed in the fourth partial region.

In an embodiment, a density of pixel circuits in the first partial region is defined as a second circuit density, a density of first dummy pixel circuits in the second partial region is defined as a first dummy pixel density, and the second circuit density and the first dummy circuit density may be substantially the same as each other.

In an embodiment, a density of pixel circuits in the third partial region is defined as a fourth circuit density, a density of second dummy pixel circuits in the fourth partial region is defined as a second dummy pixel density, and the fourth circuit density and the second dummy circuit density may be substantially the same as each other.

In an embodiment, the width of the third partial region in a first direction may be greater than the width of the first partial region in the first direction.

In an embodiment, the display panel may further include a first connection line connected between the second pixel circuit and the second light emitting element, and a second connection line connected between the fourth pixel circuit and the fourth light emitting element, where each of the first connection line and the second connection line may be disposed in a different layer from the layer in which an anode of each of the second light emitting element and the fourth light emitting element is disposed, and an extension length of the second connection line in a first direction may be greater than an extension length of the first connection line in the first direction.

In an embodiment, a pixel circuit may not be disposed in each of the second partial region and the fourth partial region.

In an embodiment, the third region and the third display region may be unfolded in a first mode, and folded in a second mode.

In an embodiment, each of the first region to the third region may be provided in plural, and each of a plurality of third regions may be disposed between two adjacent second regions among a plurality of second regions.

In an embodiment, the support plate may include a metal.

In an embodiment, the first support portion of the support plate may include a plurality of first extension portions arranged in a first direction and extending in a second direction crossing the first direction, and a second extension portions disposed between adjacent first extension portions among the plurality of first extension portions, and extending in the first direction.

In an embodiment, the first extension portions and the second extension portions may define a grid shape.

In an embodiment of the invention, a display device includes a support plate including a first region, a second region adjacent to the first region, and a third region adjacent to the second region, where a plurality of first openings is defined in the third region, and the third region includes a first support portion between adjacent first openings of the plurality of first openings, and a display panel including a first display region overlapping the first region, a second display region overlapping the second region, and a third display region overlapping the third region, where the display panel includes a plurality of light emitting elements and a plurality of pixel circuits. In such an embodiment, the plurality of pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit. In such an embodiment, the plurality of light emitting elements include a first light emitting element connected to the first pixel circuit, a second light emitting element connected to the second pixel circuit, a third light emitting element connected to the third pixel circuit, and a fourth light emitting element connected to the fourth pixel circuit. In such an embodiment, the second display region includes a first partial region in which the first pixel circuit, the second pixel circuit, and the first light emitting element are disposed, and a second partial region in which the second light emitting element is disposed, and the third display region includes a third partial region in which the third pixel circuit, the fourth pixel circuit, and the third light emitting element are disposed and which overlaps at least a portion of the first support portion, and a fourth partial region in which the fourth light emitting element is disposed, and which overlaps each of the plurality of first openings. In such an embodiment, an arrangement of light emitting elements in the first display region is substantially the same as an arrangement of light emitting elements in the second display region and an of light emitting elements in the third display region, and a width of the third partial region in a first direction is greater than a width of the first partial region in the first direction.

In an embodiment of the invention, a display device includes a display panel divided into a first region, a second region, and a third region sequentially disposed along one direction, where the display panel includes a plurality of light emitting elements and a plurality of pixel circuits. In such an embodiment, the first region has a constant shape when an operation mode changes, and the third region has a shape which changes according to a change of the operation mode. In such an embodiment, the plurality of pixel circuits include a first pixel circuit, a second pixel circuit, a third pixel circuit, and a fourth pixel circuit, and the plurality of light emitting elements include a first light emitting element connected to the first pixel circuit, a second light emitting element connected to the second pixel circuit, a third light emitting element connected to the third pixel circuit, and a fourth light emitting element connected to the fourth pixel circuit. In such an embodiment, the second region includes a first partial region in which the first pixel circuit, the second pixel circuit, and the first light emitting element are disposed, and a second partial region in which the second light emitting element is disposed. In such an embodiment, the third region includes a third partial region in which the third pixel circuit, the fourth pixel circuit, and the third light emitting element are disposed, and a fourth partial region in which the fourth light emitting element is disposed. In such an embodiment, a first separation distance between the second pixel circuit and the second light emitting element is less than a second separation distance between the fourth pixel circuit and the fourth light emitting element.

The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the disclosure, when an element (or an area, a layer, a portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it means that the element may be directly connected to/coupled to the other element, or that a third element may be disposed therebetween.

Like reference numerals refer to like elements. Also, in the drawings, the thickness, the ratio, and the dimensions of elements are exaggerated for an effective description of technical contents.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and a second element may also be referred to as a first element in a similar manner without departing from the teachings herein.

In addition, terms such as “below,” “lower,” “above,” “upper,” and the like are used to describe the relationship of components shown in the drawings. The terms are used as a relative concept and are described with reference to the direction indicated in the drawings.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

In the disclosure, being “directly disposed” may mean that there is no layer, film, region, plate, or the like added between a portion of a layer, a film, a region, a plate, or the like and other portions. For example, being “directly disposed” may mean being disposed without additional members such as an adhesive member between two layers or two members.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is also to be understood that terms such as terms defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings in the context of the related art, and should not be interpreted in too ideal a sense or an overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings.

1 FIG.A 1 FIG.C 1 FIG.A 1 FIG.B 1 FIG.C toare perspective views of an electronic device according to an embodiment of the invention.illustrates an electronic device ED of an embodiment in an unfolded state, andandillustrate the electronic device ED of an embodiment in a folded state.

1 FIG.A 1 FIG.C 1 2 1 Referring toto, the electronic device ED according to an embodiment of the invention may include a display surface DS on a plane defined by a first direction DRand a second direction DRcrossing the first direction DR. The electronic device ED may provide an image IM to a user through the display surface DS.

The display surface DS may include a display region DA and a non-display region NDA around the display region DA. The display region DA may display the image IM, and the non-display region NDA may not display the image IM. The non-display region NDA may surround the display region DA. However, the embodiment of the invention is not limited thereto. The shape of the display region DA, and a shape of the non-display region NDA may be variously modified.

1 2 3 3 3 3 Hereinafter, a direction substantially perpendicularly crossing the plane defined by the first direction DRand the second direction DRis defined as a third direction DR. The third direction DRmay be a thickness direction of the electronic device ED. The third direction DRbecomes a reference that distinguishes the front surface and the rear surface of each member. In the disclosure, “on a plane” may be defined as a state viewed in the third direction DR.

1 2 1 2 1 2 2 1 2 The electronic device ED may include a folding region FA and a plurality of non-folding regions NFAand NFA. The non-folding regions NFAand NFAmay include a first non-folding region NFAand a second non-folding region NFA. In the second direction DR, the folding region FA may be disposed between the first non-folding region NFAand the second non-folding region NFA.

1 2 The electronic device ED in a first mode may be defined as the electronic device ED in an unfolded state, and the electronic device ED in a second mode may be defined as the electronic device ED in a folded state. As the electronic device ED changes from the first mode to the second mode, the shape of the folding region FA changes, but the shapes of the non-folding regions NFAand NFAdo not change.

1 FIG.B 1 1 1 2 As illustrated in, in an embodiment, the folding region FA may be folded with respect to a folding axis FX parallel to the first direction DR. The folding region FA has a predetermined curvature and a predetermined radius of curvature R. The first non-folding region NFAand the second non-folding region NFAface each other, and the electronic device ED may be inner-folded such that the display surface DS is not exposed to the outside.

In an embodiment of the invention, the electronic device ED may be outer-folded such that the display surface DS is exposed to the outside. In an embodiment of the invention, the electronic device ED may be configured in a way such that an inner-folding or outer-folding operation may be alternatively repeated from an un-folding operation, but the embodiment of the invention is not limited thereto. In an embodiment of the invention, the electronic device ED may be configured to selectively perform one of the un-folding operation, the inner-folding operation, and the outer-folding operation.

1 FIG.B 1 FIG.C 1 FIG.B 1 FIG.C 2 FIG. 1 2 1 1 2 1 1 2 In an embodiment, as illustrated in, the distance between the first non-folding region NFAand the second non-folding region NFAmay be substantially the same as two times the radius of curvature Rin a folded state. In an alternative embodiment, as illustrated in, the distance between the first non-folding region NFAand the second non-folding region NFAmay be less than two times the radius of curvature Rin a folded state.andare illustrated with respect to the display surface DS, and a housing HM (see) forming the appearance of the electronic device ED may be in contact in end regions of the first non-folding region NFAand the second non-folding region NFA.

2 FIG. is an exploded perspective view of an electronic device according to an embodiment of the invention.

2 FIG. As illustrated in, an embodiment of the electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and the housing HM. Although not separately illustrated, the electronic device ED may further include an instrument structure for controlling a folding operation of the display device DD.

The display device DD generates an image and senses an external input. The display device DD includes a window WM and a display module DM. The window WM define the front surface of the electronic device ED.

2 FIG.A The display module DM may include at least the display panel DP.illustrates only the display panel DP among laminated structures of the display module DM, but the display module DM may substantially further include a plurality of components disposed on an upper side of the display panel DP. The laminate structure of the display module DM will be described in detail later.

The display panel DP is not particularly limited, and may be, for example, a light emitting-type display panel such as an organic light emitting display panel or an inorganic light emitting display panel.

1 FIG.A 1 FIG.A The display panel DP includes a display region DP-DA and a non-display region DP-NDA respectively corresponding to the display region DA (see) and the non-display region NDA (see) of the electronic device ED. In the disclosure, when “a region/portion corresponds to a region/portion,” it means that the region/portion overlaps the region/portion, and the regions/portions are not limited to having the same area.

2 FIG. In an embodiment, as illustrated in, a driving chip DIC may be disposed on the non-display region DP-NDA of the display panel DP. A flexible circuit board FCB may be coupled to the non-display region DP-NDA of the display panel DP. The flexible circuit board FCB may be connected to a main circuit board. The main circuit board may be one electronic component constituting the electronic module EM.

2 FIG. The driving chip DIC may include driving elements for driving a pixel of the display panel DP, for example, a data driving circuit.illustrates an embodiment having a structure in which the driving chip DIC is mounted on the display panel DP, but the invention is not limited thereto. In an alternative embodiment, for example, the driving chip DIC may be mounted on the flexible circuit board FCB.

The electronic module EM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, or the like. The electronic module EM may include the main circuit board, and the modules listed above may be mounted on the main circuit board, or may be electrically connected to the main circuit board through a flexible circuit board. The electronic module EM is electrically connected to the power module PSM.

2 FIG. 1 2 1 2 1 2 Referring to, the electronic module EM is disposed in each of a first housing HMand a second housing HM, and the power module PSM may be disposed in each of the first housing HMand the second housing HM. Although not illustrated, the electronic module EM disposed in the first housing HM, and the electronic module EM disposed in the second housing HMmay be electrically connected through a flexible circuit board.

Although not separately illustrated, the electronic device ED may further include an electronic optical module. The electronic optical module may be an electronic component configured to output or receive an optical signal. The electronic optical module may include a camera module and/or a proximity sensor. The camera module may capture external images through some regions of the display panel DP.

2 FIG. 1 2 1 2 The housing HM illustrated inis coupled to the display device DD, particularly the window WM, to accommodate the above other modules. The housing HM is illustrated as including the first and second housings HMand HMseparated from each other, but the embodiment of the invention is not limited thereto. Although not illustrated, the electronic device ED may further include a hinge structure for connecting the first and second housings HMand HM.

3 FIG. is a plan view of a display panel according to an embodiment of the invention.

3 FIG. 3 FIG. Referring to, an embodiment of the display panel DP may include the display region DP-DA and the non-display region DP-NDA around the display region DP-DA. A pixel PX is disposed in the display region DP-DA. A scan driver SDV, a data driver, and a light emitting driver EDV may be disposed in the non-display region DP-NDA. The data driver may be a part of circuits configured in the driving chip DIC illustrated in.

1 2 2 2 1 2 The display panel DP includes a first region AA, a second region AA, and a bending region BA, which are arranged in the second direction DR. The second region AAand the bending region BA may be parts of the non-display region DP-NDA. The bending region BA is disposed between the first region AAand the second region AA.

1 1 10 20 0 10 20 0 1 2 1 FIG.A 1 FIG.A 1 FIG.C The first region AAis a region corresponding to the display surface DS of. The first region AAmay include a first non-folding region NFA, a second non-folding region NFA, and a folding region FA. The first non-folding region NFA, the second non-folding region NFA, and the folding region FArespectively correspond to the first non-folding region NFA, the second non-folding region NFA, and the folding region FA ofto.

1 2 10 3 0 1 2 20 2 3 1 1 2 3 2 1 2 In an embodiment, the display region DP-DA includes two display regions, i.e., a first display region DAand a second display region DA, corresponding to the first non-folding region NFA. The display region DP-DA includes a third display region DPcorresponding to the folding region FA. The display region DP-DA includes two display regions, i.e., the first display region DAand the second display region DA, corresponding to the second non-folding region NFA. The second display regions DAmay be regions more adjacent to the third display region DAthan the first display regions DAare. In an embodiment, a first display region DA, a second display region DA, a third display region DA, a second display region DA, and a first display region DAmay be sequentially arranged in the display panel DP along the second direction DR.

1 2 1 1 1 In an embodiment, the length of the bending region BA in the first direction DRand the length of the second region AAin the first direction DRmay be less than the length of the first region AAin the first direction DR. In such an embodiment, the bending region BA is a region having a short length in a bending axis direction such that the bending region BA may be more easily bent.

1 1 1 1 2 1 1 1 The display panel DP may include a plurality of pixels PX, a plurality of scan lines SLto SLm, a plurality of data lines DLto DLn, a plurality of light emission lines ELto ELm, first and second control lines CSLand CSL, a power line PL, and a plurality of pads PD. Here, m and n are natural numbers. The pixels PX may be connected to the scan lines SLto SLm, the data lines DLto DLn, and the light emission lines ELto ELm.

1 2 1 2 1 1 The scan lines SLto SLm may extend in the second direction DR, and connected to the scan driver SDV. The data lines DLto DLn may extend in the second direction DR, and connected to the driving chip DIC via the bending region BA. The light emission lines ELto ELm may extend in the first direction DR, and connected to the light emission driver EDV.

2 1 1 2 2 2 The power line PL may include a portion extending in the second direction DRand a portion extended in the first direction DR. The portion extended in the first direction DRand the portion extending in the second direction DRmay be disposed in (or directly on) different layers from each other. The portion of the power line PL extending in the second direction DRmay be extended to the second region AAvia the bending region BA. The power line PL may provide a first voltage to the pixels PX.

1 2 2 2 The first control line CSLis connected to the scan driver SDV, and may extend toward a lower end of the second region AAvia the bending region BA. The second control line CSLis connected to the light emission driver EDV, and may extend toward the lower end of the second region AAvia the bending region BA.

2 1 2 On a plane, the pads PD may be disposed adjacent to the lower end of the second region AA. The driving chip DIC, the power line PL, the first control line CSL, and the second control line CSLmay be connected to the pads PD. The flexible circuit board FCB may be electrically connected to the pads PD through an anisotropic conductive adhesive layer.

4 FIG. is a cross-sectional view of a display module according to an embodiment of the invention.

4 FIG. 110 120 130 140 Referring to, an embodiment of the display module DM may include the display panel DP, an input sensor ISP, and an anti-reflection layer ARL. The display panel DP may include a base layer, a circuit layer, a light emitting element layer, and an encapsulation layer.

110 120 110 110 110 The base layermay provide a base surface on which the circuit layeris disposed. The base layermay be a flexible substrate capable of bending, folding, rolling, and the like. The base layermay be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the embodiment of the invention is not limited thereto, and alternatively, the base layermay be an inorganic layer, an organic layer, or a composite material layer.

110 110 The base layermay have a multi-layered structure. In an embodiment, for example, the base layermay include a first synthetic resin layer, a multi-layered or single-layered inorganic layer, and a second synthetic resin layer disposed on the multi-layered or single-layered inorganic layer. Each of the first and second synthetic resin layers may include a polyimide-based resin, but is not particularly limited thereto.

120 110 120 The circuit layermay be disposed on the base layer. The circuit layermay include an insulation layer, a semiconductor pattern, a conductive pattern, a signal line, or the like.

130 120 130 The light emitting element layermay be disposed on the circuit layer. The light emitting element layermay include a light emitting element. In an embodiment, for example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-light emitting diode (micro-LED), or a nano-light emitting diode (nano-LED).

140 130 140 130 140 140 The encapsulation layermay be disposed on the light emitting element layer. The encapsulation layermay protect the light emitting element layerfrom foreign materials such as moisture, oxygen, and dust particles. The encapsulation layermay include at least one inorganic layer. The encapsulation layermay include a laminate structure of an inorganic layer/an organic layer/an inorganic layer.

The input sensor ISP may be directly disposed on the display panel DP. The input sensor ISP may sense a user's input in a capacitive manner. The display panel DP and the input sensor ISP may be formed through a continuous process. Here, “being directly disposed” may mean that a third component is not disposed between the input sensor ISP and the display panel DP. That is, a separate adhesive layer may not be disposed between the input sensor ISP and the display panel DP.

The anti-reflection layer ARL may be directly disposed on the input sensor ISP. The anti-reflection layer ARL may reduce the reflectance of external light incident from the outside of the display device DD. The anti-reflection layer ARL may include color filters. The color filters may have a predetermined arrangement. In an embodiment, for example, the color filters may be arranged based on an arrangement of light emission colors of pixels included in the display panel DP. In addition, the anti-reflection layer ARL may further include a black matrix adjacent to the color filters.

In an embodiment of the invention, the position of the input sensor ISP and the position of the anti-reflection layer ARL are interchangeable. In an embodiment of the invention, the anti-reflection layer ARL may be substituted with a polarizing film. The polarizing film may be coupled to the input sensor ISP through an adhesive layer.

5 FIG.A 5 FIG.B 5 FIG.C 5 FIG.D 5 FIG.E 5 FIG.C 5 FIG.B 5 FIG.D 5 FIG.C is a cross-sectional view of a display device according to an embodiment of the invention.is a perspective view of a support plate according to an embodiment of the invention.is an enlarged plan view of a portion of a support plate according to an embodiment of the invention.is a cross-sectional view of a portion of a support plate according to an embodiment of the invention.is an enlarged plan view of a portion of a support plate according to an embodiment of the invention.illustrates a plane corresponding to region A′ of.illustrates a cross-section taken along line I-I′ of.

5 FIG.A 5 FIG.A 3 FIG. illustrates an embodiment of the display module DM in an unfolded state in which the display module DM is not folded. In, regions dividing the display module DM are illustrated with respect to the display panel DP of.

5 FIG.A Referring to, an embodiment of a display device DD includes a window WM, an upper member UM, a display module DM, and a lower member LM. The upper member UM collectively refers to components disposed between the window WM and the display module DM, and the lower member LM collectively refers to components disposed on a lower side of the display module DM.

1 The window WM may include a thin-film glass substrate UTG, a thin-film window protection layer PF disposed on the thin-film glass substrate UTG, and a bezel pattern BP disposed on a lower surface of the window protection layer PF. In an embodiment, the window protection layer PF may include a synthetic resin film. The window WM may include an adhesive layer AL(hereinafter, a first adhesive layer) which couples the window protection layer PF and the thin-film glass substrate UTG to each other.

1 FIG.A 5 FIG.A The bezel pattern BP overlaps the non-display region NDA illustrated in. The bezel pattern BP may be disposed on one surface of the thin-film glass substrate UTG or on one surface of the window protection layer PF.exemplarily illustrates an embodiment where the bezel pattern BP is disposed on a lower surface of the window protection layer PF. However, the embodiment of the invention is not limited thereto, and alternatively, the bezel pattern BP may be disposed on an upper surface of the window protection layer PF. The bezel pattern BP is a colored light blocking film, and may be formed, for example, by a coating method. The bezel pattern BP may include a base material and a dye or a pigment mixed in the base material.

The thickness of the thin-film glass substrate UTG may be in a range of approximately 15 micrometers (μm) to approximately 45 μm. The thin-film glass substrate UTG may be a chemically reinforced glass. The thin-film glass substrate UTG may minimize the occurrence of wrinkles even when folding and unfolding are repeated.

The thickness of the window protection layer PF may be in a range of approximately 50 μm to approximately 80 μm. The synthetic resin film of the window protection layer PF may include polyimide, polycarbonate, polyamide, triacetylcellulose, or polymethylmethacrylate, or polyethylene terephthalate. Although not separately illustrated, at least one selected from a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer may be disposed on the upper surface of the window protection layer PF.

1 1 The first adhesive layer ALmay be a pressure sensitive adhesive (PSA) film or an optically clear adhesive (OCA) member. Adhesive layers to be described below may also include a same adhesive as that of the first adhesive layer AL.

1 1 In an embodiment, the first adhesive layer ALmay be separated or separable from the thin-film glass substrate UTG to be replaced. Since the strength of the window protection layer PF is lower than that of the thin-film glass substrate UTG, scratches may occur relatively easily in the window protection layer PF. In such an embodiment, after the first adhesive layer ALand the window protection layer PF are separated, a new window protection layer PF may be attached to the thin-film glass substrate UTG.

The upper member UM includes an upper film DPL. The upper film DPL may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetylcellulose, or polymethylmethacrylate, or polyethylene terephthalate.

4 FIG. 2 3 The upper film DPL may absorb an external impact applied to the front surface of the display device DD. The display module DM described with reference tomay include the anti-reflection layer ARL which replaces a polarizing film, and due to the anti-reflection layer ARL, the front-surface impact strength (resistance) of the display device DD may be reduced. The upper film DPL may compensate for reduced impact strength by applying the anti-reflection layer ARL. In an alternative embodiment of the invention, the upper film DPL may be omitted. The upper member UM may include a second adhesive layer ALwhich couples the upper film DPL and the window WM to each other, and a third adhesive layer ALwhich couples the upper film DPL and the display module DM to each other.

4 8 The lower member LM may include a panel protection layer PPL, a barrier layer BRL, a support plate PLT, a cover layer SCV, and a digitizer DTM, and fourth to eighth adhesive layers ALto AL. In an embodiment of the invention, at least one selected from the above-described components may be omitted. In an embodiment, for example, the barrier layer BRL, the cover layer SCV, or the digitizer DTM, and an adhesive layer related thereto may be omitted.

The panel protection layer PPL may be the disposed on a lower side of the display module DM. The panel protection layer PPL may protect a lower portion of the display module DM. The panel protection layer PPL may include a flexible synthetic resin film. In an embodiment, for example, the panel protection layer PPL may include polyethylene terephthalate.

1 1 2 2 3 FIG.A In an embodiment of the invention, the panel protection layer PPL may not be disposed in the bending region BA. The panel protection layer PPL may include a first panel protection layer PPL-for protecting the first region AAof the display panel DP (see) and a second panel protection layer PPL-for protecting the second region AAthereof.

4 4 4 1 1 4 2 2 The fourth adhesive layer ALcouples the panel protection layer PPL and the display panel DP to each other. The fourth adhesive layer ALmay include a first portion AL-corresponding to the first panel protection layer PPL-and a second portion AL-corresponding to the second panel protection layer PPL-.

2 2 1 1 Although not illustrated, when the bending region BA is bent, the second panel protection layer PPL-may be disposed together with the second region AAon lower portions of the first region AAand the first panel protection layer PPL-. Since the panel protection layer PPL is not disposed in the bending region BA, the bending region BA may be more easily bent.

5 FIG.A 5 As illustrated in, the fifth adhesive layer ALcouples the panel protection layer PPL and the barrier layer BRL to each other. The barrier layer BRL may be disposed on a lower side of the panel protection layer PPL. The barrier layer BTU, may increase resistance against compressive force caused by external pressing. Therefore, the barrier layer BRL may serve to prevent the deformation of the display panel DP. The barrier layer BRL may include a flexible plastic material such as polyimide or polyethylene terephthalate. In addition, the barrier layer BRL may be a colored film with low light transmittance. The barrier layer BRL may absorb light incident from the outside. In an embodiment, for example, the barrier layer BRL may a black synthetic resin film. When the display device DD is viewed from an upper side of the window protection layer PF, elements disposed on a lower side of the barrier layer BRL may not be visually recognized by a user.

6 6 6 1 6 2 6 6 1 6 2 0 The sixth adhesive layer ALcouples the barrier layer BRL and the support plate PLT to each other. The sixth adhesive layer ALmay include a first portion AL-and a second portion AL-spaced apart from each other. A separation distance D(or a gap) between the first portion AL-and the second portion AL-corresponds to the width of the folding region FA, and is greater than a gap GP in the digitizer DTM to be described later.

The support plate PLT is disposed on a lower side of the barrier layer BRL. The support plate PLT supports components disposed on an upper side thereof, and maintains an unfolded state and a folded state of the display device DD. The support plate PLT has greater strength than the barrier layer BRL.

The support plate PLT may include a metal material which has high strength. The support plate PLT may include a material having an elastic modulus of about 60 gigapascals (GPa) or greater. The support plate PLT may include a metal material such as stainless steel.

The support plate PLT may include a reinforced fiber composite material. The support plate PLT may include a reinforced fiber disposed on the inner side of a matrix portion. The reinforced fiber may be a carbon fiber or glass fiber. The matrix portion may include a polymer resin. The matrix portion may include a thermoplastic resin. In an embodiment, for example, the matrix portion may include a polyamide-based resin or polypropylene-based resin. In an embodiment, for example, the reinforced fiber composite material may be carbon fiber reinforced plastic (CFRP) or glass fiber reinforced plastic (GFRP).

5 FIG.A 5 FIG.D 1 10 2 20 0 1 2 1 2 Referring toto, the support plate PLT includes at least a first support portion PLT-corresponding to the first non-folding region NFAand a second support portion PLT-corresponding to the second non-folding region NFA. The support plate PLT may include a folding portion PLT-F which corresponds to the folding region FA, and the folding portion PLT-F is disposed between the first support portion PLT-and the second support portion PLT-, with a plurality of openings OP defined therein. The first support portion PLT-, the second support portion PLT-, and the folding portion PLT-F may have a shape of a single body or be integrally formed as a single unitary and indivisible part.

1 2 1 2 3 1 1 2 2 3 3 1 2 1 2 3 FIG. In each of the first support portion PLT-and the second support portion PLT-, a first region PLAand a second region PLAmay be defined. In the folding portion PLT-F, a third region PLAmay be defined. The first region PLAmay be a region corresponding to the first display region DAin the display region DP-DA of the display panel DP described above with reference to. The second region PLAmay be a region corresponding to the second display region DAin the display region DP-DA of the display panel DP. The third region PLAmay be a region corresponding to the third display region DAin the display region DP-DA of the display panel DP. The first region PLAand the second region PLAmay have a plate shape having a shape of a single body. The first region PLAand the second region PLAmay provide a flat support surface of a single body.

1 FIG.A 1 FIG.C 1 2 1 2 1 2 As described with reference toto, as the electronic device ED changes from the first mode to the second mode, the shape of the folding portion PLT-F changes, but the shapes of the first support portion PLT-and the second support portion PLT-do not change. Each of the first support portion PLT-and the second support portion PLT-provides a flat support surface regardless of an operation mode. The first support portion PLT-and the second support portion PLT-may be defined as a first region whose shape is not changed according to the change of an operation mode of the electronic device ED, and the folding portion PLT-F may be defined as a second region whose shape is changed according to the change of an operation mode of the electronic device ED.

5 FIG.C 1 FIG.B 1 FIG.C 1 2 As illustrated in, the plurality of openings OP may be defined in a way such that the folding portion PLT-F has a grid shape on a plane. The flexibility of the folding portion PLT-F is improved due to the plurality of openings OP. During the folding operation illustrated inand, the folding portion PLT-F may prevent foreign substances from penetrating into an open central region of the barrier layer BRL from the first support portion PLT-and the second support portion PLT-. The flexibility of the folding portion PLT-F is improved due to the plurality of openings OP.

5 FIG.C 1 2 2 2 As illustrated in, the plurality of openings OP may be defined in the folding portion PLT-F. A region excluding the plurality of openings OP is defined as a support region. The support region may include first extension portions F-C and second extension portions F-L. In the disclosure, the first extension portions F-C and the second extension portions F-L are collectively referred to as a “support portion.” Each of the first extension portions F-C extends in the first direction DR, and the first extension portions F-C are arranged in the second direction DR. Each of the second extension portions F-L extends in the second direction DR, and is disposed between adjacent first extension portions F-C. The first extension portions F-C and the second extension portions F-L may define a grid shape. The first extension portions F-C may be positioned in a way such that the plurality of openings OP may be disposed in a zig-zag shape along the second direction DR.

5 FIG.D 3 As illustrated in, the plurality of openings OP may each have a uniform width. The width of each of the plurality of openings OP is not changed in the third direction DR, and may have a uniform value.

5 FIG.E 1 1 2 2 Referring to, in an alternative embodiment, the second extension portions F-L may be omitted. In such an embodiment, each of the first extension portions F-C may correspond to a stick member extending in the first direction DR. In such an embodiment, stick members may be arranged between the first support portion PLT-and the second support portion PLT-along the second direction DRat uniform intervals.

5 FIG.B 1 1 2 With reference to, the length of the stick members in the first direction DRmay be the same as the length of the first support portion PLT-or the second support portion PLT-. Regions between the stick members may correspond to the above-described openings OP.

5 FIG.A 0 1 2 1 2 1 2 Referring back to, the cover layer SCV and the digitizer DTM are disposed on a lower side of the support plate PLT. The cover layer SCV is disposed to overlap the folding region FA. The digitizer DTM may include a first digitizer DTM-and a second digitizer DTM-which respectively overlap the first support portion PLT-and the second support portion PLT-. A portion of each of the first digitizer DTM-and the second digitizer DTM-may be disposed on (or to overlap) a lower side of the cover layer SCV.

7 8 7 17 1 1 1 7 2 2 2 The seventh adhesive layer ALcouples the support plate PLT and the digitizer DTM to each other, and the eighth adhesive layer ALcouples the cover layer SCV and support plate PLT to each other. The seventh adhesive layer ALmay include a first portion A-, which couples the first support portion PLT-and the first digitizer DTM-to each other, and a second portion AL-, which couples the second support portion PLT-and the second digitizer DTM-to each other.

7 1 7 2 7 2 8 7 The cover layer SCV may be disposed between the first portion AL-and the second portion AL-of the seventh adhesive layer ALin the second direction DR. The cover layer SCV may be spaced apart from the digitizer DTM to prevent interference with respect to the digitizer DTM in an unfolded state. The sum of the thickness of the cover layer SCV and the thickness of the eighth adhesive layer ALmay be less than the thickness of the seventh adhesive layer AL.

The cover layer SCV may cover the openings OP of the folding portion PLT-F. The cover layer SCV may have a lower elastic modulus than the support plate PLT. In an embodiment, for example, the cover layer SCV may include at least one selected from thermoplastic polyurethane, rubber, and silicon, but the embodiment of the invention is not limited thereto.

The digitizer DTM is also referred to as an electromagnetic radiation (EMR) sensing panel, and includes a plurality of loop coils which generate a magnetic field of a preset resonant frequency with an electronic pen. The magnetic field formed in the loop coil is applied to an LC resonance circuit including an inductor (coil) and a capacitor of the electronic pen. The coil generates a current by the received magnetic field, and transfers the generated current to the capacitor. Accordingly, the capacitor charges the current input from the coil and discharges the charged current to the coil. As a result, a magnetic field of the resonant frequency is emitted to the coil. The magnetic field emitted by the electronic pen may be absorbed again by the loop coil of the digitizer DTM, and accordingly, it is possible to determine to which position the electronic pen is in proximity in a touch screen.

1 2 0 The first digitizer DTM-and the second digitizer DTM-are disposed spaced apart with the predetermined gap GP interposed therebetween. The gap GP may be in a range of approximately 0.3 millimeter (mm) to approximately 3 mm, and may be disposed to correspond to the folding region FA.

6 FIG.A 6 FIG.B is an equivalent circuit diagram of a pixel according to an embodiment of the invention.is a signal timing diagram illustrating a driving method of a pixel according to an embodiment of the invention.

6 FIG.A exemplarily illustrates a pixel PXij connected to an i-th scan line SLi of a first group, and connected to a j-th data line DLj. The pixel PXij may include the pixel driving circuit PC (hereinafter, a pixel circuit) and a light emitting element LD.

1 7 1 2 5 7 3 4 1 7 1 7 6 FIG.A In an embodiment, the pixel circuit PC may include first to seventh transistors Tto Tand a capacitor Cst. In such an embodiment, as shown in, the first transistor T, the second transistor T, and the fifth transistor Tto the seventh transistor Tmay be P-type transistors, and the third transistor Tand the fourth transistor Tmay be N-type transistors. However, the embodiment of the invention is not limited thereto. Alternatively, the first to seventh transistors Tto Tmay be implemented as either P-type transistors or N-type transistors. Herein, an input region (or input electrode) of an N-type transistor is described as a drain (or drain region), and an input region of a P-type transistor is described as a source (or source region), an output region (or output electrode) of the N-type transistor is described as the source (or source region), and an output region of the P-type transistor is described as the drain (or drain region). Also, in an embodiment of the invention, at least one selected from the first to seventh transistors Tto Tmay be omitted.

1 2 10 20 In an embodiment, the first transistor Tmay be a driving transistor, and the second transistor Tmay be a switching transistor. The capacitor Cst is electrically connected between the power line PL that receives a first power voltage ELVDD and a reference node RN. The capacitor Cst includes a first electrode CEelectrically connected to the reference node RN, and a second electrode CEelectrically connected to the power line PL.

1 The light emitting element LD is electrically connected between the first transistor Tand a signal line SL. The signal line SL may provide a second power voltage ELVSS, or provide a driving signal TDS to a cathode of the light emitting element LD. The second power voltage ELVSS has a lower level than the first power voltage ELVDD.

1 1 1 1 1 The first transistor Tis electrically connected between the power line PL and an anode of the light emitting element LD. A source Sof the first transistor Tis electrically connected to the power line PL. In the disclosure, “being electrically connected between a transistor and a signal line or between a transistor and a transistor” means that “a source, a drain, and a gate of the transistor have a shape of a single body with the signal line, or are connected through a connection electrode.” Between the source Sof the first transistor Tand the power line PL, another transistor may be provided or may be not provided.

1 1 1 1 1 1 A drain Dof the first transistor Tis electrically connected to the anode of the light emitting element LD. Between the drain Dof the first transistor Tand the anode of the light emitting element LD, another transistor may be provided or may not be provided. A gate Gof the first transistor Tis electrically connected to the reference node RN.

2 1 1 2 2 2 2 1 1 2 2 The second transistor Tis electrically connected between the j-th data line DLj and the source Sof the first transistor T. A source Sof the second transistor Tis electrically connected to the j-th data line DLj, and a drain Dof the second transistor Tis electrically connected to the source Sof the first transistor T. In the embodiment, a gate Gof the second transistor Tmay be electrically connected to the i-th scan line SLi of the first group.

3 1 1 3 3 1 1 3 3 3 3 3 3 4 1 4 4 4 4 1 4 4 4 4 6 FIG.A 6 FIG.A The third transistor Tis electrically connected between the reference node RN and the drain Dof the first transistor T. A drain Dof the third transistor Tis electrically connected to the drain Dof the first transistor T, and a source Sof the third transistor Tis electrically connected to the reference node RN. Although the third transistor Thaving a single gate structure is illustrated in, the third transistor Tmay include a plurality of gates. In an embodiment, a gate Gof the third transistor Tmay be electrically connected to an i-th scan line GLi of a second group. The fourth transistor Tis electrically connected between the reference node RN and a first voltage line VL. A drain Dof the fourth transistor Tis electrically connected to the reference node RN, and a source Sof the fourth transistor Tis electrically connected to the first voltage line VL. Although the fourth transistor Thaving a single gate structure is illustrated in, the fourth transistor Tmay include a plurality of gates. In an embodiment, a gate Gof the fourth transistor Tmay be electrically connected to an i-th scan line HLi of a third group.

5 1 1 5 5 5 5 1 1 5 5 The fifth transistor Tis electrically connected between the power line PL and the source Sof the first transistor T. A source Sof the fifth transistor Tis electrically connected to the power line PL, and a drain Dof the fifth transistor Tis electrically connected to the source Sof the first transistor T. A gate Gof the fifth transistor Tmay be electrically connected to an i-th light emission line ELi.

6 1 1 6 6 1 1 6 6 6 6 6 6 5 5 The sixth transistor Tis electrically connected between the drain Dof the first transistor Tand the light emitting element LD. A source Sof the sixth transistor Tis electrically connected to the drain Dof the first transistor T, and a drain Dof the sixth transistor Tis electrically connected to the anode of the light emitting element LD. A gate Gof the sixth transistor Tmay be electrically connected to the i-th light emission line ELi. In an embodiment of the invention, the gate Gof the sixth transistor Tmay be connected to a different signal from the signal line to which the gate Gof the fifth transistor Tis connected.

7 6 6 2 7 7 6 6 7 7 2 7 7 The seventh transistor Tis electrically connected between the drain Dof the sixth transistor Tand a second voltage line VL. A source Sof the seventh transistor Tis electrically connected to the drain Dof the sixth transistor T, and a drain Dof the seventh transistor Tis electrically connected to the second voltage line VL. A gate Gof the seventh transistor Tmay be electrically connected to an (i+1)-th scan line SLi+1 of the first group.

6 FIG.B 6 FIG.B 6 FIG.B 1 7 Referring to, the operation of the pixel PXij will be described in more detail. Referring to, each of signals Ei, Gli, GWi, GCi, and GWi+1 may have a high level V-HIGH during some intervals and may have a low level V-LOW during some intervals. In, the signals Ei, Gli, GWi, GCi, and GWi+1 are illustrated as having a same pulse width as each other, but the embodiment of the invention is not limited thereto. The pulse width of the signals Ei, Gli, GWi, GCi, and GWi+1 may be determined in consideration of a desired turn-on interval of the first to seventh transistors Tto T. N-type transistors are turned on when a corresponding signal has the high level V-HIGH, and P-type transistors are turned on when a corresponding signal has the low level V-LOW.

5 6 5 6 When a light emission control signal EMi has the high level V-HIGH, the fifth transistor Tand the sixth transistor Tare turned off. When the fifth transistor Tand the sixth transistor Tare turned off, a current path is not formed between the power line PL and the light emitting element LD. Therefore, a corresponding interval during which the light emission control signal EMi has the high level V-HIGH may be defined as a non-light emitting interval.

4 4 When a scan signal Gli applied to the i-th scan line HLi of the third group has the high level V-HIGH, the fourth transistor Tis turned on. When the fourth transistor Tis turned on, the reference node RN is initialized by a first initialization voltage Vint.

2 3 When a scan signal GWi applied to the i-th scan line SLi of the first group has the low level V-LOW, and a scan signal GCi applied to the i-th scan line GLi of the second group has the high level V-HIGH, the second transistor Tand the third transistor Tare turned on.

1 1 1 6 FIG.A Accordingly, the reference node RN is initialized by the initialization voltage Vint, and the first transistor Tis in the state of being turned on. When the first transistor Tis turned on, a voltage corresponding to a data signal Dj (see) is provided to the reference node RN. At this time, the capacitor Cst stores the voltage corresponding to the data signal Dj. The voltage corresponding to the data signal Dj may be a voltage reduced by a threshold voltage Vth of the first transistor Tfrom the data signal Dj.

7 7 When a scan signal GWPi+1 applied to the (i+1)-th scan line SLi+1 of the first group has the low level V-LOW, the seventh transistor Tis turned on. As the seventh transistor Tis turned on, the anode of the light emitting element LD is initialized by a second initialization voltage VAint. A parasitic capacitor of the light emitting element LD may be discharged.

5 6 5 1 6 1 When the light emission control signal EMi has the low level V-LOW, the fifth transistor Tand the sixth transistor Tare turned on. When the fifth transistor Tis turned on, the first power voltage ELVDD is provided to the first transistor T. When the sixth transistor Tis turned on, the first transistor Tand the light emitting element LD are electrically connected to each other. The light emitting element LD generates light of luminance in correspondence to the amount of a current provided thereto.

7 FIG.A 7 FIG.B 7 FIG.C 7 FIG.D 1 2 3 3 is an enlarged plan view of portion AA of the first display region DAaccording to an embodiment of the invention.is an enlarged plan view of portion BB of the second display region DAaccording to an embodiment of the invention.is an enlarged plan view of portion CC of the third display region DAaccording to an embodiment of the invention.is a plan view illustrating the third display region DAaccording to an embodiment of the invention overlapping the support plate PLT.

3 FIG. The resolution of a display device is determined by the number of pixels disposed in a reference region (or a unit area), and may be measured, for example, in pixels per inch (PPI). Typically, the resolution of a light emitting element and the resolution of a pixel circuit are the same as the resolution of a pixel. This is because each pixel includes a light emitting element and a pixel circuit connected to the light emitting element in a 1-to-1 manner, and the light emitting element and the pixel circuit are uniformly disposed throughout the display region DP-DA (see). However, in the display device according to an embodiment of the invention, the arrangement of pixel circuits is not uniform in some regions, and may be divided into a portion having a high arrangement density and a portion having a low arrangement density in some regions. Hereinafter, the arrangement of the pixel circuits will be described in greater detail.

7 FIG.A 7 FIG.C 7 FIG.A 7 FIG.C 1 2 3 1 2 3 1 2 3 Referring toto, the first display region DA, the second display region DA, and the third display region DAmay each have a different pixel arrangement from each other. More specifically, the first display region DA, the second display region DA, and the third display region DAmay each have a same arrangement of light emitting elements as each other, and the first display region DA, the second display region DA, and the third display region DAmay each have a different arrangement of pixel circuits from each other. Having the same arrangement of light emitting elements may mean that gaps between the light emitting elements are the same. In addition, it may mean that color arrangements of the light emitting elements are the same. Hereinafter, with reference toto, an embodiment of the invention will be described in greater detail.

7 FIG.A 7 FIG.A 5 FIG.B 1 5 1 5 5 5 5 5 5 1 1 Referring to, in the first display region DA, fifth pixels PXare provided. In the first display region DA, the fifth pixels PXare uniformly disposed. Each of the fifth pixels PXincludes a light emitting element LD(hereinafter, a fifth light emitting element) and a pixel circuit PC(hereinafter, a fifth pixel circuit) electrically connected thereto. The fifth light emitting elements LDmay include a red light emitting element, a green light emitting element, and a blue light emitting element. The red light emitting element, the green light emitting element, and the blue light emitting element having the same area are exemplarily illustrated, but the embodiment of the invention is not limited thereto. In addition, in, an anode is illustrated as a representative of the red light emitting element, the green light emitting element, and the blue light emitting element. The fifth pixel circuit PCcorresponding to the anode may be connected thereto through a contact-hole. A detailed description thereof will be followed. The anode in a circular shape is exemplarily illustrated, but the shape of the anode is not particularly limited. In an embodiment, the first display region DAmay be a region overlapping the first region PLAof the support plate PLT illustrated in.

7 FIG.A 7 FIG.A 5 5 5 1 2 3 4 Referring to, two fifth pixel circuits PCare disposed adjacent to each other and form one pixel circuit. A plurality of pixel groups are disposed spaced apart from each other at regular intervals. However, the arrangement of the fifth pixel circuits PCillustrated inis just an example, and the embodiment of the invention is not limited thereto. The fifth pixel circuits PCmay be disposed spaced apart from each other at uniform intervals within pixel rows PXL, PXL, PXL, and PXL.

5 5 1 7 5 5 6 FIG.A 6 FIG.A 6 FIG.A The fifth pixel circuit PCmay have an equivalent circuit structure illustrated in. A region illustrated as the fifth pixel circuit PCinis a schematically illustrated region which is occupied by the first to seventh transistors Tto Tand the capacitor Cst illustrated in. The fifth pixel circuits PCare all illustrated the same, but the embodiment of the invention is not limited thereto. The fifth pixel circuit PCmay include a first-type pixel circuit and a second-type pixel circuit, which may be paired and repeatedly disposed.

1 2 3 4 1 2 2 2 2 4 2 A plurality of pixel rows PXL, PXL, PXL, and PXLmay be defined in the first display region DAL In each of a first pixel row PXLand a second pixel row PXL, green light emitting elements are arranged along the second direction DR, and in a second pixel row PXL, red light emitting elements and blue light emitting elements may be alternately arranged along the second direction DR. In a fourth pixel row PXL, blue light emitting elements and red light emitting elements may be alternately arranged along the second direction DR.

1 2 1 2 1 2 2 2 Although not separately illustrated, the first pixel row PXLand the second pixel row PXLmay include light emitting elements of a same arrangement as each other, that is, an arrangement of the light emitting elements in the first pixel row PXLis the same as an arrangement of the light emitting elements in the second pixel row PXL. Each of the first pixel row PXLand the second pixel row PXLmay include a plurality of pixel units arranged in the second direction DR. Each of the pixel units may include a red light emitting element, a green light emitting element, and a blue light emitting element arranged along the second direction DR. Each of the pixel units may further include a fourth color light emitting element which generates light of a different color from the red light emitting element, the green light emitting element, and the blue light emitting element.

7 FIG.B 5 FIG.B 5 FIG.B 2 1 2 1 2 2 2 2 1 2 2 2 1 2 2 1 2 Referring to, the second display region DAincludes a first partial region Pand a second partial region P. The first partial regions Pand the second partial regions Pmay be alternately arranged along the second direction DR. The second display region DAmay be a region overlapping the second region PLAof the support plate PLT illustrated in. Each of the first partial region Pand the second partial region Pincluded in the second display region DAmay overlap the second region PLA. That is, each of the first partial region Pand the second partial region Pincluded in the second display region DAmay overlap a flat surface defined by each of the first support portion PLT-and the second support portion PLT-of the support plate PLT illustrated in.

7 FIG.B 1 2 2 1 1 1 2 2 2 Referring to, first pixels PXand second pixels PXare disposed in the second display region DA. Each of the first pixels PXincludes a light emitting element LD(hereinafter, a first light emitting element) and a pixel circuit PC(hereinafter, a first pixel circuit) electrically connected thereto. Each of the second pixels PXincludes a light emitting element LD(hereinafter, a second light emitting element) and a pixel circuit PC(hereinafter, a second pixel circuit) electrically connected thereto.

1 2 5 5 1 1 2 2 5 1 1 5 1 2 1 2 The first pixel circuits PCand the second pixel circuits PCare arranged according to a different rule from the fifth pixel circuits PC. The arrangement of the pixel circuits PCof the first display region DAand the arrangement of the pixel circuits PCand PCof the second display region DAmay be different from each other. In such an embodiment, the resolution (or the pixel circuit density) of the pixel circuits PCof the first display region DAmay be different from the resolution of pixel circuits of the first partial region P, the resolution of the pixel circuits PCof the first display region DAmay be different from the resolution of pixel circuits of the second partial region P, and the resolution of the pixel circuits of the first partial region Pmay be different from the resolution of the pixel circuits of the second partial region P.

7 FIG.B 1 2 1 1 1 2 2 2 As illustrated in, the first pixel circuits PCand the second pixel circuits PCmay all be disposed in the first partial region P. The first light emitting element LDmay overlap the first pixel circuit PC, whereas the second light emitting element LDmay not overlap the second pixel circuit PC. In the second partial region P, a pixel circuit may not be disposed.

7 FIG.A 7 FIG.B 7 FIG.A 7 FIG.C 7 FIG.A 7 FIG.B 1 2 1 2 1 1 1 1 1 1 2 1 1 2 Referring toand, the resolution of a pixel of the first display region DAand the resolution of a pixel of the second display region DAare the same as each other, and the resolution of a light emitting element of the first display region DAand the resolution of a light emitting element of the second display region DAare the same as each other. The resolution of the pixel circuits of the first partial region Pis higher than the resolution of the pixel circuits of a corresponding region in the first display region DA. That is, pixel circuits are more densely disposed in the first partial region Pthan in the first display region DA. More specifically, the number of pixel circuits disposed per reference area in the first partial region Pmay be greater than the number of pixel circuits disposed per reference area in the first display region DA. Into, a reference area may be, for example, an area in a rectangular shape including two adjacent light emitting elements along the second direction DR. In an embodiment, as illustrated inand, two light emitting elements and two pixel circuits may be disposed per reference area in the first display region DA, two light emitting elements and four pixel circuits may be disposed per reference area in the first partial region P, and two light emitting elements may be disposed but no pixel circuit may be disposed in the second partial region P.

1 1 2 2 When the density of pixel circuits of the first display region DAis defined as a first pixel density, and the density of pixel circuits of the first partial region Pis defined as a second pixel density, the first pixel density may be less than the second pixel density. In the disclosure, the “density of pixel circuits or light emitting elements” may be defined through the number of pixel circuits or light emitting elements disposed per reference area. In an embodiment, since no pixel circuit is disposed in the second partial region P, a third pixel density, which is the density of pixel circuits of the second partial region P, may be less than the first pixel density and the second pixel density.

1 2 1 5 1 5 1 2 5 1 2 5 1 2 The resolution of the pixel circuits PCand PCof the first partial region Pmay be higher than the resolution of the pixel circuits PCof the first display region DA. However, an area occupied by one fifth pixel circuit PC, an area occupied by one first pixel circuit PC, and an area occupied by one second pixel circuit PCmay be substantially the same as each other. When pixel circuits have a same area as each other, it means that the pixel circuits have a same layout structure, and it means that transistors constituting a pixel circuit have a same size as each other and are arranged in a same arrangement rule as each other. In the disclosure, “substantially the same” means not only that numerical values such as an area are physically the same, but also means that the numerical values are in the same range considering differences within an error range that may occur in a process despite the same design. In an embodiment, since the fifth pixel circuit PC, the first pixel circuit PC, and the second pixel circuit PChave a same area as each other, it is possible to design a uniform circuit. Since noise factors, such as a peripheral signal and parasitic capacitance, which affect the operation of the fifth pixel circuit PC, the first pixel circuit PC, and the second pixel circuit PCmay be the same as each other, the control of a pixel circuit may be easy.

7 FIG.C 5 FIG.B 5 FIG.C 5 FIG.C 7 FIG.D 7 FIG.C 7 FIG.D 5 FIG.C 7 FIG.C 3 3 4 3 4 2 3 3 3 4 3 4 1 2 3 4 3 4 3 4 4 4 Referring to, the third display region DAincludes a third partial region Pand a fourth partial region P. The third partial regions Pand the fourth partial regions Pmay be alternately arranged along the second direction DR. The third display region DAmay be a region overlapping the third region PLAof the support plate PLT illustrated in. Herein, the third partial region Pmay be a region overlapping the first extension portion F-C of, and the fourth partial region Pmay be a region overlapping the opening OP of. In, light emitting elements LDand LDof the pixel rows PXL, PXL, PXL, and PXLofoverlapping the support plate PLT are illustrated.exemplarily illustrates an embodiment where the light emitting elements LDand LDare disposed only in some regions marked as CC, but third pixels PXand fourth pixels PXmay be disposed in other region according to a rule to be described later. The fourth partial region Poverlapping the opening OP ofhas low impact resistance, so that a circuit may be disconnected or short-circuited by an external impact. Referring to, a pixel circuit disposed in the fourth partial region Pmay be minimized to reduce defects of the pixel circuit.

3 4 3 3 3 3 4 4 4 In an embodiment, the third pixels PXand the fourth pixels PXare disposed in the third display region DA. Each of the third pixels PXincludes a light emitting element LD(hereinafter, a third light emitting element) and a pixel circuit PC(hereinafter, a third pixel circuit) electrically connected thereto. Each of the fourth pixels PXincludes a light emitting element LD(hereinafter, a fourth light emitting element) and a pixel circuit PC(hereinafter, a fourth pixel circuit) electrically connected thereto.

3 3 1 3 2 3 1 3 1 3 1 3 2 3 2 3 2 3 1 3 3 2 3 3 1 3 1 3 3 2 3 Each of the third pixels PXmay include first third pixels PX-and second third pixels PX-. Each of the first third pixels PX-may include a first third light emitting element LD-and a first third pixel circuit PC-electrically connected thereto. Each of the second third pixels PX-may include a second third light emitting element LD-and a second third pixel circuit PC-electrically connected thereto. The first third pixel circuit PC-may be disposed in a central portion of the third partial region P, and the second third pixel circuit PC-may be disposed spaced apart from the center of the third partial region Pcompared to the first third pixel circuit PC-. The first third light emitting element LD-may be disposed in a central portion of the third partial region P, and the second third light emitting element LD-may be disposed at the outer periphery of the third partial region P.

4 4 1 4 2 4 1 4 1 4 1 4 2 4 2 4 2 4 1 3 2 4 2 3 4 1 4 4 2 4 Each of the fourth pixels PXmay include first fourth pixels PX-and second fourth pixels PX-. Each of the first fourth pixels PX-may include a first fourth light emitting element LD-and a first fourth pixel circuit PC-electrically connected thereto. Each of the second fourth pixels PX-may include a second fourth light emitting element LD-and a second fourth pixel circuit PC-electrically connected thereto. The first fourth pixel circuit PC-may be disposed adjacent to the second third pixel circuit PC-, and the second fourth pixel circuit PC-may be disposed at the outermost periphery of the third partial region P. The first fourth light emitting element LD-may be disposed at the outer periphery of the fourth partial region P, and the second fourth light emitting element LD-may be disposed in a central portion of the fourth partial region P.

3 4 5 5 1 3 4 3 5 1 3 5 1 4 3 4 The third pixel circuits PCand the fourth pixel circuits PCare arranged according to a different rule from the fifth pixel circuits PC. The arrangement of the pixel circuits PCof the first display region DAand the arrangement of the pixel circuits PCand PCof the third display region DAmay be different from each other. In an embodiment, the resolution (or the pixel circuit density) of the pixel circuits PCof the first display region DAmay be different from the resolution of pixel circuits of the third partial region P, the resolution of the pixel circuits PCof the first display region DAmay be different from the resolution of pixel circuits of the fourth partial region P, and the resolution of the pixel circuits of the third partial region Pmay be different from the resolution of the pixel circuits of the fourth partial region P.

7 FIG.C 3 4 3 3 3 4 4 4 As illustrated in, the third pixel circuits PCand the fourth pixel circuits PCmay all be disposed in the third partial region P. The third light emitting element LDmay overlap the third pixel circuit PCand the fourth pixel circuit PC, whereas the fourth light emitting element LDmay not overlap pixel circuits. In the fourth partial region P, a pixel circuit may not be disposed.

7 FIG.A 7 FIG.C 7 FIG.A 7 FIG.C 7 FIG.A 7 FIG.C 1 3 1 3 3 1 3 1 3 1 2 1 3 4 Referring toand, the resolution of a pixel of the first display region DAand the resolution of a pixel of the third display region DAare the same as each other, and the resolution of a light emitting element of the first display region DAand the resolution of a light emitting element of the third display region DAare the same as each other. The resolution of the pixel circuits of the third partial region Pis higher than the resolution of the pixel circuits of the first display region DA. That is, pixel circuits are more densely disposed in the third partial region Pthan in the first display region DA. In such an embodiment, the number of pixel circuits disposed per reference area in the third partial region Pmay be greater than the number of pixel circuits disposed per reference area in the first display region DA. Into, a reference area may be, for example, an area in a rectangular shape including two adjacent light emitting elements along the second direction DR. In an embodiment, as illustrated inand, two light emitting elements and two pixel circuits may be disposed per reference area in the first display region DA, two light emitting elements and four pixel circuits may be disposed per reference area in the third partial region P, and two light emitting elements may be disposed but no pixel circuit may be disposed in the fourth partial region P.

1 3 4 4 When the density of pixel circuits of the first display region DAis defined as a first pixel density, and the density of pixel circuits of the third partial region Pis defined as a fourth pixel density, the first pixel density may be less than the fourth pixel density. In such an embodiment, since no pixel circuit is disposed in the fourth partial region P, a fifth pixel density, which is the density of pixel circuits of the fourth partial region P, may be less than the first pixel density and the fourth pixel density.

3 4 3 5 1 5 3 4 1 5 1 5 1 5 The resolution of the pixel circuits PCand PCof the third partial region Pis higher than the resolution of the pixel circuits PCof the first display region DA. In an embodiment, an area occupied by one fifth pixel circuit PC, an area occupied by one third pixel circuit PC, and an area occupied by one fourth pixel circuit PCmay be substantially the same as each other. In an embodiment, areas respectively occupied by the first pixel circuit PCto the fifth pixel circuit PCmay be substantially the same as each other. Since the first pixel circuit PCto the fifth pixel circuit PCeach have a same area as each other, it is possible to design a uniform circuit. Since noise factors, such as a peripheral signal and parasitic capacitance, which affect the operation of the first pixel circuit PCto the fifth pixel circuit PCmay be the same as each other, the control of a pixel circuit may be easy.

3 4 2 1 2 2 3 4 2 1 2 2 3 4 2 1 2 2 In an embodiment, the width of each of the third partial region Pand the fourth partial region Pin the second direction DRmay be greater than the width of each of the first partial region Pand the second partial region Pin the second direction DR. In an embodiment, the width of each of the third partial region Pand the fourth partial region Pin the second direction DRmay be twice the width of each of the first partial region Pand the second partial region Pin the second direction DR. In an embodiment the width of each of the third partial region Pand the fourth partial region Pin the second direction DRmay be substantially the same as the sum of the widths of the first partial region Pand the second partial region Pin the second direction DR.

1 2 3 1 2 3 1 2 3 In an embodiment, the resolution of a light emitting element in each of the first display region DA, the second display region DA, and the third display region DAmay be the same as each other. That is, the number of light emitting elements disposed per reference area in each of the first display region DA, the second display region DA, and the third display region DAmay be the same as each other. The density of light emitting elements in each of the first display region DA, the second display region DA, and the third display region DAmay be the same.

7 FIG.C 5 FIG.C 5 FIG.C 7 FIG.A 3 3 3 4 1 3 3 3 4 4 4 3 In, a portion in which the third display region DAoverlaps the second extension portion F-L ofis not shown. In the third display region DA, a region overlapping the second extension portion F-L ofmay have a same pixel structure as the pixel structure of the third partial region P, may have a same pixel structure as the pixel structure of the fourth partial region P, or may have a same pixel structure as the pixel structure of the first display region DAillustrated in, but the embodiment of the invention is not limited thereto. In an embodiment, for example, the region overlapping the second extension portion F-L may have the same structure as the structure of the third partial region P, and the third pixel circuit PCand the third light emitting element LDwhich are disposed in the region overlapping the second extension portion F-L may be electrically connected. Alternatively, the region overlapping the second extension portion F-L may have a same structure as the structure of the fourth partial region P, and the fourth light emitting element LDdisposed in the region overlapping the second extension portion F-L may be electrically connected to the fourth pixel circuit PCdisposed in the third partial region P.

7 FIG.B 7 FIG.C 7 FIG.C 2 1 2 2 1 4 3 4 4 2 1 2 2 4 2 4 2 4 2 4 4 1 4 4 1 4 1 1 1 2 2 Referring toand, when a separation distance between the second pixel circuit PCdisposed in the first partial region Pand the second light emitting element LDdisposed in the second partial region Pis defined as a first separation distance sd, and when a separation distance between the fourth pixel circuit PCdisposed in the third partial region Pand the fourth light emitting element LDdisposed in the fourth partial region Pis defined as a second separation distance sd, the first separation distance sdmay be less than the second separation distance sd. In an embodiment, the second separation distance sdmay be defined as a separation distance between the second fourth light emitting element LD-and the second fourth pixel circuit PC-in the second fourth pixel PX-among the pixels included in the fourth pixel PX. In an embodiment, although not shown in, in the first fourth pixel PX-among the pixels included in the fourth pixel PX, a separation distance between the first fourth light emitting element LD-and the first fourth pixel circuit PC-may also be greater than the first separation distance sd. In the disclosure, the “separation distance” such as the first separation distance sdand the second separation distance sdmay be defined as a distance at which a central portion of a pixel circuit is spaced apart from a central portion of a light emitting element connected thereto along the second direction DR.

8 FIG.A 8 FIG.B 8 FIG.C 8 FIG.D 1 2 3 is a cross-sectional view of the first display region DAaccording to an embodiment of the invention.andare cross-sectional views of the second display region DAaccording to an embodiment of the invention.is a cross-sectional view of the third display region DAaccording to an embodiment of the invention.

8 FIG.A 7 FIG.A 6 FIG.A 8 FIG.B 8 FIG.C 8 FIG.B 6 FIG.A 5 5 3 4 1 1 1 2 6 In, the fifth light emitting element LDdescribed with reference toand a silicon transistor S-TFT and an oxide transistor O-TFT of the fifth pixel circuit PCare illustrated. In the equivalent circuit illustrated in, the third and fourth transistors Tand Tmay be oxide transistors O-TFT, and the rest of the transistors may be silicon transistors S-TFT. Inand, a portion of the first light emitting element LDand a portion the first pixel circuit PCare illustrated, and a portion of the second light emitting element LDand a portion of the second pixel circuit PCare illustrated. A silicon transistor S-TFT illustrated inmay be the sixth transistor Tillustrated in.

8 FIG.A 10 110 10 10 10 br br br br Referring to, a barrier layermay be disposed on a base layer. The barrier layerprevents foreign substances from being introduced from the outside. The barrier layermay include at least one inorganic layer. The barrier layermay include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and silicon oxide layers and silicon nitride layers may be alternately laminated.

10 br In an embodiment, a first shielding electrode BMLa may be disposed on the barrier layer. The first shielding electrode BMLa may include a metal. The first shielding electrode BMLa may include molybdenum (Mo) with high heat resistance, an alloy containing molybdenum, titanium (Ti), or an alloy containing titanium. The first shielding electrode BMLa may receive a bias voltage. The first shielding electrode BMLa may receive the first power voltage ELVDD. The first shielding electrode BMLa may prevent an electrical potential due to polarization from affecting the silicon transistor S-TFT. The first shielding electrode BMLa may stop external light from reaching the silicon transistor S-TFT. In an embodiment of the invention, the first shielding electrode BMLa may be a floating electrode in an isolated form from another electrode or line.

10 10 10 110 1 10 10 bf br bf bf bf A buffer layermay be disposed on the barrier layer. The buffer layermay prevent a phenomenon in which metal atoms or impurities from the base layerdiffuse into a first semiconductor pattern SCon an upper side. The buffer layermay include at least one inorganic layer. The buffer layermay include a silicon oxide layer and a silicon nitride layer.

1 10 1 1 bf In an embodiment, the first semiconductor pattern SCmay be disposed on the buffer layer. The first semiconductor pattern SCmay include a silicon semiconductor. In an embodiment, for example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. In an embodiment, for example, the first semiconductor pattern SCmay include low-temperature polysilicon.

8 FIG.A 1 1 1 1 1 illustrates only a portion of the first semiconductor pattern SC, and the first semiconductor pattern SCmay be further disposed in other regions. The first semiconductor pattern SCmay be arranged across pixels according to a specific rule. The first semiconductor pattern SCmay have different electrical properties depending on whether or not being doped. The first semiconductor pattern SCmay include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region which has been doped with the P-type dopant, and an N-type transistor may include a doped region which has been doped with the N-type dopant. The second region may be a non-doped region, or a region doped to a concentration lower than that of the first region.

1 The conductivity of the first region may be greater than the conductivity of the second region, and the first region may substantially serve as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. In an embodiment, a portion of the first semiconductor pattern SCmay be a channel of a transistor, and another portion thereof may be a source or a drain of the transistor, and the other portion thereof may be a connection electrode or a connection signal line.

1 1 1 1 1 1 1 A source region SE, a channel region AC(or an active region), and a drain region DEof the silicon transistor S-TFT may be formed from (or defined by portions of) the first semiconductor pattern SC. The source region SEand the drain region DEmay extend in opposite directions from the channel region ACon a cross section.

10 10 10 1 10 10 10 120 bf In an embodiment, a first insulation layermay be disposed on the buffer layer. The first insulation layermay cover the first semiconductor pattern SC. The first insulation layermay be an inorganic layer. The first insulation layermay be a single-layered silicon oxide layer. The first insulation layermay have a multi-layered structure as well as a single-layer structure. An inorganic layer of a circuit layerto be described later may have a single-layered or multi-layered structure, and may include at least one selected from the above-described materials, but the embodiment of the invention is not limited thereto.

1 10 1 1 1 1 1 10 10 10 1 1 In an embodiment, a gate GTof the silicon transistor S-TFT is disposed on the first insulation layer. The gate GTmay be a portion of a metal pattern. The gate GToverlaps the channel region AC. In a process of doping the first semiconductor pattern SC, the gate GTmay be a mask. On the first insulation layer, a first electrode CEof a storage capacitor Cst is disposed. Alternatively, the first electrode CEmay have a shape of a single body with the gate GT, that is, may be integrally formed with the gate GTas a single unitary and indivisible part.

20 10 1 1 20 20 10 20 In an embodiment, a second insulation layeris disposed on the first insulation layerto cover the gate GT. Although not illustrated, an upper electrode overlapping the gate GTmay be disposed on the second insulation layer. In such an embodiment, a second electrode CEoverlapping the first electrode CEmay be disposed on the second insulation layer.

20 In an embodiment, a second shielding electrode BMLb is disposed on the second insulation layer. The second shielding electrode BMLb may be disposed corresponding to a lower portion of the oxide transistor O-TFT. In an alternative embodiment of the invention, the second shielding electrode BMLb may be omitted. In such an embodiment of the invention, the first shielding electrode BMLa may extend to a lower portion of the oxide transistor O-TFT and replace the second shielding electrode BMLb.

30 20 2 30 2 2 2 2 2 3 In an embodiment, a third insulation layermay be disposed on the second insulation layer. A second semiconductor pattern SCmay be disposed on the third insulation layer. The second semiconductor pattern SCmay include a channel region ACof the oxide transistor O-TFT. The second semiconductor pattern SCmay include an oxide semiconductor. The second semiconductor pattern SCmay include a transparent conductive oxide (TCO) such as an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium gallium zinc oxide (IGZO), a zinc oxide (ZnOx), an indium oxide (InO), or the like.

2 The oxide semiconductor may include a plurality of regions which are distinguished depending on whether a transparent conductive oxide has been reduced or not. A region in which the transparent conductive oxide has been reduced (hereinafter, a reduction region) has greater conductivity than a region in which the transparent conductive oxide has not been reduced (hereinafter, a non-reduction region). The reduction region substantially serves as a source/drain or signal line of a transistor. The non-reduction region substantially corresponds to a semiconductor region (or channel) of a transistor. In an embodiment, a partial region of the second semiconductor pattern SCmay be a semiconductor region of a transistor, another partial region thereof may be a source region/drain region of the transistor, and the other partial region thereof may be a signal transmissive region.

40 30 40 2 2 2 40 2 8 FIG.A In an embodiment, a fourth insulation layermay be disposed on the third insulation layer. As illustrated in, the fourth insulation layeroverlaps a gate GTof the oxide transistor O-TFT, and may be an insulation pattern exposed by a source region SEand a drain region DEof the oxide transistor O-TFT. In an embodiment of the invention, the fourth insulation layercommonly overlaps a plurality of pixels, and may cover the second semiconductor pattern SC.

2 40 2 2 2 In an embodiment, a gate GTof the oxide transistor O-TFT is disposed on the fourth insulation layer. The gate GTof the oxide transistor O-TFT may be a portion of a metal pattern. The gate GTof the oxide transistor O-TFT overlaps the channel region AC.

50 40 50 2 10 50 In an embodiment, a fifth insulation layeris disposed on the fourth insulation layer, and the fifth insulation layermay cover the gate GT. The first insulation layerto the fifth insulation layermay each be an insulation layer.

1 50 1 1 10 20 30 40 50 A first connection electrode CNEmay be disposed on the fifth insulation layer. The first connection electrode CNEmay be connected to the drain region DEof the silicon transistor S-TFT through a contact-hole defined through the first to fifth insulation layers,,,, and.

60 50 2 60 2 1 60 60 70 60 2 60 70 A sixth insulation layermay be disposed on the fifth insulation layer. A second connection electrode CNEmay be disposed on the sixth insulation layer. The second connection electrode CNEmay be connected to the first connection electrode CNEthrough a contact-hole defined through the sixth insulation layer. On the sixth insulation layer, the data line DL may be disposed. A seventh insulation layeris disposed on the sixth insulation layer, and may cover the second connection electrode CNEand the data line DL. The sixth insulation layerand the seventh insulation layermay each be an organic layer.

5 5 5 1 4 5 1 5 The fifth light emitting element LDmay include an anode AE(or a first electrode), a light emitting layer EL, and a cathode CE (or a second electrode). A cathode CE of the first light emitting element LDto the fourth light emitting element LDto be described later may have a shape of a single body with the cathode CE of the first light emitting element LD. That is, the cathode CE may be commonly provided to the first light emitting element LDto fifth light emitting element LD.

5 5 70 5 70 The anode AEof the fifth light emitting element LDmay be disposed on the seventh insulation layer. The anode AEmay be a (semi)transmissive electrode or a reflective electrode. A pixel definition film PDL may be disposed on the seventh insulation layer. The pixel definition film PDL may have properties of absorbing light, and for example, the pixel definition film PDL may have a black color. The pixel definition film PDL may include a black coloring agent. The black coloring agent may include a black dye and a black pigment. The black coloring agent may include a metal such as carbon black or chromium, or an oxide thereof. The pixel definition film PDL may correspond to a light blocking pattern having light blocking properties.

5 5 The pixel definition film PDL may cover a portion of the anode AE. In an embodiment, for example, the pixel definition film PDL may have an opening PDL-OP defined thereon, which exposes a portion of the anode AE.

5 5 5 3 FIG. Although not illustrated, a hole control layer may be disposed between the anode AEand the light emitting layer EL. The hole control layer includes a hole transport layer, and may further include a hole injection layer. An electron control layer may be disposed between the light emitting layer ELand the cathode CE. The electron control layer may include an electron transport layer, and may further include an electron injection layer. The hole control layer and the electron control layer may be commonly formed in the plurality of pixels PX (see) using an open mask.

140 130 140 141 142 143 140 The encapsulation layermay be disposed on the light emitting element layer. The encapsulation layermay include an inorganic layer, an organic layer, and an inorganic layersequentially stacked, but layers constituting the encapsulation layerare not limited thereto.

141 143 130 142 130 141 143 142 The inorganic layersandmay protect the light emitting element layerfrom moisture and oxygen, and the organic layermay protect the light emitting element layerfrom foreign materials such as dust particles. The inorganic layersandmay include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic layermay include an acrylic organic layer, but is not limited thereto.

210 220 230 240 The input sensor ISP may be disposed on the display panel DP. The input sensor ISP may include at least one conductive layer and at least one insulation layer. In an embodiment, the input sensor ISP may include a first sensing insulation layer, a first sensing conductive layer, a second sensing insulation layer, and a second sensing conductive layer.

210 210 220 240 3 220 240 220 240 230 220 240 The first sensing insulation layermay be directly disposed on the display panel DP. The first sensing insulation layermay be an inorganic layer including at least one selected from a silicon nitride, a silicon oxynitride, and a silicon oxide. Each of the first sensing conductive layerand the second sensing conductive layermay have a single-layered structure, or a multi-layered structure in which layers are laminated along the third direction DR. The first sensing conductive layerand the second sensing conductive layermay include connection electrodes which define an electrode in a mesh shape. A conductive line of the first sensing conductive layerand a conductive line of the second sensing conductive layermay be connected though a contact-hole defined through the second sensing insulation layer, or may not be connected. Depending on the type of a sensor provided as the input sensor ISP, the connection relationship between the conductive line of the first sensing conductive layerand the conductive line of the second sensing conductive layermay be determined.

220 240 The first sensing conductive layerand the second sensing conductive layerwhich have a single-layered structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as an indium tin oxide (ITO), an indium zinc oxide (IZO), a zinc oxide (ZnOx), an indium tin zinc oxide (ITZO), or the like. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like.

220 240 230 220 240 The first sensing conductive layerand the second sensing conductive layerwhich have a multi-layered structure may include metal layers. The metal layers may have, for example, a three-layered structure of titanium/aluminum/titanium. A conductive layer of a multi-layered structure may include at least one metal layer and at least one transparent conductive layer. The second sensing insulation layermay be disposed between the first sensing conductive layerand the second sensing conductive layer.

310 320 330 The anti-reflection layer ARL may be disposed on the input sensor ISP. The anti-reflection layer ARL may include a partition layer, a color filter, and a planarization layer.

310 310 310 A material constituting the partition layeris not particularly limited as long as it is a material which absorbs light. The partition layeris a layer having a black color, and in an embodiment, the partition layermay include a black coloring agent. The black coloring agent may include a black dye and a black pigment. The black coloring agent may include a metal such as carbon black or chromium, or an oxide thereof.

310 240 310 240 310 310 310 1 320 310 320 310 The partition layermay cover the second sensing conductive layerof the input sensor ISP. The partition layermay prevent external light reflection by the second sensing conductive layer. An opening-OP may be defined in the partition layer. The opening-OP may overlap an anode AE. The color filtermay overlap the opening-OP. The color filtermay come into contact with the partition layer.

330 310 320 330 330 330 The planarization layermay cover the partition layerand the color filter. The planarization layermay include an organic substance, and a flat surface may be provided on an upper surface of the planarization layer. In an alternative embodiment of the invention, the planarization layermay be omitted.

8 FIG.B 8 FIG.C 8 FIG.A 5 2 1 1 2 5 Inand, unlike the fifth pixel circuit PCand the second pixel circuit PC, an oxide transistor O-TFT of the first pixel circuit PCis not shown. Any repetitive detailed description of the same or like features of the first pixel PXand the second pixel PXas those of the fifth pixel PXdescribed with reference towill be omitted.

8 FIG.B 8 FIG.B 1 1 1 1 1 2 2 2 2 1 2 2 2 2 Referring to, while the first light emitting element LDand the first pixel circuit PCare both disposed in the first partial region P, the first light emitting element LDand the first pixel circuit PCmay be disposed to overlap each other on a plane. An anode AEof the second light emitting element LDdisposed in the second partial region Pmay be electrically connected to the second pixel circuit PCdisposed in the first partial region P. The anode AEof the second light emitting element LDmay be electrically connected to the silicon transistor S-TFT or the oxide transistor O-TFT.illustrates the anode AEof the second light emitting element LDconnected to the silicon transistor S-TFT.

2 2 2 1 2 A line portion LP of the anode AEof the second light emitting element LDmay extend from an electrode portion EP overlapping the opening PDL-OP. The line portion LP may be electrically connected to the second pixel circuit PCthrough connection electrodes CNE′ and CNE′.

8 FIG.C 8 FIG.C 1 2 2 2 1 2 1 60 70 1 2 1 1 Referring to, a first connection line TWL, which connects the anode AEof the second light emitting element LDand the second pixel circuit PCto each other, may be further disposed. The first connection line TWLmay be disposed in a layer different from the layer in which the anode AEis disposed. As shown in, the first connection line TWLmay be disposed between the sixth insulation layerand the seventh insulation layer. The first connection line TWLmay be connected to the anode AEand the connection electrode CNE′ through contact-holes. Since the first connection line TWLis disposed, short-circuiting with an anode of another light emitting element may be effectively prevented.

8 FIG.D 3 2 3 1 4 2 3 4 1 2 5 In, unlike the second third pixel circuit PC-, an oxide transistor O-TFT of the first third pixel circuit PC-and an oxide transistor O-TFT of the second fourth pixel circuit PC-are not shown. hereinafter, any repetitive detailed description of the same or like features of the third pixel PXand the fourth pixel PXas those of the first pixel PX, the second pixel PX, and the fifth pixel PXwill be omitted.

8 FIG.D 8 FIG.B 3 1 3 1 3 3 1 3 1 3 2 3 2 3 3 2 3 2 3 2 3 2 1 2 2 3 2 Referring to, while the first third light emitting element LD-and the first third pixel circuit PC-are both disposed in the third partial region P, the first third light emitting element LD-and the first third pixel circuit PC-may be disposed to overlap each other on a plane. While the second third light emitting element LD-and the second third pixel circuit PC-are both disposed in the third partial region P, the second third light emitting element LD-and the second third pixel circuit PC-may be disposed so as not to overlap each other on a plane. An anode AE-of the second third light emitting element LD-may be electrically connected the connection electrode CNE′ through a second connection line TWL. However, the embodiment of the invention is not limited thereto. Alternatively, the second connection line TWLmay be omitted, and as illustrated in, an extended line portion may be included such that the anode AE-is connected to a connection electrode without a separate connection line.

4 2 4 2 4 4 2 3 4 2 4 2 4 2 4 2 4 2 4 2 1 3 60 70 3 4 2 8 FIG.D 8 FIG.B An anode AE-of the second fourth light emitting element LD-disposed in the fourth partial region Pmay be electrically connected to the second fourth pixel circuit PC-disposed in the third partial region P. The anode AE-of the second fourth light emitting element LD-may be electrically connected to the silicon transistor S-TFT or the oxide transistor O-TFT.illustrates the anode AE-of the second fourth light emitting element LD-connected to the silicon transistor S-TFT. The anode AE-of the second fourth light emitting element LD-may be electrically connected the connection electrode CNE′ through a third connection line TWLdisposed between the sixth insulation layerand the seventh insulation layer. However, the embodiment of the invention is not limited thereto. Alternatively, the third connection line TWLmay be omitted, and as illustrated in, an extended line portion may be included such that the anode AE-is connected to a connection electrode without a separate connection line.

7 FIG.B 7 FIG.C 8 FIG.C 8 FIG.D 1 2 2 2 4 4 1 3 1 3 2 2 4 Referring to,,, andtogether, since the first separation distance sd, which is a separation distance between the second pixel circuit PCand the second light emitting element LD, is less than the second separation distance sd, which is a separation distance between the fourth pixel circuit PCand the fourth light emitting element LD, an extension length of the first connection line TWLmay be less than an extension length of the third connection line TWL. In an alternative embodiment, unlike what is illustrated, the first connection line TWLand the third connection line TWLmay be omitted. In such an embodiment, the length by which a line portion of the anode AEincluded in the second light emitting element LDextends may be less than the length by which a line portion of an anode included in the fourth light emitting element LDis extended.

5 FIG.A 5 FIG.B 7 FIG.A 7 FIG.D 8 FIG.A 8 FIG.D 3 3 3 4 4 4 Referring to,,to, andtotogether, in a display device according to an embodiment, the third display region DAmay correspond to the folding portion PLT-F of the support plate PLT in which the plurality of openings OP are defined, the third partial region Pof the third display region DAmay overlap the first extension portion F-C between the plurality of openings OP, and the fourth partial region Pmay be a region overlapping each of the plurality of openings OP. the fourth partial region Poverlapping the opening OP has low impact resistance, so that a circuit thereon may be disconnected or short-circuited by an external impact. In an embodiment, a pixel circuit may not be disposed in the fourth partial region Pto reduce defects of the pixel circuit.

7 FIG.B 7 FIG.C 8 FIG.B 8 FIG.C 8 FIG.D In an embodiment, as illustrated in,,,, and, when there is an arrangement in which a light emitting element and a pixel circuit are spaced apart from each other, an anode may extend to connect the light emitting element and the pixel circuit which are far from each other, or a separate connection line may be provided, so that parasitic capacitance may be generated due to the extended additional line. Due to the parasitic capacitance, a portion which has the arrangement in which a light emitting element and a pixel circuit are spaced apart from each other may have reduced luminance compared to a portion, for example, a first display region, in which a light emitting element and a pixel circuit are disposed adjacent to each other.

4 3 2 2 3 2 1 4 3 2 3 1 2 3 In the display device according to an embodiment, a pixel arrangement form in which a light emitting element and a pixel circuit are spaced apart from each other may be provided by not disposing the pixel circuit in the fourth partial region Pin the third display region DA, while a pixel arrangement form in which the pixel circuit is not disposed in the second partial region Peven in the display region DAadjacent to the third display region DAmay be provided to reduce defects of a pixel circuit. However, a separation distance (hereinafter, a first separation distance) between a second light emitting element disposed in the second partial region Pand a second pixel circuit disposed in the first partial region Pmay be designed to be less than a separation distance (hereinafter, a second separation distance) between a fourth light emitting element disposed in the fourth partial region Pand a fourth pixel circuit disposed in the third partial region P, and accordingly, the magnitude of parasitic capacitance (hereinafter, first parasitic capacitance) generated between the second light emitting element and the second pixel circuit may be less than the magnitude of parasitic capacitance (hereinafter, second parasitic capacitance) generated between the fourth light emitting element and the fourth pixel circuit. Since the magnitude of the first parasitic capacitance is less than the magnitude of the second parasitic capacitance, a luminance decrease value of the second display region DAmay be smaller than a luminance decrease value of the third display region DA. Therefore, the display device according to an embodiment of the invention may be designed in a way such that luminance gradually decreases in the order of the first display region DA, the second display region DA, and the third display region DA, and accordingly, the problem of exposing (or visually recognizing) the boundary between a region overlapping a folding portion of a support plate and a region overlapping a support portion of the support plate due to the difference in the pixel circuit arrangement may be effectively prevented.

9 FIG.A 9 FIG.B 9 FIG.B 9 FIG.A 9 FIG.A 9 FIG.B 5 FIG.B 5 FIG.C is a perspective view of a support plate according to an embodiment of the invention.is an enlarged plan view of a portion of a support plate according to an embodiment of the invention.illustrates a plane corresponding to region B′ of.andillustrate a support plate of an embodiment, which is different from the support plate illustrated inand.

9 FIG.A 9 FIG.B 3 FIG. 1 2 1 2 1 2 3 1 1 2 2 3 3 1 2 1 2 Referring toandtogether, a support plate PLT′ according to an embodiment includes a first support portion PLT-, a second support portion PLT-, and a folding portion PLT-F′, and in each of the first support portion PLT-and the second support portion PLT-, a first region PLAmay be defined, and in the folding portion PLT-F′, a second region PLAand a third region PLAmay be defined. The first region PLAmay be a region corresponding to the first display region DAin the display region DP-DA of the display panel DP described above with reference to. The second region PLAmay be a region corresponding to the second display region DAin the display region DP-DA of the display panel DP. The third region PLAmay be a region corresponding to the third display region DAin the display region DP-DA of the display panel DP. The first support portion PLT-, the second support portion PLT-, and the folding portion PLT-F′ may have a shape of a single body or be integrally formed with each other as a single unitary and indivisible part. In the folding portion PLT-F′, a plurality of openings OPand OPmay be defined.

3 1 1 1 1 2 2 2 2 2 In the third region PLAof the folding portion PLT-F′, a plurality of first openings OPmay be defined. A support region excluding the plurality of first openings OPmay include first first extension portions F-Cand first second extension portions F-L. In the second region PLAof the folding portion PLT-F′, a plurality of second openings OPmay be defined. A support region excluding the plurality of second openings OPmay include second first extension portions F-Cand second second extension portions F-L.

1 1 2 2 2 2 1 2 2 2 3 1 4 1 1 2 2 2 3 4 2 1 2 2 1 1 2 2 2 2 1 2 2 2 7 FIG.C 7 FIG.B 7 FIG.B 7 FIG.C In an embodiment, a width OPWof each of the first openings OPin the second direction DRmay be greater than a width OPWof each of the second openings OPin the second direction DR. In the same manner, the width of each of the first first extension portions F-Cin the second direction DRmay be greater than the width of each of the second first extension portions F-Cin the second direction DR. The third partial region Pdescribed above with reference tomay be a region overlapping the first first extension portion F-C, and the fourth partial region Pmay be a region overlapping the first opening OP. The first partial region Pdescribed above with reference tomay be a region overlapping the second first extension portion F-C, and the second partial region Pmay be a region overlapping the second opening OP. As described above with reference toand, since the width of each of the third partial region Pand the fourth partial region Pin the second direction DRis greater than the width of each of the first partial region Pand the second partial region Pin the second direction DR, respectively, the width OPWof each of the first openings OPin the second direction DRmay be greater than the width OPWof each of the second openings OPin the second direction DR, and the width of each of the first first extension portions F-Cin the second direction DRmay be greater than the width of each of the second first extension portions F-Cin the second direction DR.

10 FIG.A 10 FIG.B 10 FIG.C 10 FIG.D 2 3 is an enlarged plan view of portion BB of a second display region according to an embodiment of the invention.is an enlarged plan view of portion CC of a third display region according to an embodiment of the invention.is a cross-sectional view of the second display region DAaccording to an embodiment of the invention.is a cross-sectional view of the third display region DAaccording to an embodiment of the invention.

10 FIG.A 10 FIG.D 1 2 1 2 2 3 1 2 2 4 As illustrated into, the display device according to an embodiment may further include dummy pixel circuits PC-Dand PC-D. The dummy pixel circuits PC-Dand PC-Dmay be disposed in a partial region of the second display region DAand the third display region DAin which a pixel circuit is not disposed. The display device of an embodiment may include a first dummy pixel circuit PC-Ddisposed in the second partial region P, and a second dummy pixel circuit PC-Ddisposed in the fourth partial region P.

1 2 1 2 1 2 Each of the first dummy pixel circuit PC-Dand the second dummy pixel circuit PC-Dmay include at least a portion of the silicon transistor S-TFT and the oxide transistor O-TFT which are described above. Each of the first dummy pixel circuit PC-Dand the second dummy pixel circuit PC-Dmay include the semiconductor pattern, the gate, and the like, which are described above. Each of the first dummy pixel circuit PC-Dand the second dummy pixel circuit PC-Dmay include a dummy connection electrode which is connected to a silicon transistor and the like through a contact-hole passing through insulation layers.

1 2 2 1 2 2 2 4 4 2 4 2 4 2 10 FIG.C 10 FIG.D The first dummy pixel circuit PC-Dmay be disposed in the second partial region Pto overlap at least a portion of the second light emitting element LDon a plane. In an embodiment, for example, as illustrated in, the first dummy pixel circuit PC-Dmay overlap a portion of the anode AEof the second light emitting element LDon a plane. The second dummy pixel circuit PC-Dmay be disposed in the fourth partial region Pto overlap at least a portion of the fourth light emitting element LDon a plane. In an embodiment, for example, as illustrated in, the second dummy pixel circuit PC-Dmay overlap a portion of the anode AE-of the second fourth light emitting element LD-on a plane.

1 2 1 1 2 1 1 2 10 FIG.A The number of the first dummy pixel circuits PC-Ddisposed per reference area in the second partial region Pmay be substantially the same as the number of pixel circuits disposed per reference area in the first partial region P. In an embodiment illustrated in, four first dummy pixel circuits PC-Dmay be disposed per reference area in the second partial region P, and four pixel circuits may be disposed per reference area in the first partial region P. When the density of the first dummy pixel circuits PC-Dof the second partial region Pis defined as a first dummy circuit density, the first dummy circuit density may be substantially the same as a second circuit density.

2 4 3 2 4 3 2 4 10 FIG.B The number of the second dummy pixel circuits PC-Ddisposed per reference area in the fourth partial region Pmay be substantially the same as the number of pixel circuits disposed per reference area in the third partial region P. In an embodiment illustrated in, four second dummy pixel circuits PC-Dmay be disposed per reference area in the fourth partial region P, and four pixel circuits may be disposed per reference area in the third partial region P. When the density of the second dummy pixel circuits PC-Dof the fourth partial region Pis defined as a second dummy circuit density, the second dummy circuit density may be substantially the same as a fourth circuit density.

When there is a partial region in which a pixel circuit is not disposed by providing a pixel arrangement form in which a light emitting element and a pixel circuit are spaced apart from each other in some display regions, there may be a difference in visibility between a portion in which the pixel circuit is not disposed and a portion in which the pixel circuit is disposed. In an embodiment, in the portion in which the pixel circuit is not disposed, since a component such as a transistor included in the pixel circuit, or a component such as a contact-hole in which a connection electrode is disposed is omitted, optical properties such as transmittance may become different from those of the portion in which the pixel circuit is disposed, and accordingly, the boundary between the portion in which the pixel circuit is not disposed and the portion in which the pixel circuit is disposed may be undesirably visually recognized. In an embodiment of the invention, since the display device further includes a dummy pixel circuit disposed in a partial region in which a pixel circuit is not disposed, the problem in which the boundary between the portion in which the pixel circuit is not disposed and a portion in which the pixel circuit is disposed is visually recognized may be effectively prevented.

11 FIG.A 11 FIG.C toare perspective views of the electronic device ED according to an embodiment of the invention.

11 FIG.A 11 FIG.C 1 2 1 Referring toto, the electronic device ED according to an embodiment of the invention may have, in an unfolded state, a rectangular shape which has long sides in the first direction DRand short sides in the second direction DRwhich crosses the first direction DR. However, the embodiment of the invention is not limited thereto. The electronic device ED may have various shapes such as a circular shape and a polygonal shape.

1 2 1 2 3 1 2 1 2 3 1 1 1 2 2 2 3 1 2 1 2 3 1 2 1 2 3 11 11 FIGS.A andB 11 11 FIGS.A andB The electronic device ED may include a plurality of folding regions FAand FAand a plurality of non-folding regions NFA, NFA, and NFA. In, an embodiment of the electronic device ED including a first folding region FA, a second folding region FA, a first non-folding region NFA, a second non-folding region NFA, and a third non-folding region NFAis exemplarily illustrated. In the first direction DR, the first folding region FAis disposed between the first non-folding region NFAand the second non-folding region NFA, and the second folding region FAis disposed between the second non-folding region NFAand the third non-folding region NFA. In, an embodiment including two folding regions FAand FAand three non-folding regions NFA, NFA, and NFAare illustrated, but the number of the folding regions FAand FAand the number of the non-folding regions NFA, NFA, and NFAare not limited thereto, and may further increase.

11 FIG.A 11 FIG.B 1 1 2 1 1 1 2 1 2 2 2 2 2 2 3 Referring toand, the first folding region FAmay be folded with respect to a first folding axis FXparallel to the second direction DR. The first folding region FAhas a predetermined curvature and a first radius of curvature R. A display surface of the first non-folding region NFAis disposed outside, and a display surface of the second non-folding region NFAmay be outer-folded to become far from the display surface of the first non-folding region NFA. The second folding region FAmay be folded with respect to a second folding axis FXparallel to the second direction DR. The second folding region FAhas a predetermined curvature and a second radius of curvature R. The display surface of the second non-folding region NFAmay be inner-folded to become closer and to face a display surface of the third non-folding region NFA.

1 1 2 2 1 2 1 1 2 1 1 1 2 1 The first radius of curvature Rof the first folding region FAwhich is outer-folded may be greater than the second radius of curvature Rof the second folding region FAwhich is inner-folded. According to the first radius of curvature Rand the second radius of curvature R, the width of the first folding region FAin the first direction DRand the width of the second folding region FAin the first direction DRmay be determined. Therefore, the width of the first folding region FAin the first direction DRis greater than the width of the second folding region FAin the first direction DR.

11 FIG.C 3 FIG. 7 FIG.C 7 FIG.B 7 FIG.A 1 2 3 1 3 2 1 2 3 3 1 3 2 2 1 2 2 2 3 2 4 3 1 3 2 3 1 3 2 2 1 2 2 2 3 2 4 2 2 1 2 2 2 3 2 4 2 1 2 2 2 3 2 4 1 1 1 2 1 3 1 1 1 1 2 1 3 Referring to, each of the first folding region FAand the second folding region FAmay correspond to the folding region FA described with reference toand the like. Third display regions DA-and DA-may respectively correspond to the first folding region FAand the second folding region FA, and the features of the third display region DAdescribed above with reference toand the like may be applied to the third display regions DA-and DA-. In the electronic device ED according to an embodiment, second display regions DA-, DA-, DA-, and DA-may be disposed adjacent to each of the third display regions DA-and DA-, and the third display regions DA-and DA-may be disposed between two adjacent second display regions DA-, DA-, DA-, and DA-. The features of the second display region DAdescribed above with reference toand the like may be applied to the second display regions DA-, DA-, DA-, and DA-. In the second display regions DA-, DA-, DA-, and DA-, first display regions DA-, DA-, and DA-may be disposed, and the features of the first display region DAdescribed above with reference toand the like may be applied to the first display regions DA-, DA-, and DA-.

According to an embodiment of the invention, a pixel arrangement form is provided in which a pixel circuit is not disposed in a region corresponding to an opening of a support plate in a display panel, while a pixel circuit is not disposed in some regions even in a portion adjacent to a folding portion in which an opening is defined. Furthermore, an embodiment of the invention has a pixel arrangement form in which a separation distance between a pixel circuit and an light emitting element gradually increases as being closer to a folding portion, so that the problem of exposing a boundary between a region overlapping the folding portion of a support plate and a region overlapping a support portion of the support plate due to the difference in the pixel circuit arrangement may be effectively prevented.

The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.