Database driven place and route for coarse-grain reconfigurable architectures

This application is related to and filed in conjunction with U.S. patent application Ser. No. 18/092,439, filed on Jan. 2, 2023, entitled “ITERATIVE DATABASE DRIVEN PLACE AND ROUTE FOR COARSE-GRAIN RECONFIGURABLE ARCHITECTURES”, which is also related to and filed in conjunction with U.S. patent application Ser. No. 18/092,440, filed on Jan. 2, 2023, entitled “TRAINING A GRAPH NEURAL NETWORK FOR DATABASE DRIVEN PLACE AND ROUTE”, which is also related to commonly owned U.S. patent application Ser. No. 17/990,556, filed on Nov. 18, 2022, entitled “ESTIMATING THROUGHPUT FOR PLACEMENT GRAPHS FOR A RECONFIGURABLE DATAFLOW COMPUTING SYSTEM”, which is also related to commonly owned U.S. Provisional Application No. 63/282,159, filed on Nov. 22, 2021, entitled “DATA-DRIVEN COST MODELING FOR PLACEMENT AND ROUTING IN DATAFLOW ARCHITECTURE COMPILERS”, which is also related to commonly owned U.S. Provisional Application No. 63/406,196, filed on Sep. 23, 2022, entitled “LEARNED COST MODELS FOR PERFORMANCE OPTIMIZATION ON DATAFLOW ARCHITECTURE”, the entire contents of each application and together are hereby incorporated by reference. This application is further related to Prabhakar et al., entitled “Plasticine: A Reconfigurable Architecture for Parallel Patterns,” published in ISCA '17, on Jun. 24-28, 2017, Toronto, ON, Canada, which is also related to Koeplinger et al., entitled “Spatial: A Language and Compiler for Application Accelerators,” published in Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Embodiment (PLDI), Proceedings of the 43rd International Symposium on Computer Architecture, 2018, the entire contents of each reference and together are hereby incorporated by reference.

The technology disclosed relates to database driven place and route for reconfigurable architectures, and can be particularly applied to a database driven place and route system for coarse-grain reconfigurable architecture systems and other distributed execution systems.

Reconfigurable processors can be configured to implement a variety of functions more efficiently or faster than might be achieved using a general-purpose processor executing a computer program. For example, coarse-grain reconfigurable (CGR) architecture (CGRA) systems are being developed in which the configurable units in the array are more complex than used in typical, more fine-grained FPGAs, and may enable faster or more efficient dataflow execution of various classes of functions. For example, CGR processors have been proposed that can enable implementation of energy-efficient accelerators for machine learning and artificial intelligence workloads. See, Prabhakar, et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns,” ISCA '17, Jun. 24-28, 2017, Toronto, ON, Canada.

A CGR system is a composition of compute and memory units that are connected in a certain topology using an interconnect fabric. It is referred to as coarse-grained reconfigurable because the reconfigurable components in the architecture operate at a coarser granularity such as instructions, words, and vectors of words, compared to fine-grained, bit-level granularity commonly found in architectures such as FPGAs. Programmable data and control paths in CGR systems can make them a natural fit to exploit nested parallelism in applications, by connecting the recompute and memory units into customized, deeply nested, and hierarchical pipelines.

Achieving faster or more efficient dataflow execution of various classes of function depend on the compiler technology. A CGRA compiler is much more complex than a regular compiler because it has to (i) perform code analysis to extract task, data, and pipelined parallelism at multiple levels of nesting, (ii) partition and schedule operations in both space and time on the configurable units, (iii) place the operations onto the configurable units, and (iv) route the data and dataflow control information between the configurable units. Reducing compile time and achieving more efficient dataflow execution of various classes of function depends on how well a particular CGRA compiler performs these tasks.

The present disclosure describes a database driven place and route system for database driven place and route for coarse-grain reconfigurable architectures. The database driven place and route system utilizes empirically validated known reference graphs and their placements onto a coarse-grain reconfigurable architecture system in the form of a database, and applies the database for techniques to place unknown and unplaced unit graphs.

In an implementation, a computer-implemented method is used for database driven place and route (DAPR) for coarse-grain reconfigurable architectures (CGRA). An unplaced unit graph is received. The unplaced unit graph is classified against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database. Configurable units of the unplaced unit graph are placed onto positions in a configurable units array based on placement position attributes of at least a portion of configurable units of the nearest matching previously placed reference unit graph. Configuration data is generated that enables the configurable units array to execute at least a portion of the unplaced unit graph.

The described subject matter can be implemented using a computer-implemented method; a non-transitory, computer-readable medium storing computer-readable instructions to perform the computer-implemented method; and a computer-implemented system comprising one or more computer memory devices interoperably coupled with one or more computers and having tangible, non-transitory, machine-readable media storing instructions that, when executed by the one or more computers, perform the computer-implemented method/the computer-readable instructions stored on the non-transitory, computer-readable medium.

The details of one or more implementations of the subject matter of this specification are set forth in the Detailed Description, the Claims, and the accompanying drawings. Other features, aspects, and advantages of the subject matter will become apparent to those of ordinary skill in the art from the Detailed Description, the Claims, and the accompanying drawings.

In the figures, like reference numbers may indicate functionally similar elements. The systems and methods illustrated in the figures, and described in the Detailed Description, may be arranged and designed in a wide variety of different implementations. Neither the figures nor the Detailed Description are intended to limit the scope as claimed. Instead, they merely represent examples of different implementations of the disclosed technology.

The following detailed description describes a database driven place and route system for database driven place and route for coarse-grain reconfigurable architecture systems.

For the purposes of this disclosure, a CGRA compiler may (i) perform code analysis to extract task, data, and pipelined parallelism at multiple levels of nesting, (ii) partition and schedule operations in both space and time on the configurable units, (iii) place the operations onto the configurable units, and (iv) route the data and dataflow control information between the configurable units.

In a typical approach, an ab-initio placer is utilized to perform the placement task to place the operations onto the configurable units, which may account for a significant amount of the overall compile time.

In contrast to the typical approach utilizing an ab-initio placer to place the operations onto the configurable units for a CGR system, a DAPR system for DAPR for CGR systems is disclosed herein. The DAPR system may more efficiently perform the placement task, which may result in a reduction of time to perform the placement task and a reduction in the overall compile time. The DAPR system includes a database of placed reference unit graphs and their placements and routing. Each of the reference unit graphs and their placements and routing are known PNR solutions that have been executed on the CGR system. The DAPR system classifies a user unit graph against the database of placed reference unit graphs utilizing a graph neural network (GNN) to identify a matching subgraph of a placed reference unit graph having the highest nearness metric in the database. The DAPR system assigns the placement position attributes of the configurable units of the matching subgraph of the placed reference unit graph to position attributes of the corresponding units of the user unit graph. The DAPR system may use an ab-initio placer to place the remaining unmatched configurable units of the user unit graph to complete the placement task.

1 FIG. 100 110 160 170 180 190 110 120 120 110 138 139 120 138 139 130 180 138 185 139 190 195 120 120 illustrates an example coarse-grained reconfigurable architecture (CGRA) systemincluding a coarse-grained reconfigurable (CGR) processor, a compiler, runtime processes, a host, and a memory. CGR processorincludes a configurable units array such as a configurable units array. Configurable units arrayincludes an array of configurable units in an array level network. CGR processorfurther includes an IO interface, and a memory interface. Configurable units arrayis coupled with IO interfaceand memory interfacethrough a data buswhich may be part of a top-level network (TLN). Hostcommunicates with IO interfaceusing a system data bus, and memory interfacecommunicates with memoryusing a memory bus. A configurable unit in the configurable units arraymay comprise a compute unit or a memory unit. A configurable unit in the configurable units arraymay also comprise a pattern memory unit (PMU), a pattern compute unit (PCU), or a fused-compute memory unit (FCMU). Further examples include a coalescing unit (CU) and an address generator (AG), which may be combined in an AGCU. A configurable unit may also be reconfigurable.

120 110 110 110 110 120 The configurable units in the configurable units arraymay be connected with an array-level network (ALN) to provide the circuitry for execution of a computation graph or a dataflow graph that may have been derived from a high-level program with user algorithms and functions. The high-level program may include a set of procedures, such as learning or inferencing in an artificial intelligence (AI) or machine learning (ML) system. More specifically, the high-level program may include applications, graphs, application graphs, user applications, computation graphs, control flow graphs, dataflow graphs, models, deep learning applications, deep learning neural networks, programs, program images, jobs, tasks and/or any other procedures and functions that may need serial and/or parallel processing. In some implementations, execution of the graph(s) may involve using multiple CGR processors. In some implementations, CGR processormay include one or more ICs. In other implementations, a single IC may span multiple CGR processors. In further implementations, CGR processormay include multiple configurable units arrays.

180 180 170 160 9 160 180 2 FIG. 2 FIG. Hostmay be, or include, a computer such as further described with reference to. Hostruns runtime processes, as further referenced herein, and may also be used to run computer programs, such as compilerfurther described herein with reference to FIG.. In some implementations, compilermay run on a computer that is similar to the computer described with reference tobut separate from host.

110 165 165 120 110 160 165 120 165 110 120 165 120 120 120 165 110 120 CGR processormay accomplish computational tasks by executing a configuration file. Configuration filemay comprise a processor-executable format file suitable for configuring a configurable units arrayof a CGR processor. For the purposes of this description, a configuration file corresponds to a dataflow graph, or a translation of a dataflow graph, and may further include initialization data. Compilercompiles the high-level program to provide the configuration file. In some implementations described herein, a configurable units arrayis configured by programming one or more configuration stores with all or parts of the configuration file. A single configuration store may be at the level of the CGR processoror the configurable units array, or a configurable unit may include an individual configuration store. The configuration filemay include configuration data for the configurable units arrayand the configurable units in the configurable units arrayand link the computation graph to the configurable units array. Execution of the configuration fileby CGR processorcauses the configurable unitsarray(s) to implement the user algorithms and functions in the dataflow graph.

110 CGR processorcan be implemented on a single integrated circuit die or on a multichip module (MCM). An IC can be packaged in a single chip module or a multichip module. An MCM is an electronic package that may comprise multiple IC dies and other devices, assembled into a single module as if it were a single device. The various dies of an MCM may be mounted on a substrate, and the bare dies of the substrate are electrically coupled to the surface or to each other using for some examples, wire bonding, tape bonding or flip-chip bonding.

2 FIG. 200 210 220 230 240 200 210 240 210 240 110 210 220 226 220 240 226 240 220 222 226 224 226 222 226 230 226 230 230 235 illustrates an example of a computer, including an input device, a processor, a storage device, and an output device. Although the example computeris drawn with a single processor, other implementations may have multiple processors. Input devicemay comprise a mouse, a keyboard, a sensor, an input port (for example, a universal serial bus (USB) port), and any other input device known in the art. Output devicemay comprise a monitor, printer, and any other output device known in the art. Furthermore, part or all of input deviceand output devicemay be combined in a network interface, such as a Peripheral Component Interconnect Express (PCIe) interface suitable for communicating with CGR processor. Input deviceis coupled with processorto provide input data, which an implementation may store in memory. Processoris coupled with output deviceto provide output data from memoryto output device. Processorfurther includes control logic, operable to control memoryand arithmetic and logic unit (ALU), and to receive program and configuration data from memory. Control logicfurther controls exchange of data between memoryand storage device. Memorytypically comprises memory with fast access, such as static random-access memory (SRAM), whereas storage devicetypically comprises memory with slow access, such as dynamic random-access memory (DRAM), flash memory, magnetic disks, optical disks, and any other memory type known in the art. At least a part of the memory in storage deviceincludes a non-transitory computer-readable medium (CRM), such as used for storing computer programs.

3 FIG. 300 330 310 320 330 338 339 illustrates example details of a CGR architectureincluding a top-level network (TLN) and two configurable units arrays (configurable units arrayand configurable units array). A configurable units array comprises a configurable unit (such as, PMUs, PCUs, FCMUs) coupled using an array-level network (ALN), for example, a bus system. The ALN is coupled with the TLNthrough several AGCUs, and consequently with I/O interface(or any number of interfaces) and memory interface. Other implementations may use different bus or communication architectures.

338 339 Circuits on the TLN in this example include one or more external I/O interfaces, including I/O interfaceand memory interface. The interfaces to external devices include circuits for routing data among circuits coupled with the TLN and external devices, such as high-capacity memory, host processors, other CGR processors, FPGA devices, and so on, that are coupled with the interfaces.

310 Each depicted configurable units array has four AGCUs (including, MAGCU1, AGCU12, AGCU13, and AGCU14 in configurable units array). The AGCUs interface the TLN to the ALNs and route data from the TLN to the ALN or vice versa.

310 320 One of the AGCUs in each configurable units array in this example is configured to be a master AGCU (MAGCU), which includes an array configuration load/unload controller for the configurable units array. The MAGCU1 includes a configuration load/unload controller for configurable units array, and MAGCU2 includes a configuration load/unload controller for configurable units array. Some implementations may include more than one array configuration load/unload controller. In other implementations, an array configuration load/unload controller may be implemented by logic distributed among more than one AGCU. In yet other implementations, a configuration load/unload controller can be designed for loading and unloading configuration of more than one configurable units array. In further implementations, more than one configuration controller can be designed for configuration of a single configurable units array. Also, the configuration load/unload controller can be implemented in other portions of the system, including as a stand-alone circuit on the TLN and the ALN or ALNs.

311 312 313 314 315 316 338 311 312 314 315 311 314 312 313 The TLN is constructed using top-level switches (switch, switch, switch, switch, switch, and switch) coupled with each other as well as with other circuits on the TLN, including the AGCUs, and external I/O interface. The TLN includes links (for example, L11, L12, L21, L22) coupling the top-level switches. Data may travel in packets between the top-level switches on the links, and from the switches to the circuits on the network coupled with the switches. For example, switchand switchare coupled by link L11, switchand switchare coupled by link L12, switchand switchare coupled by link L13, and switchand switchare coupled by link L21. The links can include one or more buses and supporting control lines, including for example a chunk-wide bus (vector bus). For example, the top-level network can include data, request and response channels operable in coordination for transfer of data in any manner known in the art.

4 FIG. 400 400 401 402 401 403 405 404 403 421 401 422 403 405 420 403 illustrates an example configurable units array, including a configurable units array in an ALN. Configurable units arraymay include several types of configurable unit, such as FCMUs, PMUs, PCUs, memory units, and/or compute units. For examples of the functions of these types of configurable units, see Prabhakar et al., “Plasticine: A Reconfigurable Architecture for Parallel Patterns”, ISCA 2017, Jun. 24-28, 2017, Toronto, ON, Canada. Each of the configurable units may include a configuration storecomprising a set of registers or flip-flops storing configuration data that represents the setup and/or the sequence to run a program, and that can include the number of nested loops, the limits of each loop iterator, the instructions to be executed for each stage, the source of operands, and the network parameters for the input and output interfaces. In some implementations, each configurable unitcomprises an FCMU. In other implementations, the array comprises both PMUs and PCUs, or memory units and compute units, arranged in a checkerboard pattern. In yet other implementations, configurable units may be arranged in different patterns. The ALN includes switch units(S), and AGCUs (each including two address generators(AG) and a shared coalescing unit(CU)). Switch unitsare connected among themselves using interconnectsand to a configurable unitwith interconnects. Switch unitsmay be coupled with address generatorsusing interconnects. In some implementations, communication channels can be configured as end-to-end connections, and switch unitsare configurable units. In other implementations, switches route data using the available links based on address information in packet headers, and communication channels establish as and when needed.

A configuration file may include configuration data representing an initial configuration, or starting state, of each of the configurable units that execute a high-level program with user algorithms and functions. Program load is the process of setting up the configuration stores in the configurable units array based on the configuration data to allow the configurable units to execute the high-level program. Program load may also require loading memory units and/or PMUs.

421 The ALN includes one or more kinds of physical data buses, for example a chunk-level vector bus (for instance, 512 bits of data), a word-level scalar bus (for example, 32 bits of data), and a control bus. For instance, interconnectsbetween two switches may include a vector bus interconnect with a bus width of 512 bits, and a scalar bus interconnect with a bus width of 32 bits. A control bus can comprise a configurable interconnect that carries multiple control bits on signal routes designated by configuration bits in the configurable units array's configuration file. The control bus can comprise physical lines separate from the data buses in some implementations. In other implementations, the control bus can be implemented using the same physical lines with a separate protocol or in a time-sharing procedure.

Physical data buses may differ in the granularity of data being transferred. In one implementation, a vector bus can carry a chunk that includes 16 channels of 32-bit floating-point data or 32 channels of 16-bit floating-point data (that is, 512 bits) of data as its payload. A scalar bus can have a 32-bit payload and carry scalar operands or control information. The control bus can carry control handshakes such as tokens and other signals. The vector and scalar buses can be packet-switched, including headers that indicate a destination of each packet and other information such as sequence numbers that can be used to reassemble a file when the packets are received out of order. Each packet header can contain a destination identifier that identifies the geographical coordinates of the destination switch unit (such as, the row and column in the array), and an interface identifier that identifies the interface on the destination switch (for example, North, South, East, West, among others) used to reach the destination unit.

401 403 A configurable unitmay have four ports (as drawn) to interface with switch units, or any other number of ports suitable for an ALN. Each port may be suitable for receiving and transmitting data, or a port may be suitable for only receiving or only transmitting data.

4 FIG. 421 422 420 A switch unit, as shown in the example of, may have eight interfaces. The North, South, East and West interfaces of a switch unit may be used for links between switch units using interconnects. The Northeast, Southeast, Northwest and Southwest interfaces of a switch unit may each be used to make a link with an FCMU, PCU or PMU instance using one of the interconnects. Two switch units in each configurable units array quadrant have links to an AGCU using interconnects. The AGCU coalescing unit arbitrates between the AGs and processes memory requests. Each of the eight interfaces of a switch unit can include a vector interface, a scalar interface, and a control interface to communicate with the vector network, the scalar network, and the control network. In other implementations, a switch unit may have any number of interfaces.

400 400 During execution of a graph or subgraph in a configurable units array after configuration, data can be sent using one or more switch units and one or more links between the switch units to the configurable units using the vector bus and vector interface(s) of the one or more switch units on the ALN. A configurable units array may comprise at least a part of configurable units array, and any number of other configurable units arrays coupled with configurable units array.

A data processing operation implemented by configurable units array configuration may comprise multiple graphs or subgraphs specifying data processing operations that are distributed among and executed by corresponding configurable units (including, FCMUs, PMUs, PCUs, AGs, and CUs).

5 FIG. 500 510 520 530 510 520 510 515 520 521 526 528 illustrates an exampleof a PMUand a PCU, which may be combined in an FCMU. PMUmay be directly coupled to PCU, or optionally using one or more switches. PMUincludes a scratchpad memory, which may receive external data, memory addresses, and memory control information (write enable, read enable) using one or more buses included in the ALN. PCUincludes two or more processor stages, such as SIMDthrough SIMD, and configuration store. The processor stages may include ALUs, or SIMDs, as drawn, or any other reconfigurable stages that can process data.

520 Each stage in PCUmay also hold one or more registers (not drawn) for short-term storage of parameters. Short-term storage, for example during one to several clock cycles or unit delays, allows for synchronization of data in the PCU pipeline.

6 FIG. 6 FIG. 600 610 611 612 613 611 621 612 622 614 614 610 620 613 623 614 615 624 600 shows an example of a computation graph. Computation graphs represent mathematical expressions and comprise nodes and directed edges. In, nodes are drawn as circles and directed edges are drawn as arrows. A node can represent a constant, a variable, for example from an input, an operation, an equation, or an output value. A directed edge can represent a dependency. Noderepresents a variable A1, whose present value equals 12. Noderepresents a variable A2, whose present value equals 251. Noderepresents the constant π. Noderepresents a multiplication operation. It receives its input data from nodeusing directed edgeand from nodeusing directed edge. Noderepresents an addition operation. Nodereceives its input data from nodeusing directed edgeand from nodeusing directed edge. Nodeoutputs its result in output nodeusing directed edge. Computation graphas a whole represents the equation Output=A1+pi*A2.

600 614 613 614 613 610 614 613 The depicted computation graphis very simple and could be implemented electronically in many ways. For example, it could be hardwired as a circuit of digital gates in an application-specific IC (ASIC), or an FPGA could be configured to emulate the circuit of digital gates, or a CGR processor could be configured to perform the addition and multiplication functions, or a CPU could run a conventional computer program to perform the functions. In all implementations, the timing is important. Nodeis not able to calculate a valid output value until all its input values are valid. That means nodemust be finished first. Most digital circuits are implemented as pipelines of clocked stages. If the add operation of nodeis in a later stage than the multiplication operation of node, then a fixed-delay buffer may need to be inserted between nodeand nodeto synchronize the value of variable A1 with the result of the multiplication in node. The fixed-delay buffer can be added to the graph to make it physically implementable.

Most computation graphs are a-cyclic, that is, they don't include loops. One class of computation graphs, dataflow graphs, may include loops, and even nested loops. This can make delays of operations performed by nodes variable, dependent on the data flowing through a pipeline of operations. When a high-level program includes multiple pipelines of parallel, interdependent operations, then synchronization can become highly complex. Synchronization can be further complicated when directed edges are implemented as data channels in a network, since the data channels can become congested. A CGR processor, may resolve both problems by using dataflow control information, sent as messages from consuming nodes to producing nodes to indicate that the consuming node is ready to receive the information, and a credit token system that prevents congestion of the data channels between the producing and consuming nodes.

7 FIG. 700 709 710 710 702 712 722 708 709 703 704 705 706 707 shows an example of a dataflow graph. This example, one head of a multi-head attention module in the Transformer model first published by Vaswani, et al., “Attention Is All You Need,” 31st Conference on Neural Information Processing Systems, 2017, is well known in the industry. It includes a loopwithin a loop. Loopincludes four general matrix multiplications, GeMM, GeMM, GeMM, and GeMM. Loopincludes an ingress matrix multiplication GeMM, mask fill node, softmax node, dropout node, and egress matrix multiplication node.

700 To physically implement dataflow graph, an implementation may insert three types of stage buffers: (1) inter-stage buffers, (2) intra-stage buffers, and (3) interface buffers. The interface buffers are used because the granularity of communication (that is, the size of tensors or data produced or consumed) varies between loops at different levels. Further, an implementation must add dataflow control information, to synchronize the various stages of asynchronous computation.

8 FIG. 7 FIG. 800 700 shows the dataflow graph ofwith buffers and dataflow control information added. A compiler in the technology presented herein can create graphfrom dataflow graph, assign the nodes to compute units and memory units in a configurable units array, and assign edges and dataflow control information to data channels in an array-level network that connects the compute units and memory units.

700 800 810 809 8 FIG. 7 FIG. To get from dataflow graphto graph, one compiler implementation divides the dataflow graph in stages (stages 0, 1, and 2 are shown in this example), and where there are nested loops also in substages (substages 1.0 through 1.4 are shown). The implementation inserts buffers between the stages to allow for pipelined processing in one or more parallel meta-pipelines that may interact. The buffers are shown as blocks labeled A . . . L. They are different from buffers at the gate level, which may be single or double inverters used to boost the energy level of digital signals that need to travel through long wires or that need to drive high-capacitance loads, or which may be flipflops operated by a system clock and used to implement synchronous logic. The buffers at the meta-pipeline level may be memories, register files, shift registers, or first-in-first-out (FIFO) memories of fixed or variable length, storing one or more data items (for example, scalars, vectors, or tensors). They may be clocked by a producer node to store data or by a consumer node to release data. They may further be controlled by dataflow control information coming from, for example, downstream nodes.shows the same operation nodes as(with like numbering), but the edges (solid arrows), where dataflows, are interrupted by the buffers to partition the graph into stages, and dataflow control information is added (shown as dashed arrows for loopand dash-dot arrows for loop). In the example shown, data travels downstream (solid arrows from the left to the right) and dataflow control information travels upstream (dashed arrows from the right to the left).

800 In further preparation for a physical implementation of graph, an implementation may assign each operation node to one or more logical compute units or memory units, and each buffer to one or more logical memory units. Some implementations may perform further preparations and optimizations. All implementations proceed to place and route, that is, assign the logical units to physical units in a layout of a configurable units array, and (in some implementations) assign the data connections and the dataflow control information connections to data channels in the ALN in the configurable units array.

9 FIG. 900 980 120 110 100 900 980 110 160 980 910 910 160 915 110 100 910 910 980 160 987 926 926 165 170 165 110 100 160 921 922 923 924 925 922 930 931 924 932 933 is a block diagram of an example compiler system flowfor transforming a high-level programsuitable for mapping onto a configurable units array such as the configurable units array, a CGR such as CGR, or a CGR system such as CGR system. As depicted, the compiler system flowincludes several stages to convert a high-level programwith user algorithms and functions such as algebraic expressions and functions, to configuration data for the configurable units and the configurable interconnections of CGR processor. A compilermay take its input including a high-level programfrom application platform, or any other source of high-level program statements suitable for parallel processing, where application platformmay provide a user interface for general users. Compilermay further receive hardware description, for example, defining the physical units in a CGR processor such as CGR processoror a CGR system such as CGR system. Application platformmay include machine learning frameworks such as PyTorch, TensorFlow, ONNX, Caffe, and Keras to provide user-selected and configured algorithms. Application platformprovides its output including the high-level programto compiler, which in turn provides its output data including placement and routing informationto a configuration file generator. Configuration file generatorprovides its output including a configuration fileto runtime processes, which in turn provides the configuration fileto CGR processoror CGR systemwhere it is executed. Compilermay include a dataflow graph compiler, an algebraic graph compiler, a template graph compiler, a template library stack, and a database driven place and route (DAPR). Algebraic graph compilerincludes a model analyzer and compiler (MAC) leveland an arithmetic or algebraic intermediate representation (AIR) level. Template library stackincludes configurable units array abstract intermediate language (RAIL)and assembly language interfacesfor power users.

921 980 910 981 980 981 921 981 980 921 110 910 921 921 981 110 921 910 At action 1, the dataflow graph compilerconverts the high-level programwith user algorithms and functions from application platformto one or more dataflow graphs. The high-level programmay be suitable for parallel processing, and therefore parts of the nodes of the dataflow graphsmay be intrinsically parallel unless an edge in the graph indicates a dependency. Dataflow graph compilermay provide code optimization steps like false data dependency elimination, dead-code elimination, and constant folding. The dataflow graphsencode the data and dataflow control information of the high-level program. Dataflow graph compilermay support programming a CGR processorat multiple levels, for example from an application platformto C++ and assembly language. In some implementations, dataflow graph compilerallows programmers to provide code that runs directly on the configurable data processor. In other implementations, dataflow graph compilerprovides libraries that contain predefined functions like linear algebra operations, element-wise tensor operations, activation functions, and reductions required for creating, executing, and profiling the dataflow graphson the CGR processors. Dataflow graph compilermay provide an application programming interface (API) to enhance functionality available using the application platform.

922 981 922 981 981 At action 2, algebraic graph compilermay include a MAC level that makes high-level mapping decisions for (sub-graphs of the) dataflow graphbased on hardware constraints. It may support various application frontends such as Samba, JAX, and TensorFlow/HLO. Algebraic graph compilermay also transform dataflow graphsusing autodiff and GradNorm, perform stitching between subgraphs, interface with template generators for performance and latency estimation, convert dataflow graph operations to AIR operation, perform tiling, sharding (database partitioning) and other operations, and model or estimate the parallelism that can be achieved on the dataflow graphs.

922 931 930 982 931 930 930 922 931 110 922 110 922 Algebraic graph compilermay further include AIR levelthat translates high-level graph and mapping decisions provided by MAC levelinto explicit AIR/Tensor statements and one or more corresponding algebraic graphs. Responsibilities of AIR levelmay include legalizing the graph and mapping decisions of MAC level, expanding data parallel, tiling, metapipe, region instructions provided by MAC level, inserting stage buffers and skip buffers, eliminating redundant operations, buffers, and sections, and optimizing for resource use, latency, and throughput. Algebraic graph compilermay legalize the deep neural network (DNN) graphs and task-graphs at AIR level, by determining whether operators in the graph are composable, that is, their specific attributes, sizes, and shapes are mappable to a CGR processor, such as CGR processor. Algebraic graph compilermay also determine whether the operators are supported by the compiler to CGR processor, and whether operators in combination with operators or optimization flags for the compiler are suitable for compilation, among other operator compatibility requirements. Algebraic graph compilermay be carried out by standard compiler passes implemented to check and allow or check and disallow such patterns in the input DNN graphs and task-graphs in process at the compiler level.

923 982 983 925 983 923 925 923 982 At action 3, template graph compilermay translate AIR graphsand/or statements into template library intermediate representation (TLIR) graphsand/or statements, optimizing for the target hardware architecture, into placeable variable-sized units, which may be referred to as logical configurable units, suitable for DAPR system. Meta-pipelines that enable iteration control may be allocated for sections of the TLIR statements and/or corresponding sections of the TLIR graphs. Template graph compilermay add further information (name, inputs, input names and dataflow description) for DAPR systemand make the graph physically realizable through each performed step. Template graph compilermay, for example, provide translation of AIR graphsto specific model operation templates such as for general matrix multiplication (GEMM). An implementation may convert part or all intermediate representation operations to templates, stitch templates into the dataflow and control flow, insert necessary buffers and layout transforms, generate test data and optimize for hardware use, latency, and throughput.

924 983 984 984 At action 4, template library stackmay translate TLIR graphsinto unplaced unit graphsincluding unplaced compute units and memory units, which may correspond to logical, unplaced physically realizable, compute units and memory units. Unplaced unit graphsfurther includes data connections between the unplaced compute units and memory units.

924 932 In some implementations, templates for common operations may be used. Templates may be implemented using assembly language, RAIL, or similar. RAIL is comparable to assembly language in that memory units and compute units are separately programmed, but it can provide a higher level of abstraction and compiler intelligence using a concise performance-oriented domain-specific language for configurable units array templates. Template library stackmay include a RAIL low-level interface such as RAIL interfacethat enables template writers and external power users to control interactions between logical compute units and memory units with high-level expressions without the need to manually program capacity splitting, register allocation, or other types of control interactions. The logical compute units and memory units also enable stage/register allocation, context splitting, transpose slotting, resource virtualization and mapping to multiple physical compute units and memory units, such as, PCUs and PMUs. RAIL also enables event handle allocation.

924 933 983 Template library stackmay also include an assembler that provides an architecture-independent low-level programming interface such as assembly language interfaceas well as optimization and code generation for the target hardware. Responsibilities of the assembler may include address expression compilation, intra-unit resource allocation and management, making a TLIR graphphysically realizable with target-specific rules, low-level architecture-specific transformations and optimizations, and architecture-specific code generation.

925 985 986 985 120 120 120 120 DAPR systemmay include a reference graphs and placements databaseand a graph neural network (GNN). Reference graphs and placements databasemay include placed reference unit graphs, where each of the placed reference unit graphs has been successfully placed and routed in the configurable units array, the corresponding implementation has been successfully executed on the configurable units array, and the post-run attributes associated with the execution have met or exceeded a post-run attributes success criterion. As such, each of the placed reference unit graphs have been shown to be a known solution for PNR. Each placed reference unit graph of the placed reference unit graphs may include configurable units, data connections between the configurable units, and placement position attributes of the corresponding configurable units in the configurable units array. The configurable units may include memory units and compute units. The data connections between the configurable units may comprise data connections between the memory units and the compute units. The placement position attributes of the corresponding configurable units may include placement position attributes of the corresponding memory units and the compute units in the configurable units array. Each placed reference unit graph may further include post-run attributes associated with the execution of an implementation of a corresponding placed and routed reference unit graph.

985 985 915 In some implementations, reference graphs and placements databasemay comprise a configurable units array attributes table, where each table entry in the configurable units array attributes table may correspond to a placed reference unit graph and the number of table entries in the configurable units array attributes table corresponds to the number of placed reference unit graphs in the reference graphs and placements database. The size of each placed reference unit graph is bound by the number of memory units and compute units in a configurable units array. A configurable units array is defined by configurable units array information in the hardware description, the configurable units array information may include structural information of a configurable units array such as row and column information, ALN information of the configurable units array, a type of each configurable unit in the configurable units array, position information of each configurable unit, a number of each type of configurable unit for example, the number of memory units and compute units in the configurable units array, and other information associated with the configurable units array.

985 985 986 986 986 984 985 16 16 FIGS.A andB Each placed reference unit graph of the reference graphs and placements databaseis a known PNR solution, as previously described. As such, each of the placed reference unit graphs of the reference graphs and placements databasemay be utilized to train the GNN. Training of the GNN is described in more detail with respect to. The DAPR system. Once GNNis trained, it may be utilized as a classifier to classify a unit graph, such as unplaced unit graph, against reference graphs and placements database.

925 984 981 980 984 At action 5, DAPR systemreceives an unplaced unit graphthat may represent at least a portion of dataflow graphof high-level program. Unplaced unit graphmay include unplaced configurable units and data connections between the unplaced configurable units. The unplaced configurable units may include unplaced memory units and compute units, and the data connections between the unplaced configurable units may include data connections between the unplaced memory units and the compute units.

925 984 985 986 985 DAPR systemmay classify unplaced unit graphagainst a reference graphs and placements databaseusing GNNto identify a nearest matching previously placed reference unit graph of the reference graphs and placements databaseand an associated matching score. The matching score is found as the ratio of the size of the matching subgraph of the nearest matching previously placed reference unit graph to the size of the nearest matching previously placed reference unit graph. The size of the matching subgraph of the nearest matching previously placed reference unit graph is equal to the number of nodes plus the number of edges in the matching subgraph, and the size of the nearest matching previously placed reference unit graph is equal to the number of nodes plus the number of edges in the nearest matching previously placed reference unit graph. Thus, a similarity matching score for a graph will have a value in the range of 0 and 1 inclusive, where a non-overlapping graph will have a similarity score of 0 and a fully overlapping graph will have a value of 1.

984 986 986 The unplaced unit graphis provided as input to the GNNand the GNNproduces the nearest matching previously placed reference unit graph and the associated matching score as output.

925 984 984 DAPR systemmay determine whether the associated matching score of the nearest matching previously placed reference unit graph is greater than an acceptance threshold. A matching score that is greater than an acceptance threshold indicates that the matching subgraph of the nearest matching previously placed reference unit graph has an appropriate amount of overlap with the unplaced unit graphto utilize the placement information associated with the previously placed matching subgraph to place the corresponding configurable units of the unplaced unit graph. A matching score that does not exceed the acceptance threshold indicates that there is not enough overlap to justify using the placement information. An acceptance threshold used to make overlap and placement determinations can be set statically, dynamically, or both statically and dynamically determined. The acceptance threshold value may be set to a static value based on testing and/or experimental results, for example, setting the acceptance threshold value to 0.5 (50% overlap), 0.75 (75% overlap), or another appropriate value between 0 and 1. Alternatively, or in addition to setting the value to a starting static value, the acceptance threshold value may be set dynamically based on the dynamic state of the GNN and newer previously placed reference unit graphs that have been shown to produce improved placement and runtime results and applying that learning in training the GNN to create an improved trained GNN.

925 925 984 120 984 120 925 984 120 984 120 925 984 120 110 In response to a determination that the associated matching score is greater than the acceptance threshold, DAPR systemmay identify a matching subgraph of the nearest matching previously placed reference unit graph. DAPR systemmay also assign the placement position attributes of configurable units of the matching subgraph of the nearest matching previously placed reference unit graph to corresponding placement positions of configurable units of the unplaced unit graphin a configurable units array. The assignment of the placement position attributes may include the assignment of the placement position attributes of memory units and compute units of the matching subgraph of the nearest matching previously placed reference unit graph to corresponding placement positions of memory units and compute units of the unplaced unit graphin the configurable units array. DAPR systemmay further place unmatched configurable units of the unplaced unit graphonto positions in the configurable units array. The placement of the unmatched configurable units may include the placement of unmatched memory units and unmatched compute units of the unplaced unit graphonto positions in the configurable units array. In response to determining that the associated matching score is less than or equal to the acceptance threshold, DAPR systemmay place, using an ab-initio placer, the unplaced memory units and the unplaced compute units of the unplaced unit graphonto positions in the configurable units arrayof CGR processorat the physical chip level.

925 120 925 925 120 110 DAPR systemmay route data and dataflow control information between the placement positions in the configurable units array. As part of the routing, DAPR systemmay determine physical data channels to allow for communication among the configurable units and between the configurable units and circuits coupled using the TLN. DAPR systemmay allocate ports on the configurable units and switches and provide configuration data and initialization data for the target hardware including the configurable units arrayand CGR processor.

925 925 925 921 922 923 924 923 925 925 987 9 FIG. DAPR systemmay further provide bandwidth calculations, allocate network interfaces such as AGCUs and virtual address generators (VAGs), provide configuration data that allows AGCUs and/or VAGs to perform address translation, and control ALN switches and data routing. DAPR systemmay provide its functionality in multiple steps and may include multiple modules (not shown in) to provide the multiple steps including a placer, a port allocator, and a router. DAPR systemmay receive its input data in various ways. For example, it may receive parts of its input data from any of the earlier modules (dataflow graph compiler, algebraic graph compiler, template graph compiler, and/or template library). In some implementations, an earlier module, such as template graph compiler, may have the task of preparing all information for DAPR systemand no other units provide PNR input data directly. DAPR systemmay produce PNR information.

926 987 925 165 984 120 120 981 984 165 120 At action 6, a configuration file generatormay receive PNR informationfrom DAPR systemand generate a configuration filewith configuration data for the placement positions of the configurable units of the unplaced unit graphand the routed data and the dataflow control information. The configuration data, when loaded onto an instance of the configurable units array, causes the configurable units arrayto implement at least the portion of the dataflow graphrepresented by the unplaced unit graph. Configuration filemay be a processor-executable format (PEF) file. In one implementation, this includes assigning coordinates and communication resources of the physical memory and compute units by placing and routing units onto the configurable units arraywhile maximizing bandwidth and minimizing latency.

170 165 120 110 120 110 165 981 984 At action 7, the runtime processesloads the configuration fileonto an instance of the configurable units arrayof CGR processorand causes the configurable units arrayof CGR processorto execute the configuration fileto implement at least the portion of the dataflow graphrepresented by the unplaced unit graph.

160 925 925 922 Further implementations of compilerprovide for an iterative process, for example by feeding information from DAPR systemback to an earlier module, so that the earlier module can execute a new compilation step in which it uses physically realized results rather than estimates of or placeholders for physically realizable circuits. For example, DAPR systemmay feed information regarding the physically realized circuits back to algebraic graph compiler.

981 Memory allocations represent the creation of logical memory spaces in on-chip and/or off-chip memories for data required to implement the dataflow graph, and these memory allocations are specified in the configuration file. Memory allocations define the type and the number of hardware circuits (functional units, storage, or connectivity components). Main memory (for example, DRAM) may be off-chip memory, and scratchpad memory (for instance, SRAM) is on-chip memory inside a configurable units array. Other memory types for which the memory allocations can be made for various access patterns and layouts include cache, read-only Look-Up Tables (LUTs), serial memories (such as, FIFOs), and register files.

160 160 160 Compilerbinds memory allocations to unplaced memory units and binds operations specified by operation nodes in the dataflow graph to unplaced compute units, and these bindings may be specified in the configuration data. In some implementations, compilerpartitions parts of a dataflow graph into memory subgraphs and compute subgraphs and specifies these subgraphs in the PEF file. A memory subgraph may comprise address calculations leading up to a memory access. A compute subgraph may comprise all other operations in the parent graph. In one implementation, a parent graph is broken up into multiple memory subgraphs and exactly one compute subgraph. In one implementation, the compiler performs the partitioning using reverse dataflow analysis such that inputs to an address used in a memory access recursively flag until compilerreaches either constant values or (bound) loop/pattern iterators. A single parent graph can produce one or more memory subgraphs, depending on how many memory accesses exist in the original loop body. In cases where the same memory addressing logic is shared across multiple memory accesses, address calculation may be duplicated to create multiple memory subgraphs from the same parent graph.

160 Compilergenerates the configuration files with configuration data, such as a bit stream, for the placement positions and the routed data and dataflow control information. In one implementation, this includes assigning coordinates and communication resources of the physical configurable units by placing and routing unplaced units onto the configurable units array while maximizing bandwidth and minimizing latency.

A first example of accelerated deep learning is using a deep learning accelerator implemented in a CGRA to train a neural network. A second example of accelerated deep learning is using the deep learning accelerator to operate a trained neural network to perform inferences. A third example of accelerated deep learning is using the deep learning accelerator to train a neural network and subsequently perform inference with any one or more of the trained neural networks, information from the trained neural network, and a variant of the same.

Examples of neural networks include fully connected neural networks (FCNNs), recurrent neural networks (RNNs), graph neural networks (GNNs), convolutional neural networks (CNNs), graph convolutional networks (GCNs), long short-term memory (LSTM) networks, autoencoders, deep belief networks, and generative adversarial networks (GANs).

An example of training a neural network is determining one or more weights associated with the neural network, such as by back-propagation in a deep learning accelerator. An example of making an inference is using a trained neural network to compute results by processing input data using the weights associated with the trained neural network. As used herein, the term ‘weight’ is an example of a ‘parameter’ as used in various forms of neural network processing. For example, some neural network learning is directed to determining parameters (such as, through back-propagation) that are usable for performing neural network inferences.

A neural network processes data according to a dataflow graph comprising layers of neurons. Example layers of neurons include input layers, hidden layers, and output layers. Stimuli (such as, input data) are received by an input layer of neurons and the computed results of the dataflow graph (for example, output data) are provided by an output layer of neurons. Example hidden layers include rectified linear unit (ReLU) layers, fully connected layers, recurrent layers, graphical network layers, long short-term memory layers, convolutional layers, kernel layers, dropout layers, and pooling layers. A neural network may be conditionally and/or selectively trained. After being trained, a neural network may be conditionally and/or selectively used for inference.

Examples of ICs, or parts of ICs, which may be used as deep learning accelerators, are processors such as central processing unit (CPUs), CGR processor ICs, graphics processing units (GPUs), FPGAs, ASICs, application-specific instruction-set processor (ASIP), and digital signal processors (DSPs). The disclosed technology implements efficient distributed computing by allowing an array of accelerators (for example, reconfigurable processors) attached to separate hosts to directly communicate with each other using buffers.

10 FIG. 1000 984 120 110 100 925 160 1040 1041 1046 1047 1048 1049 1040 986 1041 1042 1043 1044 1045 is a block diagram of an example DAPR system flowfor placement and routing of a unit graph such as unplaced unit graphonto a configurable units array such as the configurable units array, a CGR processor such as CGR processor, or a CGR system such as CGR system. DAPR systemof compilermay include a GNN classifier, a matching subgraph identifier, placement positions assigner, free unit placer, router, and PNR graph updater. GNN classifiermay include GNN. The matching subgraph identifiermay include a topological sorter, a TP sequence aligner, a minimum spanning tree (MST) builder, and an MST sequence aligner.

1040 984 985 986 1060 985 At action 1, GNN classifiermay classify unplaced unit graphagainst the reference graphs and placements databaseusing GNNto identify a nearest matching previously placed reference unit graphof the reference graphs and placements databaseand an associated matching score.

1041 1061 1060 At action 2, the matching subgraph identifiermay identify a matching subgraphof the nearest matching previously placed reference unit graph.

1041 1060 At action 3, the matching subgraph identifiermay determine whether the nearest matching previously placed reference unit graphis a directed acyclic graph.

1060 1042 1060 1060 1060 1042 984 984 984 1042 At action 4, in response to the determination that the nearest matching previously placed reference unit graphis a directed acyclic graph, the topological sortermay perform a topological sort of the nearest matching previously placed reference unit graphto linearize the nearest matching previously placed reference unit graph, produce an associated topological sort nearness metric, and create a topological sort sequence of the nearest matching previously placed reference unit graph. Similarly, the topological sortermay perform a topological sort of the unplaced unit graphto linearize the unplaced unit graph, produce an associated topological sort nearness metric, and to create a topological sort sequence of the unplaced unit graph. The topological sortermay compare the two topological sort sequences.

1043 1061 1060 984 1061 1060 1043 1061 1060 At action 5, the TP sequence alignermay align the two topological sort sequences to find common branches, identify the matching subgraphof the nearest matching previously placed reference unit graph, a matching score, and the remaining unmatched units of the unplaced unit graph, and extract placements of the corresponding configurable units of the matching subgraphof the nearest matching previously placed reference unit graph. The TP sequence alignermay utilize the topological-sort nearness metric and an edit distance, such as Levenshtein distance, to find and identify the matching subgraphof the nearest matching previously placed reference unit graph.

1060 1044 1060 984 1044 1060 984 1060 1060 1060 984 At action 6, in response to the determination that the nearest matching previously placed reference unit graphis a directed cyclic graph (is not a directed acyclic graph), MST buildermay compute an MST of the nearest matching previously placed reference unit graphand compute an MST of the unplaced unit graph. The MST buildermay utilize Prim's algorithm to compute the MSTs and their associated MST sequences of the nearest matching previously placed reference unit graphand the unplaced unit graph. The MST description of the nearest matching previously placed reference unit graphis utilized to reduce the cycle. A depth first search (DFS) of the MST of the nearest matching previously placed reference unit graphlinearizes the MST of the nearest matching previously placed reference unit graphand creates its associated MST sequence. Similarly, a DFS of the MST of the unplaced unit graphlinearizes it and creates its associated sequence.

1045 1061 1060 1061 1060 At action 7, the MST sequence alignermay align the two associated MST sequences to find common branches, identify the matching subgraphof the nearest matching previously placed reference unit graph, and extract placements of the corresponding configurable units of the matching subgraphof the nearest matching previously placed reference unit graph.

1046 1061 1060 984 120 1062 1061 1060 1062 120 At action 8, placement positions assignermay assign the placement position attributes of configurable units of the matching subgraphof the nearest matching previously placed reference unit graphto corresponding placement positions of configurable units of the unplaced unit graphin a configurable units arrayto create an assigned positions unit graph. The assignment of the placement position attributes may include the assignment of the placement position attributes of memory units and compute units of the matching subgraphof the nearest matching previously placed reference unit graphto corresponding placement positions of memory units and compute units of the assigned positions unit graphin the configurable units array.

1047 1062 1062 120 110 1061 1047 1063 At action 9, free unit placermay place the unmatched (remaining unplaced) configurable units of the assigned positions unit graphincluding the unplaced memory units and the unplaced compute units of the assigned positions unit graphonto positions in the configurable units arrayof CGR processor. This process uses the placement position attributes assigned to the memory units and the compute units of the matching subgraph, a legalizer and free unit placerbased on simulated annealing for the remaining unplaced units, and updated constraints to achieve the finalized placement of placed unit graph.

1048 120 1063 1064 1046 1047 1048 987 At action 10, routermay route data and dataflow control information between the placement positions in the configurable units arrayof placed unit graphto create a PNR unit graph. Placement positions assigner, free unit placer, and routermay each generate portions of the PNR information.

926 987 925 165 1064 At action 11, configuration file generatormay receive PNR informationfrom DAPR SYSTEMand generate a configuration filewith configuration data for the placement positions and the routed data and dataflow control information for the PNR unit graph.

170 165 120 120 110 165 981 1064 At action 12, the runtime processesloads the configuration fileonto an instance of the configurable units arrayand causes the configurable units arrayof CGR processorto execute the configuration fileto implement at least the portion of the dataflow graphrepresented by the PNR unit graph.

120 1064 170 1065 1064 110 After the configurable units arraycompletes the execution of the PNR unit graph, runtime processesmay retrieve post-run attributesassociated with the execution of the PNR unit graphfrom CGR processor.

1049 1064 1065 165 985 1049 1065 1065 165 At action 13, the PNR graph updatermay add the PNR unit graphand the post-run attributesassociated with the execution of the configuration fileto a new entry in the reference graphs and placements database. The PNR graph updateraddition may be based on the post-run attributesand a post-run attributes success criterion, where the addition is made when the post-run attributeshave met or exceeded the post-run attributes success criterion. The post-run attributes may include utilization, throughput, and latency numbers associated with the execution of the configuration file. The post-run attributes success criterion may be met or exceeded when the utilization of the execution has met or exceeded a utilization threshold, the throughput of the execution has met or exceeded a throughput threshold, the latency numbers associated with the execution have met or exceeded latency numbers thresholds, or combinations of any of these.

11 FIG. 1100 1100 1100 1100 is a flowchart illustrating an example of a computer-implemented methodfor database driven place and route for coarse-grain reconfigurable architecture (CGRA) systems. For clarity of presentation, the description that follows generally describes methodin the context of the other figures in this description. However, it will be understood that methodcan be performed, for example, by any system, environment, software, and hardware, or a combination of systems, environments, software, and hardware, as appropriate. In some implementations, various steps of methodcan be run in parallel, in combination, in loops, or in any order.

1102 1102 1100 1104 At, an unplaced unit graph representing at least a portion of a dataflow graph of a high-level program is received, by a database driven place and route (DAPR) system. The unplaced unit graph includes configurable units and data connections between the configurable units. The configurable units may include memory units and compute units, and the data connections may be between the memory units and the compute units. From, methodproceeds to.

1104 1104 1100 1106 At, the unplaced unit graph is classified against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database. From, methodproceeds to.

1106 1106 1100 1108 At, Configurable units of the unplaced unit graph are placed onto positions in a configurable units array based on placement position attributes of at least a portion of configurable units of the nearest matching previously placed reference unit graph. From, methodproceeds to.

1108 1108 1100 1110 At, data and dataflow control information are routed between the configurable units of the unplaced unit graph placed onto positions in the configurable units array. From, methodproceeds to.

1110 1110 1100 At, Configuration data is generated that enables the configurable units array to execute at least a portion of the unplaced unit graph. After, methodstops.

12 12 FIGS.A andB 1200 1225 984 120 110 100 1225 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1048 926 170 110 illustrate a sequence diagram of an example database driven place and route systemincluding an iterative database driven place and route systemfor placement and routing of a unit graph such as unplaced unit graphonto a configurable units array such as the configurable units array, a CGR processor such as CGR processor, or a CGR system such as CGR system. As shown, iterative DAPR systemmay include a priority list updater, a priority list selector, a GNN classifier, a remaining unplaced subgraph list updater, a matching subgraph identifier, a placement positions assigner, a placed matching subgraphs List updater, a topologically orderer, a layout identifier, a remaining configuration units identifier, a free unit placer, router, configuration file generator, runtime processes, and CGR processor.

1240 984 1260 1260 984 At action 1, priority list updatermay add an unplaced unit graphto priority list of unplaced graphs. The priority list of unplaced graphsmay be maintained in a priority order. The unplaced unit graphmay represent at least a portion of a dataflow graph of a high-level program. In some embodiments, the priority list may be a max-heap and the priority order may be ordered by the size of each unplaced unit graph in the priority list. The size of each unplaced unit graph may be equal to the number of nodes plus the number of edges of the corresponding unplaced unit graph.

1225 1260 1260 1225 1225 1260 1268 1260 1225 1260 At action 2, iterative DAPR systemmay determine whether the priority list of unplaced graphsis not empty. As part of determining whether the priority listis not empty, iterative DAPR systemmay first determine whether the iteratively selecting, classifying, and determining a particular unplaced graph at the top of the max-heap may be stuck in a loop where no progress is being made. To avoid being stuck in a loop, the number of unsuccessful retries is tracked. When the number of retries exceeds a retry threshold, iterative DAPR systemmay remove each unplaced unit graph from the priority listand add them to the remaining unplaced subgraphs list, which results in the priority listbeing empty. Then iterative DAPR systemmay determine whether the priority list of unplaced graphsis not empty.

1260 1225 In response to the determination that the priority list of unplaced graphsis not empty, iterative DAPR systemmay perform priority list processing including actions 3 through 10.

1241 1261 1260 1260 1261 1260 1261 1260 At action 3, priority list selectormay select a current graphfrom the priority list. The selection may be based on a priority of each graph in the priority list of unplaced graphs. Selecting the current graphfrom the priority listmay also include removing the current graphfrom the priority list.

1225 1261 985 986 1265 1266 1262 985 1263 1261 Iterative DAPR systemmay perform iterative DAPR classification of the current graphagainst reference graphs and placements databaseusing GNNto retrieve a placed matching subgraph of the current graphand an unplaced subgraph of the current graphbased on a nearest matching previously placed reference unit graphof the reference graphs and placements databaseand an associated matching score. Performing iterative DAPR classification of the current graphincludes actions 4 through 7.

1242 1261 985 986 1262 985 1263 At action 4, GNN classifiermay classify the current graphagainst reference graphs and placements databaseusing GNNto identify the nearest matching previously placed reference unit graphof reference graphs and placements databaseand the associated matching score.

1225 1261 1225 1265 1266 1262 985 1263 Iterative DAPR systemperforming iterative DAPR classification of the current graphmay also include iterative DAPR systemretrieving the placed matching subgraph of the current graphand the unplaced subgraph of the current graphbased on the nearest matching previously placed reference unit graphof reference graphs and placements databaseand the associated matching score, which further includes actions 5 through action 7.

1225 1263 1262 At action 5, iterative DAPR systemmay determine whether the matching scoreassociated with the nearest matching previously placed reference unit graphis greater than an acceptance threshold.

1263 1244 1264 1262 At action 6, in response to determining that the associated matching scoreis greater than the acceptance threshold, matching subgraph identifiermay identify a placed matching subgraphof the nearest matching previously placed reference unit graph.

1245 1264 1262 1261 1265 1264 1262 1265 1261 1266 At action 7, placement positions assignermay assign the placement position attributes of configurable units of the placed matching subgraphof the nearest matching previously placed reference unit graphto placement position attributes of configurable units of a corresponding placed matching subgraph of the current graphto create the placed matching subgraph of the current graph. The assignment of the placement position attributes may include the assignment of the placement position attributes of memory units and compute units of the placed matching subgraphof the nearest matching previously placed reference unit graphto corresponding placement positions of memory units and compute units of placed matching subgraph of the current graph. The remaining unplaced configurable units of the current graphcomprise the unplaced subgraph of the current graph.

1225 1261 1225 1265 1266 1260 1267 1268 1263 Iterative DAPR systemperforming iterative DAPR classification of the current graphmay further include iterative DAPR systemprocessing the placed matching subgraph of the current graphand the unplaced subgraph of the current graphto update at least one of the priority list, a placed matching subgraphs list, and a remaining unplaced subgraphs listbased on the associated matching score, which also includes actions 8 through 10.

1225 1263 1263 1263 1265 Iterative DAPR systemmay determine whether the associated matching scoreis greater than an acceptance threshold. In response to determining that the associated matching scoreis greater than the acceptance threshold, actions 8 and 9 are performed. The associated matching scorebeing greater than the acceptance threshold indicates that the placed matching subgraph of the current graphhas been placed.

1246 1265 1267 At action 8, placed matching subgraphs list updatermay add the placed matching subgraph of the current graphto the placed matching subgraphs list.

1240 1266 1260 At action 9, priority list updatermay add the unplaced subgraph of the current graphto the priority list.

1263 1263 1265 In response to determining that the associated matching scoreis less than or equal to the acceptance threshold, action 10 is performed. The associated matching scorebeing less than or equal to the acceptance threshold indicates that the placed matching subgraph of the current graphhas not been placed.

1243 1266 1268 At action 10, remaining unplaced subgraphs list updatermay add the unplaced subgraph of the current graphto the remaining unplaced subgraphs list.

1225 1260 1260 1260 1260 1225 Iterative DAPR systemmay determine whether the priority listof unplaced graphsis empty. In response to the determination that the priority listof unplaced graphsis not empty, iterative DAPR systemmay perform another iteration of priority list processing.

1260 1225 1267 1268 1267 In response to the determination that the priority list of unplaced graphsis empty, iterative DAPR systemmay perform iterative DAPR placement to place configurable units of each placed matching subgraph in the placed matching subgraphs listand configurable units of each unplaced subgraph in the remaining unplaced subgraphs listbased on corresponding placement position attributes of configurable units of each placed matching subgraph in the placed matching subgraphs list. Performing iterative DAPR placement includes performing actions 11 through 14.

1247 1267 At action 11, topologically orderermay order the placed matching subgraphs in the placed matching subgraphs listtopologically using a topological sort algorithm.

1248 1267 1269 1269 120 1267 1248 1269 1269 120 At action 12, layout identifiermay identify a placement layout of the ordered placed matching subgraphs in the placed matching subgraphs listbased on left-to-right and top-to-bottom bounding boxes to create a composite graphwith the configurable units of the composite graphplaced onto positions in the configurable units arraybased on the corresponding placement position attributes of the configurable units of each placed matching subgraph in the placed matching subgraphs list. Layout identifiermay also generate position constraints associated with the composite graphset by the placement positions of the configurable units of the composite graphin the configurable units array.

1249 1270 1268 At action 13, remaining configuration units identifiermay identify remaining configurable unitsto be placed from the union of the configurable units of each unplaced subgraph in the remaining unplaced subgraphs list.

1250 1270 120 1269 1269 120 1250 1263 1250 At action 14, free unit placermay place the remaining configurable unitsto be placed onto positions in the configurable units arraywithin the position constraints associated with the composite graphset by the placement positions of the configurable units of the composite graphin the configurable units array. Free unit placermay also create a placed unit graph. The free unit placermay comprise a simulated annealing placer.

1048 120 1263 1264 1245 1250 1048 1287 1287 1269 120 1270 120 120 1263 At action 15, routermay route data and dataflow control information between the placement positions in configurable units arrayof placed unit graphto create a PNR unit graph. Placement positions assigner, free unit placer, and routermay each generate portions of the PNR information. The PNR informationmay be based on at least the placement positions of the configurable units of the composite graphin the configurable units array, the placement positions of the remaining configurable unitsin the configurable units array, the routed data and dataflow control information between the placement positions in configurable units arrayof placed unit graph.

926 1287 1225 1265 1264 120 120 981 984 At action 16, configuration file generatormay receive PNR informationfrom iterative DAPR systemand generate a configuration filewith configuration data for the placement positions and the routed data and dataflow control information for the PNR unit graph. The configuration data, when loaded onto an instance of a configurable units array, may cause the configurable units arrayto implement at least the portion of the dataflow graphrepresented by the unplaced unit graph.

170 1265 120 120 110 1265 981 1264 At action 17, the runtime processesloads the configuration fileonto an instance of configurable units arrayand causes configurable units arrayof CGR processorto execute the configuration fileto implement at least the portion of the dataflow graphrepresented by the PNR unit graph.

13 FIG. 1300 1300 1300 1300 is a flowchart illustrating an example of a computer-implemented methodfor iterative database driven place and route for coarse-grain reconfigurable architecture (CGRA) systems. For clarity of presentation, the description that follows generally describes methodin the context of the other figures in this description. However, it will be understood that methodcan be performed, for example, by any system, environment, software, and hardware, or a combination of systems, environments, software, and hardware, as appropriate. In some implementations, various steps of methodcan be run in parallel, in combination, in loops, or in any order.

1302 1302 1300 1304 At, an unplaced unit graph is added, by a database driven place and route (DAPR) system, to a priority list, the unplaced unit graph representing at least a portion of a dataflow graph of a high-level program. From, methodproceeds to.

1304 1304 1300 1306 At, a current subgraph of the unplaced unit graph is selected from the priority list. From, methodproceeds to.

1306 1306 1300 1308 At, the current subgraph of the unplaced unit graph is classified against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database. From, methodproceeds to.

1308 1308 1300 1310 At, a placed matching subgraph of the current subgraph of the unplaced unit graph is determined from a placed matching subgraph of the nearest matching previously placed reference unit graph. From, methodproceeds to.

1310 1310 1300 1312 At, selecting, classifying, and determining is iterated, until the priority list is empty. From, methodproceeds to.

1312 1312 1300 1314 At, a placement layout of configurable units of each placed matching subgraph of the unplaced unit graph onto a configurable units array is identified. From, methodproceeds to.

1314 1314 1300 1316 At, data and dataflow control information is routed between the configurable units of each placed matching subgraph of the unplaced unit graph placed onto positions in the configurable units array. From, methodproceeds to.

1316 1316 1300 At, configuration data is generated that enables the configurable units array to execute at least a portion of the unplaced unit graph. After, methodstops.

14 FIG. 1400 1485 1400 1425 1440 1445 1446 1440 1441 1442 1443 1444 is a sequence diagram of an example database construction flowfor constructing a reference graphs and placements databaseof known PNR solutions. As shown, the database construction flowincludes an ab-initio PNR, a graph similarity identifier, a PNR graph updater, and a GNN trainer. The graph similarity identifierincludes a topological sorter, an MST builder, an MST serializer, and a matching graph identifier.

1425 1460 1461 1487 1461 120 1461 120 120 At action 1, the ab-initio PNRmay perform an architecture agnostic PNR algorithm on a reference unit graphto create a PNR reference unit graphand PNR information. The PNR reference unit graphincludes configurable units, data and dataflow control information between the configurable units in a configurable units array such as the configurable units array, and placement position attributes of the corresponding configurable units. The configurable units of the PNR reference unit graphmay include memory units and compute units. The data and dataflow control information may include data and dataflow control information between the memory units and the compute units. The placement position attributes of the corresponding configurable units may include placement position attributes of the memory units and the compute units in the configurable units array. The placement position attributes may include the placement positions of the corresponding memory units and the compute units in the configurable units array.

1440 1461 1462 1463 At action 2, the graph similarity identifiermay linearize the PNR reference unit graphto create a linearized PNR reference unit graphand a similarity matching score.

1440 1461 At action 3, the graph similarity identifiermay determine whether the PNR reference unit graphis a directed acyclic graph.

1461 1441 1461 1461 1462 At action 4, in response to the determination that the PNR reference unit graphis a directed acyclic graph, the topological sortermay perform a topological sort of the PNR reference unit graphto linearize the PNR reference unit graphand create the linearized PNR reference unit graph.

1461 1442 1461 1442 1461 1461 At action 5, in response to the determination that the PNR reference unit graphis a directed cyclic graph (is not a directed acyclic graph), MST buildermay compute an MST of the PNR reference unit graph. The MST buildermay utilize Prim's algorithm to compute the MST of the PNR reference unit graph. The MST description of the PNR reference unit graphis utilized to reduce the cycle.

1443 1461 1461 1462 At action 6, the MST serializermay perform a depth first search (DFS) of the MST of the PNR reference unit graphto linearize the MST of the PNR reference unit graphand create the linearized PNR reference unit graph.

1444 1463 1462 At action 7, matching graph identifiermay determine a similarity matching scorefor the linearized PNR reference unit graph.

1444 1462 1485 1485 1485 1485 The matching graph identifiermay compare the linearized PNR reference unit graphagainst each linearized previously placed reference unit graph in the reference graphs and placements databaseto identify a nearest matching previously placed reference unit graph in the reference graphs and placements databasehaving a higher similarity matching score than each corresponding similarity matching score of each of the other linearized previously placed reference unit graphs in the reference graphs and placements database. Each similarity matching score is found as the ratio of the size of the largest matching subgraph of each corresponding linearized previously placed reference unit graph in the reference graphs and placements databaseto the size of each corresponding linearized previously placed reference unit graph. The size of the largest matching subgraph of a corresponding linearized previously placed reference unit graph is equal to the number of nodes plus the number of edges in the largest matching subgraph, and the size of the corresponding linearized previously placed reference unit graph is equal to the number of nodes plus the number of edges in the corresponding linearized previously placed reference unit graph. Thus, a similarity matching score for a graph will have a value in the range of 0 and 1 inclusive, where a non-overlapping graph will have a similarity score of 0 and a fully overlapping graph will have a value of 1.

926 1487 1425 1465 1461 At action 8, configuration file generatormay receive PNR informationfrom ab-initio PNRand generate a configuration filewith configuration data for the placement positions and the routed data and dataflow control information for the PNR reference unit graph.

170 1465 120 110 120 110 1465 1461 120 110 1465 170 1466 120 110 At action 9, the runtime processesmay load the configuration fileonto an instance of the configurable units arrayof CGR processorand causes the configurable units arrayof CGR processorto execute the configuration fileto implement the PNR reference unit graph. After the configurable units arrayof CGR processorcompletes the execution of the configuration file, runtime processesmay retrieve post-run attributesassociated with the execution from the configurable units arrayof CGR processor.

1445 1461 120 1462 1463 1466 1465 1485 120 1445 1466 1465 1465 1466 1485 1485 At action 10, the PNR graph updatermay add the PNR reference unit graphincluding the placement position attributes of the corresponding configurable units in the configurable units array, the linearized PNR reference unit graph, the similarity matching score, and the post-run attributesassociated with the execution of the configuration fileto a new entry in the reference graphs and placements database. The placement position attributes may include the placement positions (also referred herein as placed coordinates) of the corresponding memory units and the compute units in the configurable units array. The PNR graph updateraddition may be based on the post-run attributesand a post-run attributes success criterion, where the addition is made when the post-run attributeshave met or exceeded the post-run attributes success criterion. The post-run attributes may include utilization, throughput, and latency numbers associated with the execution of the configuration file. The post-run attributes success criterion may be met or exceeded when the utilization of the execution has met or exceeded a utilization threshold, the throughput of the execution has met or exceeded a throughput threshold, the latency numbers associated with the execution have met or exceeded latency numbers thresholds, or combinations of any of these. The post-run attributesand the post-run attributes success criterion may act as a filter for the reference graphs and placements databasethat may ensure that only PNR reference unit graphs that are known to have been successfully placed and routed, and have met or exceeded the post-run attributes success criterion are included in the reference graphs and placements database.

1446 1486 1485 At action 11, GNN trainermay train a GNN to generate a trained GNNusing a table of reference graphs and placements, each reference unit graph in a table of reference graphs and placements, an index of a corresponding nearest matching previously placed reference unit graph entry in the table as a classification training target, and a corresponding matching score as an assessment training target. The table of reference graphs and placements may comprise the reference graphs and placements database. Training may require configuring the graph neural network for each placement graph in the training set.

16 16 FIGS.A andB Training a GNN and the GNN is described in more detail with references to.

1485 1460 1400 1460 1461 1485 1446 1486 1461 1485 In some embodiments, the reference graphs and placements databaseof known PNR solutions can be dynamically constructed or updated during online operation of the DAPR system each time a new reference unit graphis received. After performing actions 1 through 10 of the database construction flowfor the new reference unit graphincluding adding the new PNR reference unit graphto a new entry in the reference graphs and placements database, the GNN trainermay train or retrain a GNN to generate a trained or retrained GNNusing the new PNR reference unit graphin the reference graphs and placements database.

15 FIG. 1500 1500 1500 1500 is a flowchart illustrating an example of a computer-implemented methodfor training a GNN using reference unit graphs and their placement and routing for coarse-grain reconfigurable architecture (CGRA) systems. For clarity of presentation, the description that follows generally describes methodin the context of the other figures in this description. However, it will be understood that methodcan be performed, for example, by any system, environment, software, and hardware, or a combination of systems, environments, software, and hardware, as appropriate. In some implementations, various steps of methodcan be run in parallel, in combination, in loops, or in any order.

1502 1502 1500 1504 At, a graph neural network (GNN) is trained to predict a nearest matching subgraph identifier and a nearest matching score using a plurality of features for each previously placed reference unit graph from a database of previously placed reference unit graphs, and to produce a trained GNN. From, methodproceeds to.

1504 1504 1500 1506 At, an unplaced unit graph representing at least a portion of a dataflow graph of a high-level program is received. From, methodproceeds to.

1506 1506 1500 1508 At, a nearest matching subgraph identifier and a nearest matching score is determined for the unplaced unit graph using the trained GNN. From, methodproceeds to.

1508 1508 1500 1510 At, configurable units of the unplaced unit graph are placed onto positions in a configurable units array according to placement position attributes corresponding to a nearest matching subgraph identified by the nearest matching subgraph identifier to produce placed configurable units of the unplaced unit graph. From, methodproceeds to.

1510 1510 1500 1512 At, data and dataflow control information are routed between the configurable units of the unplaced unit graph placed onto positions in the configurable units array. From, methodproceeds to.

1512 1512 1500 At, configuration data corresponding to the placed configurable units of the unplaced unit graph is generated that enables the configurable units array to implement at least a portion of the unplaced unit graph. After, methodstops.

16 FIG.A 1600 is a block diagram of an example graph neural network (GNN)suitable for training a GNN using placed reference unit graphs and classification of unplaced unit graphs for coarse-grain reconfigurable architecture (CGRA) systems.

1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 As illustrated, graph neural networkincludes an embedding stageA, an aggregation stageB, a classification stageC, and a regressor stageD. The embedding stageA and the aggregation stageB of the graph neural networkmay be configured for specific unit graphs during training and when classifying an unplaced unit graph to identify a nearest matching previously placed reference unit graph and an associated matching score. In contrast, classification stageC and regressor stageD are independent of the unit graph and need not be configured for the unit graph being trained on or being classified.

1600 1602 1602 1610 1620 1630 The embedding stageA includes a branchfor each configuration unit in a unit graph whether a placed reference unit graph used during training or an unplaced unit graph used during classification. Each branchincludes a configuration unit attributes register, a set of embedding tablesand a linear transform module.

1610 The configuration unit attributes registerreceives and stores a set of attributes for each configuration unit in a unit graph. Each attribute may be an index and need not be descriptive. Examples of attributes include a configurable unit type, a dataflow task, an end-to-end (e2e) attribute and a routing length. The configurable unit type specifies the type of configurable unit such as a compute unit, memory unit or switch unit. The dataflow task identifies the task assigned to the configurable unit. The e2e attribute indicates a sink unit's readiness to receive incoming packets end-to-end from the source. The higher the credit, the more spaces the unit will have to receive data. The routing length indicates the traveling latency from sender to receiver.

16 FIG.B 16 FIG.B 16 1620 1610 1620 1620 1620 1620 Referring now toas well asA, each set of embedding tablesincludes a table for each attribute within the attribute register. Within each attribute table a feature vector may be stored for each possible value for that attribute. For example, as shown in the example set of embedding tables illustrated in, if there are three possible configuration unit types three feature vectors would be stored in the configuration unit type embedding tableA. Similarly, if there are 10 possible dataflow tasks, 10 feature vectors would be stored in the dataflow task embedding tableB. Lastly, with 5 possible routing lengths 5 feature vectors would be stored in the routing length embedding tableC. It is appreciated that the depicted embedding tablescould each be a portion of a larger table.

1630 1610 1630 Each of the linear transform modulesmay receive a feature vector for each of the attributes in the attribute register, for example, as a combined feature vector, and generate a composite feature vector therefrom. The length of the composite feature vector may be different than individual or combined attribute feature vectors. In some cases, the linear transform modulesare multi-layer perceptron's.

1602 1620 1630 1620 1630 1602 1602 Each branchmay have the same set of embedding tableswith identical feature vector entries as well at the same linear transform modulewith identical (transformation) weights. Consequently, during training the learning that occurs to the feature vectors stored in the embedding tablesand the weights used in the linear transform moduleof each branchresults in training for every branch.

1600 1640 1650 1660 1640 1640 1650 1660 The aggregation stageB includes a graph layerand multiple message passing layersand a reduction layer. The graph layerreceives the composite feature vector for each configuration unit and stores it in a corresponding node in the graph neural network. The graph layeris also configured with the connectivity information from the unit graph being trained or classified. The message passing layersleverage that connectivity information to exchange and aggregate the composite feature vectors. For example, the composite feature vectors may be exchanged between configuration units that are neighbors within the placement graph and the feature vector with the maximum value may be retained. By conducting m passes of aggregation, each node in the graph neural network will retain the maximum (aggregated) composite feature vector that is within distance m within the graph neural network. The reduction layeraverages all of the aggregated composite feature vectors to produce an average feature vector for the entire (placed reference or unplaced) unit graph.

1600 1670 1685 1685 1485 1685 1670 1630 1620 14 FIG. The classification stageC includes multiple perceptron layers. The perceptron layers produce an identifier of a nearest matching placed reference graphfor the unit graph such as an index of the nearest matching placed reference graphentry in a table of reference graphs and placements. The table of reference graphs and placements, for example, may comprise reference graphs and placements databaseas shown in. The table may contain N entries and an index into the table may have a value between 0 and N−1. During training the classified index of the nearest matching placed reference graphentry is compared to the actual index of the unit graph in the table of reference graphs and placements. The error is backpropagated to update the corresponding weights in the perceptron layers, the linear transform modulesand the entries in the embedding tables. In some cases, initially, before training commences, the weights and embedding table entries may be set to random values.

1600 1672 1685 1685 1672 1630 1620 The regressor stageD includes multiple perceptron layers. The perceptron layers produce a matching score associated with the classified index of the nearest matching placed reference graphentry. During training the classified matching score associated with the classified index of the nearest matching placed reference graphentry is compared with the actual matching score associated with the actual index of the unit graph in the table of reference graphs and placements. The error is backpropagated to update the corresponding weights in the perceptron layers, the linear transform modulesand the entries in the embedding tables.

1600 It should be noted that the depicted graph neural networkleverages learning for the configuration units individually within a unit graph as well as the topology of the unit graph as a whole.

Nodes in a placement graph that may be used for training or estimating may correspond to a set of configurable units.

An embedding stage of the graph neural network and the trained graph neural network may include a branch for each configurable unit of the set of configurable units. Inputs to each branch of the embedding stage may include a set of configuration unit attributes for a configuration unit of the set of configurable units. The set of configuration unit attributes may include one or more of configurable unit type, a dataflow task, an e2e attribute and a routing length. Each branch of the embedding stage may use a set of embedding tables including an embedding table for each configuration unit attribute of the set of configuration unit attributes. Each branch of the embedding stage may generate a composite feature vector from a set of embedding vectors provided by the set of embedding tables used by the branch. The feature vector may be generated using a multi-layer perceptron. The set of embedding tables may include one or more of a configurable unit type table, a dataflow task table, an e2e attribute table and a routing length table.

The graph neural network and the trained graph neural network may include a graph aggregation stage. The graph aggregation stage may determine an aggregated feature vector for each node in the placement graph to produce aggregated feature vectors. The graph aggregation stage may determine the aggregated feature vectors by exchanging messages between each pair of connected nodes in the placement graph. The graph aggregation stage may conduct two or more passes of exchanging messages. The graph aggregation stage may average the aggregated feature vectors to produce an average feature vector for the placement graph. The regressor stage may estimate the throughput and the matching score associated with the nearest matching placed reference graph entry for the placement graph from the average feature vector using a multi-layer perceptron. The training module updates weights within the regressor stage and the embedding stage of the graph neural network using backpropagation.

In some embodiments, the regressor stage may utilize an empirically validated data driven cost model in identifying a matching score of a placement of a placed reference unit graph obtained by the DAPR.

In some embodiments, an adaptive machine learning model for the matching score may be trained based on an existing database of reference graphs and their corresponding throughputs and placements.

The subject matter described in this specification can be implemented to realize one or more of the following advantages. First, by starting from known place and route (PNR) solutions in a database of previously placed reference unit graphs, faster placement of unplaced unit graphs can be achieved at similar throughput and latency than ab-initio PNR solutions. Second, placement and routing of configurable units of an unplaced unit graph based on a database of previously placed reference unit graphs, referred herein as database driven place and route (DAPR), may utilize placement, routing, and post-run attributes information of one or more previously placed reference unit graphs to place at least a portion of the configurable units of the unplaced unit graph, which may reduce the number of configurable units to be placed to the remaining unplaced configurable units of the unplaced unit graph. Third, DAPR may use classification with graph neural networks (GNNs) to find a similarity match between an unplaced unit graph and a previously placed unit graph in the DAPR database of previously placed reference unit graphs. Fourth, these techniques work for both directed cyclic compute graphs and directed acyclic compute graphs. Fifth, the PNR algorithm is architecture agnostic in the global placement and scales well with the size of the network. Sixth, the database contains implicit knowledge of the placement and routing information based on prior ab-initio PNR solutions and utilizing this information may reduce the amount of compile time for mapping data-flow applications onto configurable units arrays, coarse-grained reconfigurable (CGR) type processors, and coarse-grained reconfigurable architecture (CGRA) systems. Empirical measures of compilation of data-flow applications have shown that up to 75% of compile time is dedicated to PNR. As such, the reduction of the amount of compile time achieved by utilizing the DAPR scheme for mapping data-flow applications onto configurable units arrays, CGR type processors, and CGRA systems directly results in a reduction in a portion of the up to 75% of compile time dedicated to PNR. Seventh, the techniques of DAPR may allow potential near real-time compilation of deep neural network (DNN) graphs and task-graphs onto at least one configurable units array, coarse-grained reconfigurable (CGR) type processors, and coarse-grained reconfigurable architecture (CGRA) systems by utilizing an online, ground truth referenced scheme. Eighth, the DAPR scheme has the capacity to implicitly learn globally from multiple compilations, since the CGRA is invariant, and utilize this learned knowledge in future compilations. This learned knowledge may allow the DAPR scheme to continuously improve over time and may result in improved hit-rates, better matching previously placed reference graphs, and higher matching scores during classification of an unplaced unit graph against the DAPR database.

Described implementations of the subject matter can include one or more features, alone or in combination.

For example, in a first implementation, a computer-implemented method for database driven place and route comprising: receiving an unplaced unit graph; classifying the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; placing configurable units of the unplaced unit graph onto positions in a configurable units array based on placement position attributes of at least a portion of configurable units of the nearest matching previously placed reference unit graph; and generating configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph.

A first feature, combinable with any of the following features, wherein classifying further to identify a matching score associated with the nearest matching previously placed reference unit graph, and wherein placing configurable units of the unplaced unit graph onto positions in the configurable units array comprises: determining whether the matching score is greater than an acceptance threshold for the matching score; and in response to determining that the matching score is greater than the acceptance threshold: identifying a matching subgraph of the unplaced unit graph from the nearest matching previously placed reference unit graph; and assigning placement positions of configurable units of the matching subgraph of the unplaced unit graph in the configurable units array according to placement position attributes of corresponding configurable units of at least the portion of configurable units of the nearest matching previously placed reference unit graph. A second feature, combinable with any of the previous or following features, wherein in response to determining that the matching score is greater than the acceptance threshold further comprises: placing unmatched configurable units of the unplaced unit graph onto positions in the configurable units array within position constraints set by assigning the placement positions of the configurable units of the matching subgraph of the unplaced unit graph in the configurable units array. A third feature, combinable with any of the previous or following features, wherein placing configurable units of the unplaced unit graph onto positions in the configurable units array further comprises, in response to determining that the matching score is less than or equal to the acceptance threshold for the matching score: placing the configurable units of the unplaced unit graph onto positions in the configurable units array. A fourth feature, combinable with any of the previous or following features, further comprising: routing data and dataflow control information between the configurable units of the unplaced unit graph after placing the configurable units of the unplaced unit graph onto positions in the configurable units array and before generating the configuration data. A fifth feature, combinable with any of the previous or following features, further comprising: loading the configuration data onto an instance of the configurable units array; executing at least the portion of the unplaced unit graph on the instance of the configurable units array; retrieving post-run attributes associated with executing at least the portion of the unplaced unit graph on the instance of the configurable units array; and adding at least the portion of the unplaced unit graph to the database based on the post-run attributes. A sixth feature, combinable with any of the previous or following features, wherein the post-run attributes comprise utilization, throughput, and latency numbers associated with executing at least the portion of the unplaced unit graph on the instance of the configurable units array. A seventh feature, combinable with any of the previous or following features, wherein the unplaced unit graph comprises a directed acyclic graph. An eighth feature, combinable with any of the previous or following features, wherein the unplaced unit graph comprises a directed cyclic graph. A nineth feature, combinable with any of the previous or following features, wherein the GNN comprises a graph convolutional neural network (GCN). A tenth feature, combinable with any of the previous or following features, wherein the unplaced unit graph represents at least a portion of a dataflow graph of a high-level program. An eleventh feature, combinable with any of the previous or following features, wherein the configurable units of the unplaced unit graph comprise memory units and compute units, and wherein the placement position attributes of at least the portion of the configurable units of the nearest matching previously placed reference unit graph comprise placed positions of the memory units and the compute units in the configurable units array. A twelfth feature, combinable with any of the previous or following features, wherein classifying the unplaced unit graph against the database of previously placed reference unit graphs using the GNN to identify the nearest matching previously placed reference unit graph of the database further comprises: identifying, using an empirically validated data driven cost model, a matching score associated with the nearest matching previously placed reference unit graph. The foregoing and other described implementations can each, optionally, include one or more of the following features:

In a second implementation, a system for database driven place and route, comprising: at least one processor; and one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to: receive an unplaced unit graph; classify the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; place configurable units of the unplaced unit graph onto positions in a configurable units array based on placement position attributes of at least a portion of configurable units of the nearest matching previously placed reference unit graph; and generate configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph.

A first feature, combinable with any of the following features, wherein the programming instructions to classify the unplaced unit graph further to identify a matching score associated with the nearest matching previously placed reference unit graph, and wherein the programming instructions to place configurable units of the unplaced unit graph onto positions in the configurable units array further to: determine whether the matching score is greater than an acceptance threshold for the matching score; and in response to determine that the matching score is greater than the acceptance threshold: identify a matching subgraph of the unplaced unit graph from the nearest matching previously placed reference unit graph; and assign placement positions of configurable units of the matching subgraph of the unplaced unit graph in the configurable units array according to placement position attributes of corresponding configurable units of at least the portion of configurable units of the nearest matching previously placed reference unit graph. A second feature, combinable with any of the previous or following features, wherein in response to determine that the matching score is greater than the acceptance threshold, the programming instructions further to: place unmatched configurable units of the unplaced unit graph onto positions in the configurable units array within position constraints set by assign of the placement positions of the configurable units of the matching subgraph of the unplaced unit graph in the configurable units array. A third feature, combinable with any of the previous or following features, wherein the programming instructions to place configurable units of the unplaced unit graph onto positions in the configurable units array further to, in response to determine that the matching score is less than or equal to the acceptance threshold for the matching score, place the configurable units of the unplaced unit graph onto positions in the configurable units array. A fourth feature, combinable with any of the previous or following features, wherein the programming instructions further to: route data and dataflow control information between the configurable units of the unplaced unit graph after the configurable units of the unplaced unit graph have been placed onto positions in the configurable units array and before the configuration data has been generated. A fifth feature, combinable with any of the previous or following features, wherein the programming instructions further to: load the configuration data onto an instance of the configurable units array; execute at least the portion of the unplaced unit graph on the instance of the configurable units array; retrieve post-run attributes associated with executing at least the portion of the unplaced unit graph on the instance of the configurable units array; and add at least the portion of the unplaced unit graph to the database based on the post-run attributes. A sixth feature, combinable with any of the previous or following features, wherein the post-run attributes comprise utilization, throughput, and latency numbers associated with execution of at least the portion of the unplaced unit graph on the instance of the configurable units array. The foregoing and other described implementations can each, optionally, include one or more of the following features:

In a third implementation, a non-transitory, computer readable-medium storing one or more programming instructions executable by at least one processor to perform operations for database driven place and route comprising: receiving an unplaced unit graph; classifying the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; placing configurable units of the unplaced unit graph onto positions in a configurable units array based on placement position attributes of at least a portion of configurable units of the nearest matching previously placed reference unit graph; and generating configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph.

In a fourth implementation, a computer-implemented method for iterative database driven place and route, comprising: adding an unplaced unit graph to a priority list; selecting a current subgraph of the unplaced unit graph from the priority list; classifying the current subgraph of the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; determining a placed matching subgraph of the current subgraph of the unplaced unit graph from a placed matching subgraph of the nearest matching previously placed reference unit graph; iteratively selecting, classifying, and determining, until the priority list is empty; identifying a placement layout of configurable units of each placed matching subgraph of the unplaced unit graph onto a configurable units array; and generating configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph.

A first feature, combinable with any of the following features, wherein classifying further to identify a matching score associated with the nearest matching previously placed reference unit graph, and wherein determining the placed matching subgraph of the current subgraph of the unplaced unit graph from the placed matching subgraph of the nearest matching previously placed reference unit graph comprises: determining whether the matching score is greater than an acceptance threshold; and in response to determining that the matching score is greater than the acceptance threshold: identifying the placed matching subgraph of the nearest matching previously placed reference unit graph; and assigning placement position attributes of configurable units of the placed matching subgraph of the nearest matching previously placed reference unit graph to placement position attributes of corresponding configurable units of the placed matching subgraph of the current subgraph of the unplaced unit graph. A second feature, combinable with any of the previous or following features, wherein in response to determining that the matching score is greater than the acceptance threshold further comprises: adding an unplaced subgraph of the current subgraph of the unplaced unit graph to the priority list, wherein the unplaced subgraph of the current subgraph of the unplaced unit graph comprises remaining unplaced configurable units of the current subgraph of the unplaced unit graph; and adding the placed matching subgraph of the current subgraph of the unplaced unit graph to a list of placed matching subgraphs. A third feature, combinable with any of the previous or following features, wherein in response to determining that the matching score is less than or equal to the acceptance threshold: adding an unplaced subgraph of the current subgraph of the unplaced unit graph to a list of remaining unplaced subgraphs, wherein the unplaced subgraph of the current subgraph of the unplaced unit graph comprises remaining unplaced configurable units of the current subgraph of the unplaced unit graph. A fourth feature, combinable with any of the previous or following features, wherein selecting the current subgraph of the unplaced unit graph from the priority list further comprises removing the current subgraph of the unplaced unit graph from the priority list. A fifth feature, combinable with any of the previous or following features, further comprising ordering each placed matching subgraph in a list of placed matching subgraphs topologically using a topological sort algorithm, prior to identifying the placement layout of the configurable units of each placed matching subgraph onto the configurable units array. A sixth feature, combinable with any of the previous or following features, wherein identifying the placement layout of the configurable units of each placed matching subgraph onto the configurable units array comprises: generating a composite graph with configurable units of the composite graph placed onto positions in the configurable units array according to placement position attributes of the configurable units of each placed matching subgraph of the nearest matching previously placed reference unit graph. A seventh feature, combinable with any of the previous or following features, further comprising: combining configurable units of each remaining unplaced subgraph of the unplaced unit graph of a list of remaining unplaced subgraphs of the unplaced unit graph into a union of the configurable units of each remaining unplaced subgraph of the unplaced unit graph; identifying remaining configurable units to be placed from the union of the configurable units of each remaining unplaced subgraph of the unplaced unit graph; and placing the remaining configurable units to be placed onto positions in the configurable units array within position constraints set by the configurable units of the composite graph placed onto positions in the configurable units array. An eighth feature, combinable with any of the previous or following features, wherein placing the remaining configurable units further comprises placing the remaining configurable units to be placed onto positions in the configurable units array using simulated annealing. A nineth feature, combinable with any of the previous or following features, wherein the unplaced unit graph represents at least a portion of a dataflow graph of a high-level program. A tenth feature, combinable with any of the previous or following features, further comprising, prior to identifying the matching score associated with the nearest matching previously placed reference unit graph: training an adaptive machine learning model for predicting the matching score based on an existing database of reference graphs and their corresponding throughputs and placements, and to produce a trained adaptive machine learning model, wherein identifying the matching score associated with the nearest matching previously placed reference unit graph utilizes the trained adaptive machine learning model to predict the matching score associated with the nearest matching previously placed reference unit graph. An eleventh feature, combinable with any of the previous or following features, wherein the priority list is a max-heap ordered by size of each unplaced subgraph of the unplaced unit graph in the priority list, and wherein the size of each unplaced subgraph is equal to the number of nodes plus the number of edges of the unplaced subgraph. A twelfth feature, combinable with any of the previous or following features, wherein the priority list is a max-heap, and wherein when a number of retries for iteratively selecting, classifying, and determining a particular unplaced subgraph at the top of the max-heap exceeds a retry threshold: adding each unplaced subgraph of the unplaced unit graph in the priority list to a list of remaining unplaced subgraphs of the unplaced unit graph to be placed by a free unit placer; and setting the priority list to empty. In a fifth implementation, system for iterative database driven place and route, comprising: at least one processor; and one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to: add an unplaced unit graph to a priority list; select a current subgraph of the unplaced unit graph from the priority list; classify the current subgraph of the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; determine a placed matching subgraph of the current subgraph of the unplaced unit graph from a placed matching subgraph of the nearest matching previously placed reference unit graph; iteratively select, classify, and determine, until the priority list is empty; identify a placement layout of configurable units of each placed matching subgraph of the unplaced unit graph onto a configurable units array; and generate configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph. The foregoing and other described implementations can each, optionally, include one or more of the following features:

A first feature, combinable with any of the following features, wherein the programming instructions to classify further to identify a matching score associated with the nearest matching previously placed reference unit graph, and wherein the programming instructions to determine the placed matching subgraph of the current subgraph of the unplaced unit graph from the placed matching subgraph of the nearest matching previously placed reference unit graph further to: determine whether the matching score is greater than an acceptance threshold; and in response to determine that the matching score is greater than the acceptance threshold: identify the placed matching subgraph of the nearest matching previously placed reference unit graph; and assign placement position attributes of configurable units of the placed matching subgraph of the nearest matching previously placed reference unit graph to placement position attributes of corresponding configurable units of the placed matching subgraph of the current subgraph of the unplaced unit graph. A second feature, combinable with any of the previous or following features, wherein in response to determine that the matching score is greater than the acceptance threshold, the programming instructions further to: add an unplaced subgraph of the current subgraph of the unplaced unit graph to the priority list, wherein the unplaced subgraph of the current subgraph of the unplaced unit graph comprises remaining unplaced configurable units of the current subgraph of the unplaced unit graph; and add the placed matching subgraph of the current subgraph of the unplaced unit graph to a list of placed matching subgraphs. A third feature, combinable with any of the previous or following features, wherein in response to determine that the matching score is less than or equal to the acceptance threshold, the programming instructions further to: add an unplaced subgraph of the current subgraph of the unplaced unit graph to a list of remaining unplaced subgraphs, wherein the unplaced subgraph of the current subgraph of the unplaced unit graph comprises remaining unplaced configurable units of the current subgraph of the unplaced unit graph. A fourth feature, combinable with any of the previous or following features, wherein the programming instructions to select the current subgraph of the unplaced unit graph from the priority list further to remove the current subgraph of the unplaced unit graph from the priority list. A fifth feature, combinable with any of the previous or following features, wherein the programming instructions further to order each placed matching subgraph in a list of placed matching subgraphs topologically using a topological sort algorithm, prior to identifying the placement layout of the configurable units of each placed matching subgraph onto the configurable units array. A sixth feature, combinable with any of the previous or following features, wherein the programming instructions to identify the placement layout of the configurable units of each placed matching subgraph onto the configurable units array further to: generate a composite graph with configurable units of the composite graph placed onto positions in the configurable units array according to placement position attributes of the configurable units of each placed matching subgraph of the nearest matching previously placed reference unit graph. A seventh feature, combinable with any of the previous or following features, wherein the programming instructions further to: combine configurable units of each remaining unplaced subgraph of the unplaced unit graph of a list of remaining unplaced subgraphs of the unplaced unit graph into a union of the configurable units of each remaining unplaced subgraph of the unplaced unit graph; identify remaining configurable units to be placed from the union of the configurable units of each remaining unplaced subgraph of the unplaced unit graph; and place the remaining configurable units to be placed onto positions in the configurable units array within position constraints set by the configurable units of the composite graph placed onto positions in the configurable units array. An eighth feature, combinable with any of the previous or following features, wherein the programming instructions to place the remaining configurable units further to place the remaining configurable units to be placed onto positions in the configurable units array using simulated annealing. A nineth feature, combinable with any of the previous or following features, wherein the unplaced unit graph represents at least a portion of a dataflow graph of a high-level program. In a sixth implementation, a non-transitory, computer readable-medium storing one or more programming instructions executable by at least one processor to perform operations for iterative database driven place and route, comprising: adding an unplaced unit graph to a priority list; selecting a current subgraph of the unplaced unit graph from the priority list; classifying the current subgraph of the unplaced unit graph against a database of previously placed reference unit graphs using a graph neural network (GNN) to identify a nearest matching previously placed reference unit graph of the database; determining a placed matching subgraph of the current subgraph of the unplaced unit graph from a placed matching subgraph of the nearest matching previously placed reference unit graph; iteratively selecting, classifying, and determining, until the priority list is empty; identifying a placement layout of configurable units of each placed matching subgraph of the unplaced unit graph onto a configurable units array; and generating configuration data that enables the configurable units array to execute at least a portion of the unplaced unit graph. In a seventh implementation, a computer-implemented method for training a graph neural network for database driven place and route, comprising: training a graph neural network (GNN) to predict a nearest matching subgraph identifier and a nearest matching score using a plurality of features for each previously placed reference unit graph from a database of previously placed reference unit graphs, and to produce a trained GNN; receiving an unplaced unit graph; determining a nearest matching subgraph identifier and a nearest matching score for the unplaced unit graph using the trained GNN; placing configurable units of the unplaced unit graph onto positions in a configurable units array according to placement position attributes corresponding to a nearest matching subgraph identified by the nearest matching subgraph identifier to produce placed configurable units of the unplaced unit graph; and generating configuration data corresponding to the placed configurable units of the unplaced unit graph that enables the configurable units array to implement at least a portion of the unplaced unit graph. The foregoing and other described implementations can each, optionally, include one or more of the following features:

A first feature, combinable with any of the following features, wherein training the GNN further comprises using each corresponding nearest matching subgraph identifier and nearest matching score as training targets to produce the trained GNN. A second feature, combinable with any of the previous or following features, wherein nodes in a unit graph used for training or placing correspond to a set of configurable units. A third feature, combinable with any of the previous or following features, wherein an embedding stage of the GNN and the trained GNN comprises a branch for each configurable unit of a set of configurable units, wherein inputs to each branch of the embedding stage comprise a set of configuration unit attributes for a configuration unit of the set of configurable units, wherein the set of configuration unit attributes comprises one or more of configurable unit type, a dataflow task, an end-to-end (e2e) attribute, and a routing length, wherein each branch of the embedding stage uses a set of embedding tables comprising an embedding table for each configuration unit attribute of the set of configuration unit attributes, wherein each branch of the embedding stage generates a composite feature vector from a set of embedding vectors provided by the set of embedding tables used by the branch, wherein the composite feature vector is generated using a multi-layer perceptron, and wherein the set of embedding tables comprises one or more of a configurable unit type table, a dataflow task table, an e2e attribute table, and a routing length table. A fourth feature, combinable with any of the previous or following features, wherein the GNN and the trained GNN comprise a graph aggregation stage, wherein the graph aggregation stage determines an aggregated feature vector for each node in a unit graph to produce aggregated feature vectors, wherein the graph aggregation stage determines the aggregated feature vectors by exchanging messages between each pair of connected nodes in the unit graph, wherein the graph aggregation stage conducts two or more passes of exchanging messages, and wherein the graph aggregation stage averages the aggregated feature vectors to produce an average feature vector for the unit graph. A fifth feature, combinable with any of the previous or following features, wherein a classification stage predicts a nearest matching subgraph identifier for a unit graph from an average feature vector using a multi-layer perceptron, and wherein a regressor stage predicts a nearest matching score for the unit graph from the average feature vector using a multi-layer perceptron. A sixth feature, combinable with any of the previous or following features, wherein weights within a classification stage, a regressor stage, and an embedding stage of the GNN are updated using backpropagation. A seventh feature, combinable with any of the previous or following features, wherein construction of the database of previously placed reference unit graphs comprises: placing and routing, using an ab-initio architecture agnostic place and route algorithm, configurable units of an unplaced reference unit graph onto positions in a configurable units array, wherein placing and routing associates the unplaced reference unit graph to a placed and routed reference unit graph; generating configuration data for placement positions and routed data and dataflow control information for the placed and routed reference unit graph; loading the configuration data onto an instance of the configurable units array of a course-grained reconfigurable processor; executing the placed and routed reference unit graph on the instance of the configurable units array of the course-grained reconfigurable processor; retrieving post-run attributes associated with executing the placed and routed reference unit graph on the instance of the configurable units array; and adding the placed and routed reference unit graph to a new entry in the database of previously placed reference unit graphs including placement position attributes of corresponding configurable units in the placed and routed reference unit graph and the post-run attributes, wherein entries in the database of previously placed reference unit graphs form training data for training the GNN. In an eighth implementation, a system for training a graph neural network for database driven place and route, comprising: at least one processor; and one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to: train a graph neural network (GNN) to predict a nearest matching subgraph identifier and a nearest matching score using a plurality of features for each previously placed reference unit graph from a database of previously placed reference unit graphs, and to produce a trained GNN; receive an unplaced unit graph; determine a nearest matching subgraph identifier and a nearest matching score for the unplaced unit graph using the trained GNN; place configurable units of the unplaced unit graph onto positions in a configurable units array according to placement position attributes corresponding to a nearest matching subgraph identified by the nearest matching subgraph identifier to produce placed configurable units of the unplaced unit graph; and generate configuration data corresponding to the placed configurable units of the unplaced unit graph that enables the configurable units array to implement at least a portion of the unplaced unit graph. The foregoing and other described implementations can each, optionally, include one or more of the following features:

A first feature, combinable with any of the following features, wherein the programming instructions to train the GNN further to use each corresponding nearest matching subgraph identifier and nearest matching score as training targets to produce the trained GNN. A second feature, combinable with any of the previous or following features, wherein nodes in a unit graph used to train or place correspond to a set of configurable units. A third feature, combinable with any of the previous or following features, wherein an embedding stage of the GNN and the trained GNN comprises a branch for each configurable unit of a set of configurable units, wherein inputs to each branch of the embedding stage comprise a set of configuration unit attributes for a configuration unit of the set of configurable units, wherein the set of configuration unit attributes comprises one or more of configurable unit type, a dataflow task, an end-to-end (e2e) attribute, and a routing length, wherein each branch of the embedding stage uses a set of embedding tables comprising an embedding table for each configuration unit attribute of the set of configuration unit attributes, wherein each branch of the embedding stage generates a composite feature vector from a set of embedding vectors provided by the set of embedding tables used by the branch, wherein the composite feature vector is generated using a multi-layer perceptron, and wherein the set of embedding tables comprises one or more of a configurable unit type table, a dataflow task table, an e2e attribute table, and a routing length table. A fourth feature, combinable with any of the previous or following features, wherein the GNN and the trained GNN comprise a graph aggregation stage, wherein the graph aggregation stage determines an aggregated feature vector for each node in a unit graph to produce aggregated feature vectors, wherein the graph aggregation stage determines the aggregated feature vectors by exchanging messages between each pair of connected nodes in the unit graph, wherein the graph aggregation stage conducts two or more passes of exchanging messages, and wherein the graph aggregation stage averages the aggregated feature vectors to produce an average feature vector for the unit graph. A fifth feature, combinable with any of the previous or following features, wherein a classification stage predicts a nearest matching subgraph identifier for a unit graph from an average feature vector using a multi-layer perceptron, and wherein a regressor stage predicts a nearest matching score for the unit graph from the average feature vector using a multi-layer perceptron. A sixth feature, combinable with any of the previous or following features, wherein weights within a classification stage, a regressor stage, and an embedding stage of the GNN are updated using backpropagation. In a nineth implementation, a non-transitory, computer readable-medium storing one or more programming instructions executable by at least one processor to perform operations for training a graph neural network for database driven place and route, comprising: training a graph neural network (GNN) to predict a nearest matching subgraph identifier and a nearest matching score using a plurality of features for each previously placed reference unit graph from a database of previously placed reference unit graphs, and to produce a trained GNN; receiving an unplaced unit graph; determining a nearest matching subgraph identifier and a nearest matching score for the unplaced unit graph using the trained GNN; placing configurable units of the unplaced unit graph onto positions in a configurable units array according to placement position attributes corresponding to a nearest matching subgraph identified by the nearest matching subgraph identifier to produce placed configurable units of the unplaced unit graph; and generating configuration data corresponding to the placed configurable units of the unplaced unit graph that enables the configurable units array to implement at least a portion of the unplaced unit graph The foregoing and other described implementations can each, optionally, include one or more of the following features:

A first feature, combinable with any of the following features, wherein training the GNN further comprises using each corresponding nearest matching subgraph identifier and nearest matching score as training targets to produce the trained GNN. A second feature, combinable with any of the previous or following features, wherein nodes in a unit graph used for training or placing correspond to a set of configurable units. A third feature, combinable with any of the previous or following features, wherein an embedding stage of the GNN and the trained GNN comprises a branch for each configurable unit of a set of configurable units, wherein inputs to each branch of the embedding stage comprise a set of configuration unit attributes for a configuration unit of the set of configurable units, wherein the set of configuration unit attributes comprises one or more of configurable unit type, a dataflow task, an end-to-end (e2e) attribute, and a routing length, wherein each branch of the embedding stage uses a set of embedding tables comprising an embedding table for each configuration unit attribute of the set of configuration unit attributes, wherein each branch of the embedding stage generates a composite feature vector from a set of embedding vectors provided by the set of embedding tables used by the branch, wherein the composite feature vector is generated using a multi-layer perceptron, and wherein the set of embedding tables comprises one or more of a configurable unit type table, a dataflow task table, an e2e attribute table, and a routing length table. A fourth feature, combinable with any of the previous or following features, wherein the GNN and the trained GNN comprise a graph aggregation stage, wherein the graph aggregation stage determines an aggregated feature vector for each node in a unit graph to produce aggregated feature vectors, wherein the graph aggregation stage determines the aggregated feature vectors by exchanging messages between each pair of connected nodes in the unit graph, wherein the graph aggregation stage conducts two or more passes of exchanging messages, and wherein the graph aggregation stage averages the aggregated feature vectors to produce an average feature vector for the unit graph. A fifth feature, combinable with any of the previous or following features, wherein a classification stage predicts a nearest matching subgraph identifier for a unit graph from an average feature vector using a multi-layer perceptron, and wherein a regressor stage predicts a nearest matching score for the unit graph from the average feature vector using a multi-layer perceptron. The foregoing and other described implementations can each, optionally, include one or more of the following features:

The preceding description is presented to enable the making and use of the technology disclosed. Various modifications, alterations, and permutations of the disclosed implementations can be made and will be readily apparent to those of ordinary skill in the art, and the general principles defined can be applied to other implementations and applications, without departing from the scope of the present disclosure. In some instances, one or more technical details that are unnecessary to obtain an understanding of the described subject matter and that are within the skill of one of ordinary skill in the art may be omitted so as to not obscure one or more described implementations. The present disclosure is not intended to be limited to the described or illustrated implementations, but to be accorded the widest scope consistent with the described principles and features.

While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventive concept or on the scope of what can be claimed, but rather as descriptions of features that can be specific to particular implementations of particular inventive concepts. Certain features that are described in this specification in the context of separate implementations can also be implemented, in combination, in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations, separately, or in any sub-combination. Moreover, although previously described features can be described as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can, in some cases, be excised from the combination, and the claimed combination can be directed to a sub-combination or variation of a sub-combination.

Particular implementations of the subject matter have been described. Other implementations, alterations, and permutations of the described implementations are within the scope of the following claims as will be apparent to those skilled in the art. While operations are depicted in the drawings or claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed (some operations can be considered optional), to achieve desirable results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) can be advantageous and performed as deemed appropriate.

Moreover, the separation or integration of various system modules and components in the previously described implementations should not be understood as requiring such separation or integration in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Accordingly, the previously described example implementations do not define or constrain the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Furthermore, any claimed implementation is considered to be applicable to at least a computer-implemented method; a non-transitory, computer-readable medium storing computer-readable instructions to perform the computer-implemented method; and a computer system comprising a computer memory interoperably coupled with a hardware processor configured to perform the computer-implemented method or the instructions stored on the non-transitory, computer-readable medium.