Semiconductor memory device

This application is a Continuation application of U.S. application Ser. No. 17/841,362, filed Jun. 15, 2022, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-185721, filed Nov. 15, 2021, the entire contents of both of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor memory device.

A NAND-type flash memory is known as a semiconductor memory device.

In general, according to one embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the first memory cell array in a first direction; a third memory cell array arranged adjacent to the first memory cell array in a second direction intersecting with the first direction; a fourth memory cell array arranged above the third memory cell array in the first direction and arranged adjacent to the second memory cell array in the second direction; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.

Hereinafter, embodiments will be described with reference to the drawings. Note that, in the following description, constituent elements having substantially the same functions and configurations are denoted by the same reference numerals. Repetitive description may be omitted if not needed. In addition, each embodiment described below illustrates a device and a method for embodying a technical idea of the embodiment. The technical idea of the embodiment does not specify the material, shape, structure, arrangement, and the like of components described below. Various modifications can be made to the technical idea of the embodiment without departing from the gist of the invention. Such embodiments and modifications of the embodiments are included in the invention described in claims and the equivalent scope thereof.

A semiconductor memory device according to a first embodiment will be described.

1.1 Overall Configuration of Semiconductor Memory Device

1 1 1 FIG. 1 FIG. 1 FIG. First, an example of the overall configuration of a semiconductor memory devicewill be described with reference to.is a block diagram illustrating the overall configuration of the semiconductor memory device. Note that some of couplings between respective constituent elements are indicated by arrow lines in. However, couplings between the constituent elements are not limited thereto.

1 The semiconductor memory deviceis, for example, a three-dimensional (3D) stacked NAND-type flash memory. The 3D stacked NAND-type flash memory includes a plurality of non-volatile memory cell transistors three-dimensionally arranged on a semiconductor substrate.

1 FIG. 1 10 20 10 20 10 1 10 20 10 20 As illustrated in, the semiconductor memory deviceincludes a plurality of array chipsand a circuit chip. The array chipis a chip provided with arrays of non-volatile memory cell transistors. The circuit chipis a chip provided with circuits that controls the array chips. The semiconductor memory deviceaccording to the present embodiment is formed by bonding the plurality of array chipsand the circuit chip. Hereinafter, unless the chip is limited to the array chipor the circuit chip, it is simply referred to as a “chip”.

1 FIG. 1 10 1 10 2 10 10 1 10 2 10 In the example of, the semiconductor memory deviceincludes two array chips_and_. Note that the number of array chipsmay be three or more. Hereinafter, unless the array chip is limited to the array chip_or_, it is referred to as the array chip.

10 11 11 10 1 11 1 11 3 10 2 11 2 11 4 10 11 11 1 11 2 11 3 11 4 11 1 FIG. Each array chipincludes a plurality of memory cell arrays. The memory cell arrayis a region in which non-volatile memory cell transistors are three-dimensionally arranged. In the example of, the array chip_includes memory cell arrays_and_. The array chip_includes memory cell arrays_and_. Note that each array chipmay include three or more memory cell arrays. Hereinafter, unless the memory cell array is limited to the memory cell array_,_,_, or_, it is referred to as the memory cell array.

20 21 22 23 24 1 23 23 24 24 23 23 23 24 24 24 1 FIG. a b a b a b a b The circuit chipincludes a sequencer, a voltage generator, a plurality of row decoders, and a plurality of sense amplifiers. In the example of, the semiconductor memory deviceincludes two row decodersand, and two sense amplifiersand. Hereinafter, unless the row decoder is limited to the row decoderor, it is referred to as the row decoder. Unless the sense amplifier is limited to the sense amplifieror, it is referred to as the sense amplifier.

21 1 21 22 23 23 24 24 21 22 23 23 24 24 21 1 21 a b a b a b a b The sequenceris a circuit that performs control of the semiconductor memory device. The sequenceris coupled to the voltage generator, the row decodersand, and the sense amplifiersand. The sequencercontrols the voltage generator, the row decodersand, and the sense amplifiersand. In addition, the sequencercontrols the overall operation of the semiconductor memory devicein accordance with the control of an external controller. More specifically, the sequencerexecutes a write operation, a read operation, an erase operation, and the like.

22 22 23 23 24 24 22 23 23 24 24 a b a b a b a b The voltage generatoris a circuit that generates voltages used for the write operation, the read operation, the erase operation, and the like. The voltage generatoris coupled to the row decodersand, the sense amplifiersand, and the like. The voltage generatorsupplies voltages to the row decodersand, the sense amplifiersand, and the like.

23 11 23 22 11 23 11 The row decoderis a circuit that performs decoding of row addresses. The row address is an address signal that designates interconnects of the memory cell arrayin a row direction. The address signal is included in a write instruction, a read instruction, an erase instruction, and the like received from the external controller. The row decodersupplies the voltages applied from the voltage generatorto the memory cell arraysbased on the decoding result of the row address. In the present embodiment, one row decoderis provided for two memory cell arrays.

23 11 1 11 2 23 11 3 11 4 a b For example, the row decoderis commonly coupled to the memory cell arrays_and_via a plurality of word lines WLa, and a plurality of selection gate lines SGDa and SGSa. Similarly, the row decoderis commonly coupled to the memory cell arrays_and_via a plurality of word lines WLb, and a plurality of selection gate lines SGDb and SGSb. The word lines WLa and WLb are interconnects used for controlling the memory cell transistors. The selection gate lines SGDa, SGDb, SGSa, and SGSb are interconnects used for selecting string units SU.

11 1 11 2 11 1 11 2 23 11 1 11 2 23 11 1 11 2 23 a a a. More specifically, the memory cell array_and the memory cell array_share the word lines WLa, and the selection gate lines SGDa and SGSa. That is, the word lines WLa of the memory cell array_and the word lines WLa of the memory cell array_are commonly coupled to the row decoder. Similarly, the selection gate lines SGDa of the memory cell array_and the selection gate lines SGDa of the memory cell array_are commonly coupled to the row decoder. In addition, the selection gate lines SGSa of the memory cell array_and the selection gate lines SGSa of the memory cell array_are commonly coupled to the row decoder

11 3 11 4 11 3 11 4 23 11 3 11 4 23 11 3 11 4 23 b b b. Similarly, the memory cell array_and the memory cell array_share the word lines WLb, and the selection gate lines SGDb and SGSb. That is, the word lines WLb of the memory cell array_and the word lines WLb of the memory cell array_are commonly coupled to the row decoder. Similarly, the selection gate lines SGDb of the memory cell array_and the selection gate lines SGDb of the memory cell array_are commonly coupled to the row decoder. In addition, the selection gate lines SGSb of the memory cell array_and the selection gate lines SGSb of the memory cell array_are commonly coupled to the row decoder

24 24 11 24 11 24 11 The sense amplifieris a circuit that performs writing and reading of data. The sense amplifiersenses data read from the corresponding memory cell arraysduring the read operation. In addition, the sense amplifiersupplies voltages corresponding to write data to the memory cell arraysduring the write operation. In the present embodiment, one sense amplifieris provided for two memory cell arrays.

24 11 1 11 4 24 11 2 11 3 a b The sense amplifieris commonly coupled to the memory cell arrays_and_via a plurality of bit lines BLa. Similarly, the sense amplifieris commonly coupled to the memory cell arrays_and_via a plurality of bit lines BLb.

11 1 11 4 11 1 11 4 24 11 2 11 3 11 2 11 3 24 a b. More specifically, the memory cell array_and the memory cell array_share the bit lines BLa. That is, the bit lines BLa of the memory cell array_and the bit lines BLa of the memory cell array_are commonly coupled to the sense amplifier. Similarly, the memory cell array_and the memory cell array_share the bit lines BLb. That is, the bit lines BLb of the memory cell array_and the bit lines BLb of the memory cell array_are commonly coupled to the sense amplifier

11 11 11 1 0 1 1 1 11 2 0 2 1 2 11 3 0 3 1 3 11 4 0 4 1 4 11 1 FIG. Next, the internal configuration of the memory cell arraywill be described. The memory cell arrayincludes a plurality of blocks BLK. The block BLK is, for example, a set of a plurality of memory cell transistors from which data is collectively erased. The plurality of memory cell transistors in the block BLK are associated with rows and columns. In the example of, the memory cell array_includes a BLK_, a BLK_, . . . . The memory cell array_includes a BLK_, a BLK_, . . . . The memory cell array_includes a BLK_, a BLK_, . . . . The memory cell array_includes a BLK_, a BLK_, . . . . Hereinafter, unless the block is limited to which block of which memory cell arrayit is, it is referred to as the block BLK.

1 FIG. 0 3 0 1 0 1 1 1 2 1 3 1 0 2 0 2 1 2 2 2 3 2 0 3 0 3 1 3 2 3 3 3 0 4 0 4 1 4 2 4 3 4 11 The block BLK includes a plurality of string units SU. The string unit SU is, for example, a set of a plurality of NAND strings that are collectively selected in the write operation or the read operation. The NAND string includes a set of a plurality of memory cell transistors that are coupled in series. In the example of, each block BLK includes four string units SUto SU. More specifically, for example, the block BLK_includes four string units SU_, SU_, SU_, and SU_. The block BLK_includes four string units SU_, SU_, SU_, and SU_. The block BLK_includes four string units SU_, SU_, SU_, and SU_. The block BLK_includes four string units SU_, SU_, SU_, and SU_. Hereinafter, unless the string unit is limited to which string unit of which memory cell arrayit is, it is referred to as the string unit SU.

11 11 Note that the number of blocks BLK in the memory cell arrayand the number of string units SU in the block BLK are freely set. The circuit configuration of the memory cell arraywill be described later.

1.2 Circuit Configuration of Memory Cell Array

11 1 11 4 11 1 11 4 2 FIG. 2 FIG. Next, an example of the circuit configuration of the memory cell arrays_to_will be described with reference to.is a circuit diagram of the memory cell arrays_to_.

2 FIG. As illustrated in, the string unit SU includes a plurality of NAND strings NS.

1 2 0 4 2 FIG. The NAND string NS includes a plurality of memory cell transistors MC, and selection transistors STand ST. In the example of, the NAND string NS includes five memory cell transistors MCto MC. Note that the number of memory cell transistors MC is freely set.

The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be of a metal-oxide-nitride-oxide-silicon (MONOS) type, or of a floating gate (FG) type. In the MONOS type, an insulating layer is used as the charge storage layer. In the FG type, a conductive layer is used as the charge storage layer. Hereinafter, a case will be described where the memory cell transistor MC is of the MONOS type.

1 2 1 2 1 2 The selection transistors STand STare used for selecting the string units SU during various operations. The number of selection transistors STand STare freely set. It is sufficient that one or more selection transistors STand one or more selection transistors STare included in the NAND string NS.

1 2 2 0 1 2 3 4 1 2 0 1 2 3 4 1 1 2 2 FIG. In each NAND string NS, current paths of the memory cell transistors MC, and current paths of the selection transistors STand STare coupled in series. In the example of, the selection transistor ST, the memory cell transistors MC, MC, MC, MC, and MC, and the selection transistor STare arranged in this order from the lower side toward the upper side in the drawing. The current paths are coupled in series. In other words, the selection transistor ST, the memory cell transistors MC, MC, MC, MC, and MC, and the selection transistor STare coupled in this order from a source line SL to bit lines BL. A drain of the selection transistor STis coupled to any of the bit lines BL. A source of the selection transistor STis coupled to the source line SL.

1 1 11 1 11 2 FIG. In the string unit SU, drains of a plurality of selection transistors STare coupled to different bit lines BL. In the example of, in the string unit SU, drains of the selection transistors STof n+1 (n being an integer of 0 or more) NAND strings NS are coupled to the respective n+1 bit lines BL. In each string unit SU of two memory cell arrays, a drain of one selection transistor STis commonly coupled to one bit line BL. That is, the two memory cell arraysshare the bit lines BL.

1 11 1 1 11 4 0 1 0 1 3 1 1 0 4 3 4 0 1 11 2 1 11 3 0 More specifically, n+1 selection transistors STof each string unit SU of the memory cell array_and n+1 selection transistors STof each string unit SU of the memory cell array_are commonly coupled to the respective n+1 bit lines BLato BLa(n). For example, a drain of one selection transistor STof each of the string units SU_to SU_and a drain of one selection transistor STof each of the string units SU_to SU_are commonly coupled to the bit line BLa. Similarly, n+1 selection transistors STof each string unit SU of the memory cell array_and n+1 selection transistors STof each string unit SU of the memory cell array_are commonly coupled to the respective n+1 bit lines BLbto BLb(n).

0 4 11 1 0 4 11 2 0 4 0 1 0 2 0 0 0 1 4 1 4 0 1 0 2 11 1 11 2 Control gates of a plurality of memory cell transistors MCto MCincluded in one block BLK of the memory cell array_and control gates of a plurality of memory cell transistors MCto MCincluded in one block BLK of the memory cell array_are commonly coupled to word lines WLato WLa, respectively. More specifically, the blocks BLK_and BLK_include a plurality of memory cell transistors MC. The control gates of the plurality of memory cell transistors MCare commonly coupled to one word line WLa. Similarly, other memory cell transistors MCto MCare commonly coupled to the word lines WLato WLa, respectively. That is, the block BLK_and the block BLK_share the word lines WL. The same applies to other blocks BLK of the memory cell arrays_and_.

0 4 11 3 0 4 11 4 0 4 0 3 0 4 0 0 0 1 4 1 4 0 3 0 4 11 3 11 4 Similarly, control gates of a plurality of memory cell transistors MCto MCincluded in one block BLK of the memory cell array_and control gates of a plurality of memory cell transistors MCto MCincluded in one block BLK of the memory cell array_are commonly coupled to word lines WLbto WLb, respectively. More specifically, the blocks BLK_and BLK_include a plurality of memory cell transistors MC. The control gates of the plurality of memory cell transistors MCare commonly coupled to one word line WLb. Similarly, other memory cell transistors MCto MCare commonly coupled to the word lines WLbto WLb, respectively. That is, the block BLK_and the block BLK_share the word lines WL. The same applies to other blocks BLK of the memory cell arrays_and_.

1 11 1 1 11 2 0 1 0 1 0 2 0 2 1 1 0 0 1 0 1 0 2 0 2 0 1 1 1 0 1 1 1 2 0 2 1 1 2 1 0 1 1 2 2 0 2 2 1 3 1 0 1 1 3 2 0 2 3 11 1 11 2 Gates of a plurality of selection transistors STincluded in one string unit SU of one block BLK of the memory cell array_and gates of a plurality of selection transistors STincluded in one string unit SU of one block BLK of the memory cell array_are commonly coupled to a selection gate line SGDa. For example, the string unit SU_of the block BLK_and the string unit SU_of the block BLK_include a plurality of selection transistors ST. The gates of the plurality of selection transistors STare commonly coupled to one selection gate line SGDa. That is, the string unit SU_of the block BLK_and the string unit SU_of the block BLK_share the selection gate line SGDa. Similarly, a plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDa. A plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDa. A plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDa. The same applies to other blocks BLK of the memory cell arrays_and_.

1 11 3 1 11 4 1 0 3 0 3 1 0 4 0 4 0 1 1 3 0 3 1 1 4 0 4 1 1 2 3 0 3 1 2 4 0 4 2 1 3 3 0 3 1 3 4 0 4 3 11 3 11 4 In addition, gates of a plurality of selection transistors STincluded in one string unit SU of one block BLK of the memory cell array_and gates of a plurality of selection transistors STincluded in one string unit SU of one block BLK of the memory cell array_are commonly coupled to a selection gate line SGDb. For example, a plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDb. Similarly, a plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDb. A plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDb. A plurality of selection transistors STof the string unit SU_of the block BLK_and a plurality of selection transistors STof the string unit SU_of the block BLK_are commonly coupled to a selection gate line SGDb. The same applies to other blocks BLK of the memory cell arrays_and_.

2 11 1 2 11 2 0 1 0 2 2 2 0 1 0 2 11 1 11 2 11 1 11 2 Gates of a plurality of selection transistors STincluded in one block BLK of the memory cell array_and gates of a plurality of selection transistors STincluded in one block BLK of the memory cell array_are commonly coupled to one selection gate line SGSa. More specifically, for example, the blocks BLK_and BLK_include a plurality of selection transistors ST. The gates of the plurality of selection transistors STare commonly coupled to one selection gate line SGSa. That is, the blocks BLK_and BLK_share the selection gate line SGSa. The same applies to other blocks BLK of the memory cell arrays_and_. Note that the memory cell arrays_and_may share different selection gate lines SGSa for each string unit SU.

2 11 3 2 11 4 0 3 0 4 2 2 0 3 0 4 11 3 11 4 11 3 11 4 In addition, gates of a plurality of selection transistors STincluded in one block BLK of the memory cell array_and gates of a plurality of selection transistors STincluded in one block BLK of the memory cell array_are commonly coupled to one selection gate line SGSb. More specifically, for example, the blocks BLK_and BLK_include a plurality of selection transistors ST. The gates of the plurality of selection transistors STare commonly coupled to one selection gate line SGSb. That is, the blocks BLK_and BLK_share the selection gate line SGSb. The same applies to other blocks BLK of the memory cell arrays_and_. Note that the memory cell arrays_and_may share different selection gate lines SGSb for each string unit SU.

11 1 11 4 Source lines SL are, for example, shared among a plurality of blocks BLK of the memory cell arrays_to_.

Hereinafter, a set of a plurality of memory cell transistors MC coupled to one word line WL in one string unit SU is referred to as a “cell unit CU”. For example, when the memory cell transistor MC stores 1-bit data, a storage capacity of the cell unit CU is defined as “one-page data”. The cell unit CU may have the storage capacity of two or more page data in accordance with the number of bits of data that the memory cell transistor MC stores.

11 23 0 0 0 0 1 0 0 2 24 0 1 24 0 2 a a b In the present embodiment, in the write operation and the read operation, two cell units CU of two memory cell arraysto which a word line WL is commonly coupled can be simultaneously selected. For example, in the write operation or the read operation, when the row decoderselects the word line WLaand the selection gate line SGDa, two cell units CU, that is, the cell unit CU that includes the memory cell transistors MCof the string unit SU_and the cell unit CU that includes the memory cell transistors MCof the string unit SU_, are selected. In this case, a voltage is applied from the sense amplifierto the cell unit CU of the string unit SU_via the bit line BLa. A voltage is applied from the sense amplifierto the cell unit CU of the string unit SU_via the bit line BLb. Therefore, in the write operation or the read operation, page data of each of the two cell units CU can be collectively processed.

1.3 Arrangement of Chips

3 FIG. 3 FIG. 3 FIG. 20 10 1 10 2 Next, an example of an arrangement of each chip will be described with reference to.is a cross-sectional view illustrating the arrangement of the circuit chip, and the array chips_and_. Note that, in the example of, in order to simplify the description, one word line WLa, one word line WLb, one bit line BLa, and one bit line BLb are illustrated. The selection gate lines SGD and SGS, and the source lines SL are omitted.

20 20 20 10 20 1 1 2 Hereinafter, a direction substantially parallel to a surface of the circuit chipis referred to as an X direction. A direction that intersects with the X direction and is substantially parallel to the surface of the circuit chipis referred to as a Y direction. A direction that intersects with the X direction and the Y direction and is substantially perpendicular to the surface of the circuit chipis referred to as a Z direction. When the Z direction is further limited, a direction from the array chiptoward the circuit chipis referred to as a Zdirection, and a direction opposite to the Zdirection is referred to as a Zdirection.

3 FIG. 10 1 20 2 10 2 10 1 As illustrated in, the array chip_is provided on the circuit chipin the Zdirection. The array chip_is provided on the array chip_.

20 23 23 24 24 200 a b a b In the circuit chip, the row decodersand, and the sense amplifiersandare provided on a semiconductor substrate.

10 1 11 1 11 3 11 1 23 24 2 11 3 23 24 2 a a b b In the array chip_, for example, the memory cell arrays_and_are arranged side by side in the Y direction. For example, the memory cell array_is provided above the row decoderand the sense amplifierin the Zdirection. In addition, for example, the memory cell array_is provided above the row decoderand the sense amplifierin the Zdirection.

10 2 11 2 11 4 11 2 11 1 2 11 4 11 3 2 11 1 11 2 11 3 11 4 In the array chip_, for example, the memory cell arrays_and_are arranged side by side in the Y direction. The memory cell array_is provided above the memory cell array_in the Zdirection. The memory cell array_is provided above the memory cell array_in the Zdirection. That is, the memory cell arrays_and_are stacked in the Z direction. Similarly, the memory cell arrays_and_are stacked in the Z direction.

11 11 1 11 2 11 3 11 4 1 Hereinafter, a set of a plurality of memory cell arraysto which a word line WL is commonly coupled and stacked in the Z direction is referred to as an array unit AU. More specifically, for example, the memory cell arrays_and_constitute an array unit AUa. In addition, the memory cell arrays_and_constitute an array unit AUb. The semiconductor memory deviceincludes two array units AUa and AUb arranged adjacent to each other in the Y direction.

23 11 1 11 2 23 11 3 11 4 a b One end of the word line WLa is coupled to the row decoder. The word line WLa is commonly coupled to the memory cell arrays_and_stacked in the Z direction. One end of the word line WLb is coupled to the row decoder. The word line WLb is commonly coupled to the memory cell arrays_and_stacked in the Z direction.

24 11 1 11 4 24 11 2 11 3 11 11 10 11 10 a b The bit line BLa is coupled to the sense amplifier. The bit line BLa is commonly coupled to the memory cell arrays_and_arranged at different positions from each other in the Z direction and the Y direction. The bit line BLb is coupled to the sense amplifier. The bit line BLb is commonly coupled to the memory cell arrays_and_arranged at different positions from each other in the Z direction and the Y direction. That is, the bit line BL is commonly coupled to one memory cell arrayof one array unit AU and one memory cell arrayprovided in a different array chipof the other array unit AU. In other words, the bit line BL is commonly coupled to two memory cell arraysthat do not share the word line WL and are provided in different array chips.

1.4 Arrangement of Memory Cell Arrays

4 FIG. 4 FIG. 4 FIG. 11 1 11 4 20 11 Next, an example of an arrangement of memory cell arrays will be described with reference to.is a perspective view illustrating the arrangement of the memory cell arrays_to_and the circuit chip. Note that, in the example of, in order to simplify the description, one word line WLa, one word line WLb, one selection gate line SGDa, one selection gate line SGDb, one selection gate line SGSa, and one selection gate line SGSb, and four bit lines BLa and four bit lines BLb are illustrated in each memory cell array. The source lines SL are omitted.

4 FIG. 11 11 1 11 2 23 20 11 3 11 4 23 20 a b As illustrated in, the memory cell arrayincludes a cell portion and a WLSG coupling portion. The cell portion is a region in which the memory cell transistors are arranged. The WLSG coupling portion is a region in which a plurality of contact plugs, each coupled to a corresponding one of the word lines WL and the selection gate lines SGD and SGS, are provided. For example, the word lines WLa and the selection gate lines SGDa and SGSa of the memory cell arrays_and_are commonly coupled to the row decoderof the circuit chip. The word lines WLb and the selection gate lines SGDb and SGSb of the memory cell arrays_and_are commonly coupled to the row decoderof the circuit chip.

11 1 11 3 11 2 11 4 10 1 10 2 11 11 1 11 4 11 1 24 20 11 2 11 3 11 3 24 20 a b BL coupling portions are provided between the memory cell array_and the memory cell array_, and between the memory cell array_and the memory cell array_. The BL coupling portion is a coupling region for coupling the bit lines BL provided in the array chip_and the bit lines BL provided in the array chip_to each other. More specifically, for example, a plurality of bit lines BL extending in the Y direction are provided in the cell portion of each memory cell array. In the BL coupling portion, the bit lines BLa of the memory cell array_and the bit lines BLa of the memory cell array_are coupled. The bit lines BLa of the memory cell array_extend from the cell portion in the Z direction, and are coupled to the sense amplifierof the circuit chip. In addition, in the BL coupling portion, the bit lines BLb of the memory cell array_and the bit lines BLb of the memory cell array_are coupled. The bit lines BLb of the memory cell array_extend from the cell portion in the Z direction, and are coupled to the sense amplifierof the circuit chip.

4 FIG. 11 1 24 a Note that, in the example of, for example, in the vicinity of the center portion of the cell portion of the memory cell array_, coupling portions with the sense amplifierare provided in intermediate portions of the bit lines BLa, but the present invention is not limited thereto. For example, coupling portions may be provided at ends of the bit lines BLa. In addition, the coupling portions of the bit lines BLa do not need to be arranged side by side in the X direction. The same applies to the bit lines BLb.

1.5 Planar Configuration of Memory Cell Array

11 11 2 11 1 11 0 3 11 3 11 1 11 4 11 2 5 6 FIGS.and 5 FIG. 6 FIG. 5 6 FIGS.and 5 6 FIGS.and Next, an example of the configuration of the memory cell arraywill be described with reference to.is a plan view of the memory cell array_.is a plan view of the memory cell array_. Note that, in the example of, in order to simplify the description, a case will be described where each memory cell arrayincludes four blocks BLKto BLK, and each block BLK includes one string unit SU. In addition, in the example of, insulating layers are omitted. The configuration of the memory cell array_is similar to that of the memory cell array_. The configuration of the memory cell array_is similar to that of the memory cell array_.

11 2 First, the planar configuration of the memory cell array_will be described.

5 FIG. 0 2 3 2 102 102 102 102 0 4 102 102 As illustrated in, four blocks BLK_to BLK_are arranged side by side in the Y direction from the upper side toward the lower side in the drawing. In each block BLK, a plurality of interconnect layersare stacked apart from each other in the Z direction. For example, seven interconnect layersare stacked. Each interconnect layerextends in the X direction. Each of the interconnect layersfunctions as (is included in) a corresponding one of the selection gate line SGS, the word lines WLto WL, and the selection gate line SGD. Slits SLT are formed on the respective two side surfaces, facing the Y direction, of each interconnect layer. The slit SLT extends in the X direction and the Z direction. The slit SLT separates the interconnect layersfor each block BLK.

The block BLK includes the cell portion and the WLSG coupling portions.

102 The cell portion is provided with a plurality of memory pillars MP. The memory pillar MP is a pillar corresponding to the NAND string NS. Details of the structure of the memory pillar MP will be described later. The memory pillar MP has a substantially columnar shape and extends in the Z direction. The memory pillar MP penetrates (passes through) the plurality of interconnect layersstacked in the Z direction.

5 FIG. In the example of, the plurality of memory pillars MP in the block BLK are arranged in a staggered manner in two rows in the X direction. Note that an array of the memory pillars MP can be freely designed. The array of the memory pillars MP may be, for example, a staggered arrangement in eight rows. In addition, the array of the memory pillars MP may not be the staggered arrangement.

A plurality of bit lines BLb are arranged side by side in the X direction above the memory pillars MP. The bit line BLb extends in the Y direction. The memory pillars MP of each block BLK are each electrically coupled to any of the bit lines BLb.

11 2 1 The WLSG coupling portion of the memory cell array_includes CPregions.

1 1 1 1 102 1 102 102 1 1 1 102 1 102 0 1 2 3 4 1 0 1 1 1 2 1 3 1 4 1 102 1 1 1 1 0 1 1 1 2 1 3 1 4 1 11 2 1 1 1 5 FIG. 5 FIG. w w w w w d s s w w w w w d The CPregion is a region in which a plurality of contact plugs CPare provided. The contact plug CPextends in the Z direction. Each of the contact plugs CPis coupled to any one of the interconnect layersstacked apart from each other in the Z direction. The contact plug CPis not electrically coupled to any other interconnect layersexcept the one interconnect layer. In the example of, seven contact plugs CPare provided in one CPregion. The seven contact plugs CPare coupled to the respective seven interconnect layersstacked spaced apart from each other in the Z direction. Hereinafter, when specifying the contact plugs CPcoupled to the interconnect layerscorresponding to the word lines WL, WL, WL, WL, and WL, they are referred to as contact plugs CP_, CP_, CP_, CP_, and CP_, respectively. When specifying the contact plugs CPcoupled to the interconnect layerscorresponding to the selection gate lines SGD and SGS, they are referred to as the contact plugs CP_and CP_, respectively. In the example of, the contact plugs CP_, CP_, CP_, CP_, CP_, CP_, and CP_are arranged in this order from an end of the memory cell array_in the X direction toward the cell portion. Note that the arrangement of the contact plugs CPin each CPregion is freely set. For example, the contact plugs CPmay be arranged in two rows along the X direction.

111 1 111 1 111 1 0 2 1 2 111 1 1 2 0 2 111 1 2 2 3 2 111 1 3 2 2 2 Interconnect layersare provided on the contact plugs CP. The interconnect layerextends from a coupling position with the contact plug CPto the block BLK adjacent in the Y direction. More specifically, the interconnect layerprovided on the contact plug CPof the block BLK_extends to the block BLK_. The interconnect layerprovided on the contact plug CPof the block BLK_extends to the block BLK_. The interconnect layerprovided on the contact plug CPof the block BLK_extends to the block BLK_. The interconnect layerprovided on the contact plug CPof the block BLK_extends to the block BLK_.

111 111 1 111 Electrode pads PD are provided on the interconnect layers. One end of the interconnect layeris coupled to the contact plug CP, and the other end of the interconnect layeris electrically coupled to the electrode pad PD. The electrode pad PD is used for electrical coupling with another chip.

11 1 11 2 Next, the planar configuration of the memory cell array_will be described. Hereinafter, differences from the planar configuration of the memory cell array_will be mainly described.

6 FIG. 11 2 As illustrated in, the configuration of the cell portion is similar to that in the memory cell array_. A plurality of bit lines BLa are arranged side by side in the X direction above the memory pillars MP. The bit line BLa extends in the Y direction. The memory pillars MP of each block BLK are each electrically coupled to any of the bit lines BLa.

11 1 1 2 The WLSG coupling portion of the memory cell array_includes CPregions and CPregions.

1 11 2 1 11 1 1 11 2 The configuration of the CPregion is similar to that in the memory cell array_. For example, the CPregions of the memory cell array_are arranged above the CPregions of the memory cell array_in the Z direction.

2 2 2 11 1 1 11 2 2 2 11 1 2 102 11 1 2 1 11 2 111 10 2 5 FIG. The CPregion is a region in which a plurality of contact plugs CPare provided. For example, the contact plugs CPof the memory cell array_are arranged above the electrode pads PD electrically coupled to the contact plugs CPof the memory cell array_in the Z direction. The contact plug CPextends in the Z direction. The contact plug CPpenetrates the memory cell array_. The contact plug CPis not electrically coupled to the interconnect layersof the memory cell array_. The contact plug CPis electrically coupled with the contact plug CPof the memory cell array_via the electrode pads PD and the interconnect layerof the array chip_described in.

2 0 1 1 1 2 11 2 2 1 1 1 0 2 11 2 2 2 1 1 3 2 11 2 2 3 1 1 2 2 11 2 More specifically, for example, the contact plug CPof the block BLK_is electrically coupled to the contact plug CPof the block BLK_of the memory cell array_. The contact plug CPof the block BLK_is electrically coupled to the contact plug CPof the block BLK_of the memory cell array_. The contact plug CPof the block BLK_is electrically coupled to the contact plug CPof the block BLK_of the memory cell array_. The contact plug CPof the block BLK_is electrically coupled to the contact plug CPof the block BLK_of the memory cell array_.

6 FIG. 2 2 2 1 11 2 2 1 0 1 1 1 2 1 3 1 4 11 2 2 0 2 1 2 2 2 3 2 4 2 1 1 11 2 2 2 w w w w w w w w w d s d s In the example of, seven contact plugs CPare provided in one CPregion. The seven contact plugs CPcorrespond to the respective seven contact plugs CPof the memory cell array_. Hereinafter, when specifying the contact plugs CPcoupled to the contact plugs CP_, CP_, CP_, CP_, and CP_wof the memory cell array_, they are referred to as contact plugs CP_, CP_, CP_, CP_, and CP_, respectively. When specifying the contact plugs CPcoupled to the contact plugs CP_and CP_of the memory cell array_, they are referred to as contact plugs CP_and CP_, respectively.

111 1 2 1 0 1 4 1 1 2 0 2 4 2 2 111 w w d s w w d s Interconnect layersare provided on the contact plugs CPand CP. The contact plugs CP_to CP_, and CP_and CP_are respectively coupled to the contact plugs CP_to CP_, and CP_and CP_of the adjacent block BLK via the interconnect layers.

1 0 1 2 1 1 1 1 1 2 0 1 1 2 1 2 3 1 1 3 1 2 2 1 More specifically, for example, the contact plugs CPof the block BLK_are electrically coupled with the contact plugs CPof the block BLK_. The contact plugs CPof the block BLK_are electrically coupled with the contact plugs CPof the block BLK_. The contact plugs CPof the block BLK_are electrically coupled with the contact plugs CPof the block BLK_. The contact plugs CPof the block BLK_are electrically coupled with the contact plugs CPof the block BLK_.

0 4 0 1 0 4 0 2 That is, the word lines WLato WLa, and the selection gate lines SGDa and SGSa of the block BLK_are electrically coupled to the word lines WLato WLa, and the selection gate lines SGDa and SGSa of the block BLK_, respectively. The same applies to other blocks BLK.

11 2 111 11 1 Similarly to the memory cell array_, electrode pads PD are provided on the interconnect layersabove the memory cell array_.

1.6 Cross-Sectional Configuration of Memory Cell Array

11 Next, the cross-sectional configuration of the memory cell arraywill be described.

1 2 1.6.1 Configuration of A-ACross Section

1 2 1 1 2 11 1 11 2 11 3 11 4 7 FIG. 7 FIG. 5 6 FIGS.and 7 FIG. First, an example of the configuration of an A-Across section of the semiconductor memory devicewill be described with reference to.is a cross-sectional view taken along line A-Ain. The example ofillustrates the memory cell arrays_and_, and the same applies to the memory cell arrays_and_.

7 FIG. 1 10 1 10 2 20 As illustrated in, the semiconductor memory devicehas a configuration in which the array chips_and_and the circuit chipare bonded. The chips are electrically coupled to each other via the electrode pads PD provided in each of the chips.

10 1 First, the internal configuration of the array chip_will be described.

10 1 11 1 The array chip_includes the memory cell array_and various interconnect layers for coupling to another chip.

10 1 101 105 107 110 112 114 102 103 104 111 106 108 109 113 115 The array chip_includes an insulating layers,,,,, and, interconnect layers,,, and, and conductors,,,, and.

11 1 101 102 102 0 4 1 102 0 1 2 3 4 102 0 102 1 102 2 102 3 102 4 102 102 102 7 FIG. w w w w w d s In the memory cell array_, a plurality of insulating layersand a plurality of interconnect layersare alternately stacked one by one. In the example of, seven interconnect layersthat function as the selection gate line SGSa, the word lines WLato WLa, and the selection gate line SGDa are stacked in this order in the Zdirection. Hereinafter, when specifying the interconnect layersfunctioning as the word lines WL, WL, WL, WL, and WL, they are referred to as interconnect layers_,_,_,_, and_, respectively. When specifying the interconnect layersfunctioning as the selection gate lines SGD and SGS, they are referred to as interconnect layers_and_, respectively.

101 102 102 102 The insulating layermay contain, for example, silicon oxide (SiO). The interconnect layercontains a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. As the conductive material of the interconnect layer, for example, a stacked structure of titanium nitride (TiN)/tungsten (W) is used. In this case, TiN is formed so as to cover W. Note that the interconnect layermay contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed so as to cover the conductive material.

102 105 105 The plurality of interconnect layersare separated for each block BLK by the slits SLT extending in the X direction. The slit SLT is filled with the insulating layer. The insulating layermay contain SiO.

103 102 2 101 102 103 103 104 103 2 104 103 103 104 s s The interconnect layeris provided above the interconnect layer_in the Zdirection. The insulating layeris provided between the interconnect layer_and the interconnect layer. The interconnect layerfunctions as (is included in) the source line SL. The interconnect layeris provided on the interconnect layerin the Zdirection. The interconnect layeris used as an interconnect layer for electrically coupling the interconnect layerto another chip. The interconnect layersandmay contain a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor.

1 102 1 1 1 106 107 106 106 102 107 106 107 106 102 107 106 107 The contact plug CPis provided on each interconnect layerin the Zdirection. The contact plug CPhas, for example, a columnar shape. The contact plug CPincludes the conductorand the insulating layer. The conductorhas, for example, a columnar shape. One end of the conductoris in contact with the interconnect layer. The insulating layeris provided so as to cover a side surface (outer periphery) of the conductor. The insulating layerhas, for example, a cylindrical shape. The side surface of the conductoris not electrically coupled with other interconnect layersby the insulating layer. The conductormay contain a metal material containing W, copper (Cu), aluminum (Al), or the like. The insulating layermay contain SiO.

7 FIG. 1 4 1 4 102 1 4 102 4 w w d w w In the example of, the contact plug CP_is provided. The contact plug CP_penetrates the interconnect layer_. The contact plug CP_is electrically coupled with the interconnect layer_.

2 102 2 2 109 110 109 110 109 110 109 102 110 The contact plug CPthat penetrates the plurality of interconnect layersis provided. The contact plug CPhas, for example, a columnar shape. The contact plug CPincludes the conductorand the insulating layer. The conductorhas, for example, a columnar shape. The insulating layeris provided so as to cover a side surface (outer periphery) of the conductor. The insulating layerhas, for example, a cylindrical shape. The conductoris not electrically coupled with the interconnect layersby the insulating layer.

103 104 2 2 108 102 2 101 102 108 108 2 s The interconnect layerand the interconnect layerare not provided in the CPregions in which the contact plugs CPare provided. The conductoris provided above the interconnect layer_in the Zdirection. The insulating layeris provided between the interconnect layerand the conductor. The conductoris in contact with (electrically coupled to) one end of the contact plug CP.

111 102 1 111 101 102 111 111 d The interconnect layeris provided above the interconnect layer_in the Zdirection. The interconnect layerextends in the Y direction. The insulating layeris provided between the interconnect layerand the interconnect layer. The interconnect layercontains a conductive material. The conductive material may include a metal material containing Cu, Al, or the like.

1 2 111 1 2 111 1 4 0 1 2 4 1 1 111 0 1 1 1 1 4 2 1 2 4 3 1 111 2 1 3 1 7 FIG. w w w w The other end of the contact plug CPand the other end of the contact plug CPprovided to the block BLK adjacent in the Y direction are (electrically) coupled to the interconnect layer. The contact plugs CPand CPcoupled to the interconnect layerare arranged side by side along the Y direction. In the example of, the contact plug CP_of the block BLK_and the contact plug CP_of the block BLK_are coupled to the interconnect layerarranged so as to straddle the blocks BLK_and BLK_. In addition, the contact plug CP_of the block BLK_and the contact plug CP_of the block BLK_are coupled to the interconnect layerarranged so as to straddle the blocks BLK_and BLK_.

112 111 101 1 112 The insulating layeris provided on the interconnect layersand the insulating layerin the Zdirection. The insulating layermay contain SiO.

113 112 113 113 111 113 A plurality of conductorsare provided in the insulating layer. The conductorfunctions as an electrode pad PD. For example, one conductoris provided on one interconnect layer. The conductormay contain a metal material containing Cu.

114 104 101 108 2 114 The insulating layeris provided on the interconnect layers, the insulating layer, and the conductorsin the Zdirection. The insulating layermay contain SiO.

115 114 115 115 108 115 A plurality of conductorsare provided in the insulating layer. The conductorfunctions as an electrode pad PD. For example, one conductoris provided on one conductor. The conductormay contain a metal material containing Cu.

10 2 10 1 Next, the internal configuration of the array chip_will be described. Hereinafter, differences from the array chip_will be mainly described.

10 2 2 108 114 115 10 1 10 1 113 10 2 115 10 1 In the array chip_, the contact plugs CP, the conductors, the insulating layer, and the conductorsdescribed in the configuration of the array chip_are eliminated. Other configurations are similar to those of the array chip_. The conductorsof the array chip_are coupled to the conductorsof the array chip_.

102 11 2 102 11 1 1 10 2 111 10 2 113 10 2 115 10 1 108 10 1 2 10 1 111 10 1 1 10 1 For example, the interconnect layerof the memory cell array_is electrically coupled to the interconnect layerof the memory cell array_via the contact plug CPof the array chip_, the interconnect layerof the array chip_, the conductorof the array chip_, the conductorof the array chip_, the conductorof the array chip_, the contact plug CPof the array chip_, the interconnect layerof the array chip_, and the contact plug CPof the array chip_.

7 FIG. 102 4 0 2 11 2 102 4 0 1 11 1 4 11 2 4 11 1 1 1 4 11 2 1 4 11 1 1 2 108 11 2 w w w w In the example of, the interconnect layer_of the block BLK_of the memory cell array_and the interconnect layer_of the block BLK_of the memory cell array_are electrically coupled. In other words, the word line WLaof the memory cell array_and the word line WLaof the memory cell array_arranged above in the Zdirection are electrically coupled. In this case, the contact plug CP_of the memory cell array_and the contact plug CP_of the memory cell array_arranged above in the Zdirection are electrically coupled. The same applies to other word lines WL. Note that the contact plugs CPand the conductorsmay be provided in the memory cell array_.

20 Next, the circuit chipwill be described.

20 21 22 23 24 The circuit chipincludes a plurality of transistors Tr and various interconnect layers. The plurality of transistor Tr are used for the sequencer, the voltage generator, the row decoders, the sense amplifiers, and the like.

20 201 202 209 203 204 206 208 210 205 207 More specifically, the circuit chipincludes insulating layers,, and, gate electrodes, conductors,,, and, and interconnect layersand.

200 200 201 201 Element isolation regions are provided in the vicinity of a surface of the semiconductor substrate. The element isolation region electrically isolates an n-type well region and a p-type well region provided in the vicinity of the surface of the semiconductor substrate, for example. The element isolation region is filled with the insulating layer. The insulating layermay contain SiO.

202 200 202 The insulating layeris provided on the semiconductor substrate. The insulating layermay contain SiO.

200 203 200 205 204 204 2 204 206 205 206 2 206 207 206 208 207 208 2 20 208 205 207 204 206 208 205 207 The transistor Tr includes a gate insulating film (not illustrated) provided on the semiconductor substrate, the gate electrodeprovided on the gate insulating film, and a source and a drain (not illustrated) formed in the semiconductor substrate. The source and the drain are each electrically coupled to the interconnect layervia the conductor. The conductorextends in the Zdirection. The conductorfunctions as a contact plug. The conductoris provided on the interconnect layer. The conductorextends in the Zdirection. The conductorfunctions as a contact plug. The interconnect layeris provided on the conductor. The conductoris provided on the interconnect layer. The conductorextends in the Zdirection. Note that the number of interconnect layers provided in the circuit chipis freely set. The conductorfunctions as a contact plug. The interconnect layersandare made of a conductive material. The conductors,, and, and the interconnect layersandmay contain a metal material, a p-type semiconductor, or an n-type semiconductor.

209 202 2 209 The insulating layeris provided on the insulating layerin the Zdirection. The insulating layermay contain SiO.

210 209 210 210 208 210 210 20 113 10 1 A plurality of conductorsare provided in the insulating layer. The conductorfunctions as an electrode pad PD. For example, one conductoris provided on one conductor. The conductormay contain a metal material such as Cu. The conductorof the circuit chipis in contact with (electrically coupled to) the conductorof the array chip_.

1 2 1.6.2 Configuration of B-BCross Section

1 2 1 1 2 1 8 FIG. 8 FIG. 5 6 FIGS.and Next, an example of the configuration of a B-Bcross section of the semiconductor memory devicewill be described with reference to.is a cross-sectional view taken along line B-Bin. Hereinafter, description will be given focusing on the configurations of the contact plugs CP.

8 FIG. 8 FIG. 1 1 0 1 4 1 11 1 11 2 1 1 0 1 4 1 1 1 0 1 4 1 102 102 0 102 4 102 1 1 0 1 4 1 111 1 1 0 1 4 1 s w w d s w w d s w w d s w w d s w w d w w d As illustrated in, the contact plugs CP_, CP_to CP_, and CP_are provided in each of the memory cell arrays_and_. In the example of, the contact plugs CP_, CP_to CP_, and CP_are arranged in this order from the right side toward the left side in the drawing. One ends of the contact plugs CP_, CP_to CP_, and CP_are in contact with (electrically coupled to) the interconnect layers_,_to_, and_, respectively. In addition, the other ends of the contact plugs CP_, CP_to CP_, and CP_are in contact with (electrically coupled to) different interconnect layers. Therefore, lengths of the contact plugs CP_S, CP_to CP_, and CP_in the Z direction are different from each other.

1 102 0 102 4 102 1 102 0 102 4 102 1 102 s w w d s w w d s s. More specifically, the contact plug CP_penetrates six interconnect layers_to_, and_. The contact plug CP_is not electrically coupled to the six interconnect layers_to_and_. One end of the contact plug CP_is electrically coupled to the interconnect layer_

1 0 102 1 102 4 102 1 0 102 1 102 4 102 1 0 102 0 w w w d w w w d w w The contact plug CP_penetrates five interconnect layers_to_and_. The contact plug CP_is not electrically coupled to the five interconnect layers_to_and_. One end of the contact plug CP_is electrically coupled to the interconnect layer_.

1 1 102 2 102 4 102 1 1 102 2 102 4 102 1 1 102 1 w w w d w w d w w The contact plug CP_penetrates four interconnect layers_to_and_. The contact plug CP_wis not electrically coupled to the four interconnect layers_to_and_. One end of the contact plug CP_is electrically coupled to the interconnect layer_.

1 2 102 3 102 4 102 1 2 102 3 102 4 102 1 2 102 2 w w w d w w w d w w The contact plug CP_penetrates three interconnect layers_,_, and_. The contact plug CP_is not electrically coupled to the three interconnect layers_,_, and_. One end of the contact plug CP_is electrically coupled to the interconnect layer_.

1 3 102 4 102 1 3 102 4 102 1 3 102 3 w w d w w d w w The contact plug CP_penetrates two interconnect layers_and_. The contact plug CP_is not electrically coupled to the two interconnect layers_and_. One end of the contact plug CP_is electrically coupled to the interconnect layer_.

1 4 102 1 4 102 1 4 102 4 w d w d w w The contact plug CP_penetrates the interconnect layer_. The contact plug CP_is not electrically coupled to the interconnect layer_. One end of the contact plug CP_is electrically coupled to the interconnect layer_.

1 102 d d. One end of the contact plug CP_is electrically coupled to the interconnect layer_

1 2 1.6.3 Configuration of C-CCross Section

1 2 1 1 2 2 9 FIG. 9 FIG. 5 6 FIGS.and Next, an example of the configuration of a C-Ccross section of the semiconductor memory devicewill be described with reference to.is a cross-sectional view taken along line C-Cin. Hereinafter, description will be given focusing on the configurations of the contact plugs CP.

9 FIG. 9 FIG. 2 2 0 2 4 2 10 1 2 2 0 2 4 2 2 2 0 2 4 2 2 2 0 2 4 2 102 102 0 102 4 102 2 2 0 2 4 2 102 102 0 102 4 102 2 2 0 2 4 2 108 2 2 0 2 4 2 111 s w w d s w w d s w w d s w w d s w w d s w w d s w w d s w w d s w w d As illustrated in, the contact plugs CP_, CP_to CP_, and CP_are provided in the array chip_. In the example of, the contact plugs CP_, CP_to CP_, and CP_are arranged in this order from the right side toward the left side in the drawing. The contact plugs CP_, CP_to CP_, and CP_have substantially the same shape (the same length). The contact plugs CP_, CP_to CP_, and CP_penetrate seven interconnect layers_,_to_, and_. The contact plugs CP_, CP_to CP_, and CP_are not electrically coupled to the seven interconnect layers_,_to_, and_. One ends of the contact plugs CP_, CP_to CP_, and CP_are coupled to different conductors. The other ends of the contact plugs CP_, CP_to CP_, and CP_are coupled to different interconnect layers.

1 2 1.6.4 Configuration of D-DCross Section

1 2 1 1 2 10 FIG. 10 FIG. 5 6 FIGS.and Next, an example of the configuration of a D-Dcross section of the semiconductor memory devicewill be described with reference to.is a cross-sectional view taken along line D-Din. Hereinafter, description will be given focusing on the configurations of the memory pillar MP and the bit line BL.

10 FIG. 10 1 10 2 As illustrated in, the memory pillars MP are provided in the array chips_and_.

102 103 126 1 126 126 3 127 126 127 127 4 128 1 128 128 128 128 3 4 The memory pillar MP penetrates the plurality of interconnect layers. The memory pillar MP extends in the Z direction. One end of the memory pillar MP is in contact with the interconnect layer. A conductoris provided on the other end of the memory pillar MP in the Zdirection. For example, the conductorhas a substantially columnar shape. The conductorfunctions as a contact plug CP. A conductoris provided on the conductor. For example, the conductorhas a substantially columnar shape. The conductorfunctions as a contact plug CP. A plurality of interconnect layersare provided above the memory pillars MP in the Zdirection. The plurality of interconnect layersare arranged side by side in the X direction. The interconnect layerextends in the Y direction. The interconnect layerfunctions as the bit line BL. The interconnect layeris electrically coupled to any of the memory pillars MP via the contact plugs CPand CP.

126 127 128 The conductorand, and the interconnect layermay contain a metal material such as W, Al, Cu, or the like.

Next, the internal configuration of the memory pillar MP will be described.

120 121 122 123 124 125 The memory pillar MP includes a block insulating film, a charge storage layer, a tunnel insulating film, a semiconductor layer, a core layer, and a cap layer.

102 2 103 120 121 122 120 121 122 123 122 123 2 103 123 1 2 123 2 0 4 1 More specifically, a hole MH that penetrates the plurality of interconnect layersis formed. The hole MH corresponds to the memory pillar MP. An end of the hole MH in the Zdirection reaches the interconnect layer. On a side surface of the hole MH, the block insulating film, the charge storage layer, and the tunnel insulating filmare stacked in this order from the outside. For example, when the hole MH has a cylindrical shape, the block insulating film, the charge storage layer, and the tunnel insulating filmeach have a cylindrical shape. The semiconductor layeris provided so as to be in contact with a side surface of the tunnel insulating film. An end of the semiconductor layerin the Zdirection is in contact with the interconnect layer. The semiconductor layeris a region in which channels of the memory cell transistors MC and the selection transistors STand STare formed. Therefore, the semiconductor layerfunctions as a signal line that couples the current paths of the selection transistor ST, the memory cell transistors MCto MC, and the selection transistor ST.

123 124 125 122 123 124 1 123 102 The semiconductor layeris filled with the core layer. A cap layer, a side surface of which is in contact with the tunnel insulating film, is provided on ends of the semiconductor layerand the core layerin the Zdirection. That is, the memory pillar MP includes the semiconductor layerthat passes through the plurality of interconnect layersand extends in the Z direction.

120 122 124 121 123 125 The block insulating film, the tunnel insulating film, and the core layermay contain SiO. The charge storage layermay contain silicon nitride (SiN). The semiconductor layerand the cap layermay contain, for example, polysilicon.

0 4 102 0 102 4 1 102 2 102 w w d s. The memory cell transistors MCto MCare configured by combining the memory pillars MP and the respective interconnect layers_to_. Similarly, the selection transistor STis configured by combining the memory pillar MP and the interconnect layer_. The selection transistor STis configured by combining the memory pillar MP and the interconnect layer_

1.7 Planar Configuration of BL Coupling Portion

11 FIG. 11 FIG. 11 FIG. 10 2 0 3 11 2 0 3 11 4 Next, an example of the configuration of the BL coupling portion will be described with reference to.is a plan view of the BL coupling portion of the array chip_. The example ofillustrates four bit lines BLbto BLbcoupled to the memory cell array_, and four bit lines BLato BLacoupled to the memory cell array_. Note that the insulating layers are omitted.

128 132 113 131 133 128 132 113 131 133 128 132 113 131 133 128 132 113 131 133 a a a a a b b b b b Hereinafter, when specifying the interconnect layersand, and the conductors,, andcorresponding to the bit lines BLa, they are referred to as interconnect layersand, and conductors,, and, respectively. In addition, when specifying the interconnect layersand, and the conductors,, andcorresponding to the bit lines BLb, they are referred to as interconnect layersand, and conductors,, and, respectively.

11 FIG. 11 FIG. 128 0 3 128 0 3 128 128 a b a b As illustrated in, the interconnect layersthat function as the bit lines BLato BLaare arranged side by side in the X direction. Similarly, the interconnect layersthat function as the bit lines BLbto BLbare arranged side by side in the X direction. Each of the interconnect layersandextends in the Y direction. In the example of, the bit lines BLa and the bit lines BLb are arranged so as to face each other in the Y direction.

131 128 131 131 128 131 132 131 6 128 132 132 128 132 128 132 132 133 132 133 133 132 133 113 133 7 132 113 The conductoris coupled to an end of each interconnect layer. The conductorhas a substantially columnar shape and extends in the Z direction. One end of the conductoris coupled to the interconnect layer, and the other end of the conductoris coupled to the interconnect layer. The conductorfunctions as a contact plug CPthat couples the interconnect layerand the interconnect layer. The interconnect layeris provided in a layer different from the interconnect layer. The shape of the interconnect layerdiffers depending on the interconnect layerelectrically coupled to the interconnect layer. The shape of the interconnect layerwill be described later. The conductoris coupled to an end of the interconnect layer. The conductorhas a substantially columnar shape and extends in the Z direction. One end of the conductoris coupled to the interconnect layer, and the other end of the conductoris coupled to the conductor. The conductorfunctions as a contact plug CPthat couples the interconnect layerand the conductor.

131 133 132 The conductorsand, and the interconnect layermay contain a metal material such as W, Al, Cu, or the like.

132 Next, an example of the shape of the interconnect layerwill be described.

128 10 2 11 1 10 1 128 10 2 11 3 10 1 113 128 11 2 113 128 132 128 132 128 132 132 132 1 132 3 132 1 132 1 128 131 132 1 132 2 132 2 132 2 132 3 132 3 132 3 113 133 a b a a b b b b a a b a a a a a a a a a a a a a a a a. The interconnect layersof the array chip_are electrically coupled to the memory cell array_of the array chip_. In addition, the interconnect layersof the array chip_are electrically coupled to the memory cell array_of the array chip_. Therefore, for example, the conductorselectrically coupled to the interconnect layersare arranged on a side closer to the memory cell array_than the conductorselectrically coupled to the interconnect layers. In such a case, for example, the interconnect layerelectrically coupled to the interconnect layerextends in the Y direction. On the other hand, the interconnect layerelectrically coupled to the interconnect layeris formed in a shape so as to bypass the interconnect layer, for example. More specifically, for example, the interconnect layerincludes three interconnect portionsto. The interconnect portionextends in the X direction. One end of the interconnect portionis coupled to the interconnect layervia the conductor, and the other end of the interconnect portionis coupled to one end of the interconnect portion. The interconnect portionextends in the Y direction. The other end of the interconnect portionis coupled to one end of the interconnect portion. The interconnect portionextends in the X direction. The other end of the interconnect portionis coupled to the conductorvia the conductor

11 FIG. 132 0 132 0 132 1 132 1 132 0 132 2 3 132 2 3 132 2 3 132 2 3 132 0 1 132 0 1 a b a b a a b a b a b In the example of, the interconnect layercorresponding to the bit line BLais arranged so as to protrude downward in the drawing and bypass the interconnect layercorresponding to the bit line BLb. The interconnect layercorresponding to the bit line BLais arranged so as to protrude upward in the drawing and bypass the interconnect layercorresponding to the bit line BLbso as to face the interconnect layercorresponding to the bit line BLa. The interconnect layerscorresponding to the bit lines BLaand BLaand the interconnect layerscorresponding to the bit lines BLband BLbalso have the same shapes as described above. The interconnect layerscorresponding to the bit lines BLaand BLaand the interconnect layerscorresponding to the bit lines BLband BLbare arranged at positions different from the interconnect layerscorresponding to the bit lines BLaand BLaand the interconnect layerscorresponding to the bit lines BLband BLbin the Y direction.

1.8 BL Cross-Sectional Configuration of Coupling Portion

12 FIG. 12 FIG. 11 FIG. 1 2 11 Next, an example of the cross-sectional configuration of the BL coupling portion will be described with reference to.is a cross-sectional view taken along line E-Ein. Hereinafter, description will be given focusing on the coupling between the bit lines BL between the memory cell arrays.

115 130 115 130 115 130 115 130 a a b b Hereinafter, when specifying the conductorsand conductorscorresponding to the bit lines BLa, they are referred to as conductorsand, respectively. In addition, when specifying the conductorsandcorresponding to the bit lines BLb, they are referred to as conductorsand, respectively.

12 FIG. 10 1 128 115 130 2 130 130 5 131 128 1 132 131 1 132 113 133 As illustrated in, in the BL coupling portion of the array chip_, one ends of the interconnect layersare coupled to the conductorsvia the conductorsextending in the Zdirection. For example, the conductorhas a substantially columnar shape. The conductorfunctions as a contact plug CP. In addition, in the cell portion, the conductoris provided on the interconnect layerin the Zdirection. The interconnect layeris provided on the conductorin the Zdirection. The interconnect layeris coupled to the conductorvia the conductor.

130 The conductormay contain a metal material such as W, Al, Cu, or the like.

10 2 131 128 1 132 131 132 113 133 In the BL coupling portion of the array chip_, the conductorsare provided on the interconnect layersin the Zdirection. The interconnect layersare provided on the conductors. The interconnect layeris coupled to the conductorvia the conductor.

128 11 2 128 11 3 131 132 133 113 115 130 128 11 3 24 20 128 11 4 128 11 1 131 132 133 113 115 130 128 11 1 24 20 b b b b b b b b b b a a a a a a a a a a More specifically, for example, the interconnect layer(bit line BLb) corresponding to the memory cell array_is coupled to the interconnect layer(bit line BLb) corresponding to the memory cell array_via the conductor, the interconnect layer, the conductor, the conductor, the conductor, and the conductor. The interconnect layer(bit line BLb) corresponding to the memory cell array_is electrically coupled to the sense amplifierof the circuit chip. Similarly, the interconnect layer(bit line BLa) of the memory cell array_is coupled to the interconnect layer(bit line BLa) corresponding to the memory cell array_via the conductor, the interconnect layer, the conductor, the conductor, the conductor, and the conductor. The interconnect layer(bit line BLa) corresponding to the memory cell array_is electrically coupled to the sense amplifierof the circuit chip.

1.9 Selection of Cell Unit in Write Operation and Read Operation

13 14 FIGS.and 13 FIG. 14 FIG. 13 14 FIGS.and Next, an example of selection of the cell units CU in the write operation and the read operation will be described with reference to.is a conceptual diagram illustrating a case where the cell units CU of the array unit AUa are selected.is a conceptual diagram illustrating a case where the cell units CU of the array unit AUb are selected. In, a thick solid line indicates a state where voltages are applied to the word line WL and the bit line BL in the write operation or the read operation. In addition, the word line WL indicated by a broken line indicates a state (an off state) where no voltage is applied.

First, a case will be described where the cell units CU of the array unit AUa are selected.

13 FIG. 11 1 11 2 24 11 1 24 11 2 a b As illustrated in, in the write operation or the read operation, one cell unit CU (memory cell transistors MC) of the memory cell array_and one cell unit CU (memory cell transistors MC) of the memory cell array_that are commonly coupled to one word line WLa are simultaneously selected. The sense amplifierapplies voltages corresponding to the write operation or the read operation to the memory cell array_via the bit lines BLa. On the other hand, the sense amplifierapplies voltages corresponding to the write operation or the read operation to the memory cell array_via the bit lines BLb. In this case, the array unit AUb is not selected and hence, no voltage is applied to the word line WLb.

Next, a case will be described where the cell units CU of the array unit AUb are selected.

14 FIG. 11 3 11 4 24 11 4 24 11 3 a b As illustrated in, in the write operation or the read operation, one cell unit CU (memory cell transistor MC) of the memory cell array_and one cell unit CU (memory cell transistors MC) of the memory cell array_that are commonly coupled to one word line WLb are simultaneously selected. The sense amplifierapplies voltages corresponding to the write operation or the read operation to the memory cell array_via the bit lines BLa. On the other hand, the sense amplifierapplies voltages corresponding to the write operation or the read operation to the memory cell array_via the bit lines BLb. In this case, the array unit AUa is not selected and hence, no voltage is applied to the word line WLa.

1.10 Order of Data Writing

15 FIG. 15 FIG. 15 FIG. 15 FIG. 11 23 23 4 0 0 4 a b Next, an order of data writing will be described with reference to.is a diagram illustrating a write order of one block BLK of each memory cell array. In the example of, one frame in the table corresponds to one cell unit CU. Numbers starting with “a” in the frames indicate a case where the row decoderselects the word line WLa and the selection gate line SGDa, that is, a case where the array unit AUa is selected. Numbers starting with “b” in the frames indicate a case where the row decoderselects the word line WLb and the selection gate line SGDb, that is, a case where the array unit AUb is selected. Note that, in the example of, as an order of selecting the word lines WL, a case is illustrated where the word lines WL are selected in order from the word line WLto the word line WL. However, the word lines WL may be selected in order from the word line WLto the word line WL.

23 a First, the write operation in which the row decoderselects the word lines WLa and the selection gate lines SGDa will be described.

15 FIG. 23 4 0 1 4 0 1 4 0 2 11 1 11 2 24 11 1 24 11 2 a a b As illustrated in, for example, the row decoderselects the word line WLaand the selection gate line SGDaas an a-th write operation. As a result, the memory cell transistor MCof the string unit SU_and the memory cell transistor MCof the string unit SU_are selected. That is, one cell unit CU of the memory cell arrays_and one cell unit CU of the memory cell arrays_are selected. In this state, the sense amplifierapplies voltages corresponding to the write data to the memory cell array_via the bit lines BLa. At the same time, the sense amplifierapplies voltages corresponding to the write data to the memory cell array_via the bit lines BLb.

23 4 1 3 2 4 11 1 4 1 1 3 1 2 4 11 2 4 1 2 3 2 2 4 a Next, the row decoderselects the word line WLa, and selects the selection gate lines SGDato SGDain this order as ato a-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the ato a-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the ato a-th write operations.

23 3 0 3 5 8 11 1 3 0 1 3 1 5 8 11 2 3 0 2 3 2 5 8 a Next, the row decoderselects the word line WLa, and selects the selection gate lines SGDato SGDain this order as ato a-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the ato a-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the ato a-th write operations.

23 9 20 a The row decoderselects the word lines WLa and the selection gate lines SGDa in the same order also in ato a-th write operations.

23 b Next, the write operation in which the row decoderselects the word lines WLb and the selection gate lines SGDb will be described.

23 4 0 1 4 0 3 4 0 4 11 3 11 4 24 11 3 24 11 4 b b a For example, the row decoderselects the word line WLband the selection gate line SGDbas a b-th write operation. As a result, the memory cell transistor MCof the string unit SU_and the memory cell transistor MCof the string unit SU_are selected. That is, one cell unit CU of the memory cell arrays_and one cell unit CU of the memory cell arrays_are selected. In this state, the sense amplifierapplies voltages corresponding to the write data to the memory cell array_via the bit lines BLb. At the same time, the sense amplifierapplies voltages corresponding to the write data to the memory cell array_via the bit lines BLa.

23 4 1 3 2 4 11 3 4 1 3 3 3 2 4 11 4 4 1 4 3 4 2 4 b Next, the row decoderselects the word line WLb, and selects the selection gate lines SGDbto SGDbin this order as bto b-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the bto b-th write operations. In the memory cell array_, the memory cell transistors MCof the string units SU_to SU_are selected in this order in response to the bto b-th write operations.

23 23 5 20 b a The row decoderselects the word lines WLb and the selection gate lines SGDb in the same order as the order by the row decoderalso in bto b-th write operations.

1.11 Advantageous Effects According to Present Embodiment

With the configuration according to the present embodiment, it is possible to provide a semiconductor memory device capable of suppressing an increase in the chip area. This advantageous effect will be described in detail.

For example, a method is known in which a plurality of memory cell arrays (array chips) are stacked in order to highly integrate a semiconductor memory device. When word lines WL of each memory cell array are separately coupled to a circuit chip, the number of word lines WL coupled to a row decoder increases. Therefore, the circuit scale of the row decoder increases in accordance with the number of memory cell arrays. In other words, the area of the circuit chip increases.

11 20 11 23 20 On the other hand, with the configuration according to the present embodiment, in the plurality of memory cell arraysstacked above the circuit chip, the word lines WL can be commonly coupled. Therefore, even when the number of memory cell arrays, that is, the number of stacked layers of the word lines WL increases, an increase in the number of word lines WL coupled to the row decodercan be suppressed. As a result, an increase in the area of the circuit chipcan be suppressed.

11 20 20 11 11 10 11 1 Furthermore, the configuration according to the present embodiment includes a structure in which two sets of array units AU each including two memory cell arraysstacked above the circuit chipare arranged side by side in a direction parallel to the circuit chip. The bit lines BL are commonly coupled to one memory cell arrayof one array unit AU and one memory cell arrayprovided in a different array chipof the other array unit AU. As a result, in the write operation and the read operation, two cell units CU of the two memory cell arraysin the array unit AU can be simultaneously selected. That is, in the write operation and the read operation, page data of each of the two cell units CU can be collectively processed. Therefore, the semiconductor memory devicecan improve processing capability.

11 11 10 Furthermore, with the configuration according to the present embodiment, two cell units CU can be collectively processed. Accordingly, the size of the block BLK in one memory cell array, that is, the data size of one page, can be halved. As a result, the size of the memory cell arraycan be reduced. Therefore, an increase in the area of the array chipcan be suppressed.

11 Furthermore, with the configuration according to the present embodiment, the bit lines BL can be shared between the array units AU. Therefore, even when the number of stacked memory cell arraysincreases, an increase in the number of bit lines BL coupled to the sense amplifier can be suppressed. As a result, an increase in the area of the circuit chip can be suppressed.

Furthermore, the configuration according to the present embodiment can suppress disturbances in the write operation and the read operation. This advantageous effect will be described in detail.

11 11 11 For example, in the write operation and the read operation, when either one of the memory cell arraysof the array unit AU is selected, a voltage is also applied to the word line WL of non-selected memory cell arrayof the selected array unit AU. Therefore, the non-selected memory cell arrayis also affected by the disturbance.

11 11 On the other hand, with the configuration according to the present embodiment, two memory cell arraysof the array unit AU can be simultaneously selected or deselected. Therefore, in the write operation and the read operation, application of a voltage to the word line WL of the non-selected memory cell arrayscan be suppressed. Therefore, the influence of disturbance can be suppressed.

11 Next, a second embodiment will be described. In the second embodiment, a layout of memory cell arraysdifferent from that in the first embodiment will be described. Hereinafter, differences from the first embodiment will be mainly described.

2.1 Arrangement of Memory Cell Arrays

16 FIG. 16 FIG. 16 FIG. 11 1 11 4 20 11 Next, an example of an arrangement of memory cell arrays will be described with reference to.is a perspective view illustrating the arrangement of memory cell arrays_to_and a circuit chip. Note that, in the example of, in order to simplify the description, one word line WLa, one word line WLb, one selection gate line SGDa, one selection gate line SGDb, one selection gate line SGSa, and one selection gate line SGSb, and eight bit lines BLa and eight bit lines BLb are illustrated in each memory cell array. The source lines SL are omitted. In addition, in order to simplify the description, BL coupling portions are omitted.

16 FIG. 11 11 As illustrated in, the memory cell arrayincludes two cell portions and one WLSG coupling portion. More specifically, the WLSG coupling portion is provided between the two cell portions arranged side by side in the X direction. That is, the WLSG coupling portion is provided at the center portion of the memory cell array. By providing the WLSG coupling portion at the center portion, even when the size of a block BLK (data size of one page) increases, the effective interconnect length of the word line WL from the WLSG coupling portion to an end of the cell portion is reduced. Accordingly, the delay of the voltage propagation in the word line WL can be suppressed. For example, when the data size of one page in the configuration of the first embodiment is 8 KB, in the configuration of the present embodiment, the data size of one page can be 16 KB while the effective interconnect length of the word line WL is maintained at the same level (while the delay of the voltage propagation in the word line WL is suppressed to the same level).

3 FIG. 11 4 11 1 11 2 11 3 Other configurations are similar to those in. The bit lines BLa of the memory cell array_are coupled to the bit lines BLa of the memory cell array_. The bit lines BLb of the memory cell array_are coupled to the bit lines BLb of the memory cell array_.

2.2 Planar Configuration of Memory Cell Array

11 11 2 11 1 18 11 0 3 11 3 11 1 11 4 11 2 17 18 FIGS.and 17 FIG. 18 FIG. 17 FIGS. 17 18 FIGS.and Next, an example of the configuration of the memory cell arraywill be described with reference to.is a plan view of the memory cell array_.is a plan view of the memory cell array_. Note that, in the example ofand, in order to simplify the description, a case will be described where each memory cell arrayincludes four blocks BLKto BLK, and each block BLK includes one string unit SU. In addition, in the example of, insulating layers are omitted. The configuration of the memory cell array_is similar to that of the memory cell array_. The configuration of the memory cell array_is similar to that of the memory cell array_.

11 2 First, the planar configuration of the memory cell array_will be described.

17 FIG. 0 2 3 2 As illustrated in, four blocks BLK_to BLK_are arranged side by side in the Y direction from the upper side toward the lower side in the drawing.

11 2 The cell portions are provided at both ends of the memory cell array_in the X direction. The configuration of the cell portion is similar to that in the first embodiment. A plurality of bit lines BLb are arranged side by side in the X direction above the memory pillars MP. The bit line BLb extends in the Y direction. The memory pillars MP of each block BLK are each electrically coupled to any of the bit lines BLb.

11 2 The WLSG coupling portion is provided at the center portion of the memory cell array_. In other words, the WLSG coupling portion is provided between the two cell portions arranged side by side in the X direction.

1 1 0 2 1 1 2 1 2 2 1 3 2 1 1 0 1 1 1 2 1 3 1 4 1 1 111 1 111 1 111 111 1 111 1 111 17 FIG. s w w w w w d The WLSG coupling portion of each block BLK includes a CPregion. The CPregion of the block BLK_and the CPregion of the block BLK_are arranged at different positions in the X direction. In addition, the CPregion of the block BLK_and the CPregion of the block BLK_are arranged at different positions in the X direction. In the example of, similar to the first embodiment, seven contact plugs CP_, CP_, CP_, CP_, CP_, CP_, and CP_are arranged in this order in one CPregion. An interconnect layeris provided on each contact plug CP. The interconnect layerextends in the Y direction from a coupling position with the contact plug CPto the adjacent block BLK. Electrode pads PD are provided on the interconnect layers. One end of the interconnect layeris coupled to the contact plug CP, and the other end of the interconnect layeris electrically coupled to the electrode pad PD. In each block BLK, the relationship of the arrangement between the contact plug CP, the interconnect layer, and the electrode pad PD is the same as that in the first embodiment.

11 1 11 2 Next, the planar configuration of the memory cell array_will be described. Hereinafter, differences from the planar configuration of the memory cell array_will be mainly described.

18 FIG. 11 2 As illustrated in, the configuration of the cell portion is similar to that in the memory cell array_. A plurality of bit lines BLa are arranged side by side in the X direction above the memory pillars MP. The bit line BLa extends in the Y direction. The memory pillars MP of each block BLK are each electrically coupled to any of the bit lines BLa.

11 1 The WLSG coupling portion is provided at the center portion of the memory cell array_.

1 2 The WLSG coupling portion of each block BLK includes a CPregion and a CPregion.

1 11 2 1 11 1 1 11 2 The configuration of the CPregion is similar to that in the memory cell array_. For example, the CPregions of the memory cell array_are arranged above the CPregions of the memory cell array_in the Z direction.

2 1 2 0 1 2 1 1 2 2 1 2 3 1 The CPregion of each block BLK is, for example, arranged side by side with the CPregion in the X direction. Therefore, the CPregion of the block BLK_and the CPregion of the BLK_are arranged at different positions in the X direction. In addition, the CPregion of the block BLK_and the CPregion of the block BLK_are arranged at different positions in the X direction.

2 2 2 1 11 2 111 10 2 17 FIG. The CPregion is a region in which a plurality of contact plugs CPare provided. The contact plugs CPare electrically coupled with the contact plugs CPof the memory cell array_via the electrode pads PD and the interconnect layersof the array chip_described in.

18 FIG. 2 2 0 2 1 2 2 2 3 2 4 2 2 2 1 11 2 s w w w w w d In the example of, seven contact plugs CP_, CP_, CP_, CP_, CP_, CP_, and CP_are arranged in this order in one CPregion. The seven contact plugs CPcorrespond to the respective seven contact plugs CPof the memory cell array_.

111 1 2 1 0 1 4 1 1 2 0 2 4 2 2 111 111 11 1 w w d s w w d s Interconnect layersare provided on the contact plugs CPand CP. The contact plugs CP_to CP_, and CP_and CP_are respectively coupled to the contact plugs CP_to CP_, and CP_and CP_of the adjacent block BLK via the interconnect layers. Electrode pads PD are provided on the interconnect layerson the memory cell array_.

2.3 Advantageous Effects According to Present Embodiment

With the configuration according to the present embodiment, advantageous effects similar to those of the first embodiment can be obtained.

11 1 11 2 11 3 11 4 According to above embodiment, a semiconductor memory device includes: a first memory cell array (_); a second memory cell array (_) arranged above the first memory cell array in a first direction (Z direction); a third memory cell array (_) arranged adjacent to the first memory cell array in a second direction (X direction) intersecting with the first direction; a fourth memory cell array (_) arranged above the third memory cell array in the first direction and arranged adjacent to the second memory cell array in the second direction; a first word line (WLa) coupled to the first memory cell array and the second memory cell array; a second word line (WLb) coupled to the third memory cell array and the fourth memory cell array; a first bit line (BLa) coupled to the first memory cell array and the fourth memory cell array; and a second bit line (BLb) coupled to the second memory cell array and the third memory cell array.

By applying the above embodiment, it is possible to provide a semiconductor memory device capable of suppressing an increase in the chip area.

Note that the embodiments are not limited to the embodiments described above, and various modifications may be applicable.

20 10 1 10 2 For example, in the above embodiments, a case is described where the circuit chipand the two array chips_and_are bonded. However, these configurations may be formed on one semiconductor substrate.

Furthermore, the “couple” in the above embodiments includes a state where coupling is indirectly made by interposing, for example, other components such as a transistor or a resistor between components to be coupled.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.