Resistor ladder-based multi-reference voltage generator with headroom increasing circuitry

This disclosure relates generally to voltage generators, and in particular, to a resistor ladder-based multi-reference voltage generator with headroom increasing circuitry.

Many circuits require a reference voltage to perform its operation. For example, certain analog-to-digital converters (ADCs) may use a reference voltage to convert an input analog signal into an output analog signal. In certain receivers that employ in-phase (I) and quadrature-phase (Q) demodulation and processing, an I-ADC is included to convert an I-analog signal into an I-digital signal using a first reference voltage, and a Q-ADC is included to convert a Q-analog signal into a Q-digital signal using a second reference voltage. In such receivers, a multi-voltage reference voltage generator may be used to generate the first and second reference voltages.

The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

An aspect of the disclosure relates to a multi-reference voltage generator. The multi-reference voltage generator, includes: a current source; a set of resistors coupled in series with the current source between an upper voltage rail and a lower voltage rail; a first set of switching devices coupled between a first output and a set of taps at respective terminals of the set of resistors, wherein the set of taps includes a first tap and a second tap; a second set of switching devices coupled between a second output and the set of taps, respectively; a switching device coupled between the first tap and the second tap; and a control circuit including an output coupled to a control input of the switching device.

Another aspect of the disclosure relates to a method of generating first and second reference voltages. The method includes: generating a current through a set of resistors to generate a set of voltages at a set of taps coupled to the set of resistors, respectively; outputting one of the set of voltages at a first selected tap as the first reference voltage; outputting the one or another of the set of voltages at a second selected tap as the second reference voltage; and coupling a first tap to a second tap of the set of taps based on the first selected tap.

To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.

The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. The term “substantially” means that the associated parameter may not be exact as indicated but accounts for some variation due to specified tolerances.

1 FIG. 100 100 105 110 115 100 120 125 140 150 100 130 135 140 155 100 160 165 illustrates a block diagram of an example receiverin accordance with an aspect of the disclosure. The receiverincludes an antenna, a band pass filter (BPF), and a low noise amplifier (LNA). The receiverfurther includes an in-phase (I) signal processing circuit including a mixer, a baseband filter (BBF), a variable gain amplifier (VGA), and an analog-to-digital converter (ADC). The receiveralso includes a quadrature-phase (I) signal processing circuit including a mixer, a BBF, a VGA, and an ADC. Common to both the I- and Q-signal processing circuits, the receiverincludes a local oscillator (LO)and a reference voltage generator (RV-GEN).

105 110 115 160 120 125 140 130 135 145 RX1 RX1 RX2 LOI LOQ RX2 LOI BBI RX2 LOQ BBQ The antennais configured to wirelessly pick-up/sense a first received radio frequency (RF) signal S. The BPFand LNAare configured to respectively band pas filter and low noise amplify the first received RF signal Sto generate a second received RF signal S. The LOis configured to generate an in-phase (I) LO signal fand a quadrature-phase (Q) LO signal f. The mixeris configured to mix the second RF signal Swith the in-phase (I) LO signal fto generate a mixed signal, which is further filtered by the BBFand amplified by the VGAto generate an in-phase (I) analog baseband signal S. Similarly, the mixeris configured to mix the second RF signal Swith the quadrature-phase (Q) LO signal fto generate a mixed signal, which is further filtered by the BBFand amplified by the VGAto generate a quadrature-phase (I) analog baseband signal S.

150 165 155 165 150 155 165 BBI I REFI BBQ Q REFQ I Q REFI REFQ The ADCis configured to convert the in-phase (I) analog baseband signal Sinto an in-phase (I) digital signal Dbased on an in-phase (I) reference voltage Vgenerated by reference voltage generator. The ADCis configured to convert the quadrature-phase (I) analog baseband signal Sinto a quadrature-phase (Q) digital signal Dbased on a quadrature-phase (Q) reference voltage Vgenerated by the reference voltage generator. For the ADCsandto accurately generate the in-phase (I) and quadrature-phase (Q) digital signals Dand D, the reference voltage generatorshould generate accurate (e.g., by calibration) in-phase (I) and quadrature-phase (Q) reference voltages Vand V, respectively.

2 FIG. 200 200 165 100 200 210 225 230 245 250 illustrates a block/schematic diagram of an example reference voltage generatorin accordance with another aspect of the disclosure. The reference voltage generatormay be an example implementation of the reference voltage generatorof receiver. The reference voltage generatorincludes an in-phase (I) resistor ladder-based single reference voltage generator, an I-buffer, a quadrature-phase (Q) resistor ladder-based single reference voltage generator, a Q-buffer, and a calibration control circuit.

210 215 220 215 220 215 220 1 250 225 220 B1 B1 REFI REFI The I-resistor ladder-based single reference voltage generatorincludes a current sourcecoupled in series with a resistor ladderbetween an upper voltage rail VDD and a lower voltage rail (e.g., ground). The current sourceis configured to generate a first bias current Ithat flows through the resistor ladderto generate a set of selectable reference voltages. A bias voltage V, which may be the highest one of the set of selectable reference voltages, is generated at a node between the current sourceand the resistor ladder. A first select signal sel, generated by the calibration control circuit, is configured to select one of the set of selectable reference voltages to output as an unbuffered I-reference voltage V. The I-bufferis configured to buffer the resistor ladderto output the I-reference voltage V.

230 235 240 235 240 235 240 2 250 245 240 B2 B2 REFQ REFQ The Q-resistor ladder-based single reference voltage generatorincludes a current sourcecoupled in series with a resistor ladderbetween the upper voltage rail VDD and the lower voltage rail. The current sourceis configured to generate a second bias current Ithat flows through the resistor ladderto generate a set of selectable reference voltages. A bias voltage V, which may be the highest one of the set of selectable reference voltages, is generated at a node between the current sourceand the resistor ladder. A second select signal sel, generated by the calibration control circuit, is configured to select one of the set of selectable reference voltages to output an unbuffered Q-reference voltage V. The Q-bufferis configured to buffer the resistor ladderto output the Q-reference voltage V.

250 225 245 250 1 2 225 245 250 1 2 REFI REFQ REFI REFQ The calibration control circuitincludes inputs coupled to outputs of the I-bufferand Q-buffer, respectively. The calibration control circuitis configured to generate the control signals seland selbased on the I- and Q-reference voltages Vand Vgenerated by the I-bufferand Q-buffer, respectively. Accordingly, through the aforementioned feedback arrangement, the calibration control circuitis configured to calibrate the I- and Q-reference voltages Vand Vvia the control signals seland sel, respectively.

3 FIG. 300 300 300 215 235 300 310 320 325 340 345 350 illustrates a block/schematic diagram of another example reference voltage generatorin accordance with another aspect of the disclosure. The reference voltage generatormay be an example implementation of the reference voltage generator, in particular, with respect to the current sourcesand. The reference voltage generatorincludes a current mirror, an in-phase (I) resistor ladder, an I-buffer, a quadrature-phase (Q) resistor ladder, a Q-buffer, and a calibration control circuit.

310 0 315 0 315 0 REF The current mirrorincludes a p-channel field effect transistor (PFET) Mcoupled in series with a reference current sourcebetween an upper voltage rail VDD and a lower voltage rail (e.g., ground). That is, the PFET Mincludes a source coupled to the upper voltage rail VDD. The reference current source, which is configured to generate a reference current I, is coupled between a gate and a drain of the (diode-connected) PFET Mand the lower voltage rail.

1 320 1 0 320 2 340 2 0 340 The PFET Mis coupled between the upper voltage rail VDD and the I-resistor ladder. That is, the PFET Mincludes a source coupled to the upper voltage rail VDD, a gate coupled to the gate and drain of PFET M, and a drain coupled to the I-resistor ladder. The PFET Mis coupled between the upper voltage rail VDD and the Q-resistor ladder. That is, the PFET Mincludes a source coupled to the upper voltage rail VDD, a gate coupled to the gate and drain of PFET M, and a drain coupled to the Q-resistor ladder.

0 1 2 1 2 200 320 1 1 350 325 320 B1 B2 REF B1 B1 REFI REFI Due to a current mirror coupling between the PFET Mand the PFETs Mand M, the PFETs Mand Mare configured to generate bias currents Iand Ibased on the reference current I. Similarly, as discussed with respect to multi-reference voltage generator, the I-resistor ladderis configured to generate a set of selectable reference voltages based on the first bias current I. A first bias voltage V, which may be the highest one of the set of selectable reference voltages, is generated at the drain of the PFET M. A first select signal sel, generated by the calibration control circuit, is configured to select one of the set of selectable reference voltages to output as an unbuffered I-reference voltage V. The I-bufferis configured to buffer the I-resistor ladderto output the I-reference voltage V.

340 2 2 350 345 340 350 325 345 1 2 B2 B2 REFI REFQ REFI REFQ The Q-resistor ladderis configured to generate a set of selectable reference voltages based on the second bias current I. A second bias voltage V, which may be the highest one of the set of selectable reference voltages, is generated at the drain of the PFET M. A second select signal sel, generated by the calibration control circuit, is configured to select one of the set of selectable reference voltages to output as an unbuffered Q-reference voltage V. The Q-bufferis configured to buffer the Q-resistor ladderto output the Q-reference voltage V. The calibration control circuit, including inputs coupled to the outputs of the I-bufferand Q-buffer, is configured to calibrate the I- and Q-reference voltages Vand Vvia the control signals seland sel, respectively.

200 300 100 220 320 240 340 REFI REFQ REFI REFQ I Q REF B1 B2 An issue with the multi-reference voltage generatorsandis significant mismatch between the temperature drifts of the I- and Q-reference voltages Vand V. The discrepancy in temperature drifts of the reference voltages Vand Vmay cause error in the generating of the I- and/or Q-data signals Dand Din receiver. Such discrepancy in the temperature drafts may be due to inaccuracy and mismatch in the mirroring of the reference current Ito the first and second bias currents Iand I. The temperature drifts discrepancy also may be due to mismatches in the resistors of the I- and Q-resistor ladders/and/.

4 FIG. 400 400 400 410 425 430 440 REFI REFQ REFI REFQ illustrates a block/schematic diagram of another example multi-reference voltage generatorin accordance with another aspect of the disclosure. The multi-reference voltage generatormay solve the discrepancy in the temperature drifts of the of the I- and Q-reference voltages Vand Vby employing a common current source and a common resistor ladder in connection with generating the reference voltages Vand V. In particular, the multi-reference voltage generatorincludes an I/Q resistor ladder-based multi-reference voltage generator, an I-buffer, a Q-buffer, and a calibration control circuit.

410 415 420 415 420 420 1 420 2 415 420 B REFI REFQ B The I/Q resistor ladder-based multi-reference voltage generatorincludes a current sourceand a resistor ladder. The current sourceis configured to generate a bias current Iflowing through the resistor ladderto generate a set of selectable reference voltages. The resistor ladderis configured to output one of the set of selectable reference voltages as an unbuffered I-reference voltage Vbased on a first select signal sel. The resistor ladderis also configured to output one of the set of selectable reference voltages as an unbuffered Q-reference voltage Vbased on a second select signal sel. A bias voltage V, which may be the highest one of the set of selectable reference voltages, is generated at a node between the current sourceand the resistor ladder.

425 420 430 420 440 425 430 440 1 2 425 430 440 1 2 REFI REFQ REFI REFQ REFI REFQ The I-bufferis configured to buffer the resistor ladderto output the I-reference voltage V. The Q-bufferis also configured to buffer the resistor ladderto output the Q-reference voltage V. The calibration control circuitincludes inputs coupled to outputs of the I-bufferand Q-buffer, respectively. The calibration control circuitis configured to generate the control signals seland selbased on the I- and Q-reference voltages Vand Vgenerated by the I-bufferand Q-buffer, respectively. Accordingly, through the aforementioned feedback arrangement, the calibration control circuitis configured to calibrate the I- and Q-reference voltages Vand Vvia the control signals seland sel, respectively.

5 FIG. 500 500 400 415 500 510 520 525 530 540 illustrates a block/schematic diagram of another example reference voltage generatorin accordance with another aspect of the disclosure. The reference voltage generatormay be an example implementation of the reference voltage generator, in particular, with respect to the current source. The reference voltage generatorincludes a current mirror, an I/Q resistor ladder, an I-buffer, a Q-buffer, and a calibration control circuit.

510 0 515 0 515 0 1 520 1 0 520 REF The current mirrorincludes a PFET Mcoupled in series with a reference current sourcebetween an upper voltage rail VDD and a lower voltage rail (e.g., ground). That is, the PFET Mincludes a source coupled to the upper voltage rail VDD. The reference current source, which is configured to generate a reference current I, is coupled between a gate and a drain of the (diode-connected) PFET Mand the lower voltage rail (e.g., ground). The PFET Mis coupled between the upper voltage rail VDD and the I/Q resistor ladder. That is, the PFET Mincludes a source coupled to the upper voltage rail VDD, a gate coupled to the gate and the drain of PFET M, and a drain coupled to the I/Q resistor ladder.

0 1 1 520 1 1 2 540 525 530 520 540 525 530 1 2 B REF B B REFI REFQ REFI REFQ REFI REFQ Due to a current mirror coupling between the PFET Mand the PFET M, the PFET Mis configured to generate a bias current Ibased on the reference current I. Similarly, the I/Q resistor ladderis configured to generate a set of selectable voltages based on the bias current I. A bias voltage V, which may be the highest one of the set of selectable voltages, is generated at the drain of the PFET M. First and second select control signals seland sel, generated by the calibration control circuit, are configured to select the same or different ones of the set of selectable voltages to output as unbuffered I- and Q-reference voltages Vand V, respectively. The I- and Q-buffersandare configured to buffer the I/Q resistor ladderto output the I- and Q-reference voltages Vand V, respectively. The calibration control circuit, including inputs coupled to the outputs of the I-bufferand Q-buffer, is configured to calibrate the I- and Q-reference voltages Vand Vvia the control signals seland sel, respectively.

6 FIG. 600 600 210 230 320 340 600 610 0 0 illustrates a schematic diagram of an example resistor ladder-based single reference voltage generatorin accordance with another aspect of the disclosure. The resistor ladder-based single reference voltage generatormay be an example of one of the resistor ladder-based single reference voltage generator,,, orpreviously discussed. The reference voltage generatorincludes a current source, a set of N+1 resistors Rto RN, and a set of N+1 switching devices SWto SWN.

610 1 0 600 600 0 0 1 0 N 0 N The current sourceis coupled between an upper voltage rail VDD and a node n. The set of N+1 resistors Rto RN are coupled in series, in that order, between a lower voltage rail (e.g., ground) and an output of the resistor ladder-based single reference voltage generator. The upper terminals (closest to the output of the resistor ladder-based single reference voltage generator) of the set of N+1 resistors Rto RN may be referred to as taps Tto T, respectively. The set of N+1 switching devices SWto SWN are coupled between the node nand the set of taps Tto T, respectively.

610 0 250 350 0 0 600 0 1 0 0 B REF REF REF B th th The current sourceis configured to generate a bias current I. The states ON/OFF (closed/open) of the set of N+1 switching devices SWto SWN may be controlled by a select control signal sel, for example, generated by calibration control circuitor. The select control signal sel is configured to set one (e.g., the j) of the set of N+1 switching devices SWto SWN to an ON (closed) state, and the remaining (e.g., ≠j) of the set of N+1 switching devices SWto SWN to OFF (open) states. In such configuration, the resistor ladder-based single reference voltage generatoris configured to generate a reference voltage Vat the tap coupled to the switching device whose state is ON (closed) as set by the select control signal sel. The reference voltage Vmay be given by the following equation: V=I*(j*R+R), where R is the resistance of each of the resistors Rto RN, j is the switching device SWj that is turned ON (closed), Ris the resistance of resistor R.

B REF REF REF 1 610 610 1 610 Note that the voltage Vat node nis substantially the same as the output reference voltage V. In such configuration, there should not be any headroom issues associated with the current source. For example, the supply voltage at the upper voltage rail VDD should be sufficiently high enough to accommodate the target reference voltage Vwithout collapsing or adversely affecting the operation of the current source(e.g., by operating the corresponding PFET Min the triode region). As a more specific example, the supply voltage VDD may be set to 1.2 Volts (V), and the target reference voltage Vmay be at about 0.6V. This results in a 0.6V voltage drop (or drain-to-source voltage Vds) across the current source, which provides sufficient margin over its minimum saturation voltage Vdsat of, for example, 0.3V.

7 FIG. 700 700 420 520 700 710 0 10 1 20 2 illustrates a schematic diagram of another example resistor ladder-based multi-reference voltage generatorin accordance with another aspect of the disclosure. The resistor ladder-based multi-reference voltage generatormay be an example of one of the resistor ladder-based multi-reference voltage generatororpreviously discussed. The reference voltage generatorincludes a current source, a set of N+1 resistors Rto RN, a first set of N+1 switching devices SWto SWN, and a second set of N+1 switching devices SWto SWN.

710 0 0 10 1 700 20 2 700 0 N REF1 0 N REF2 0 N The current sourceand the set of N+1 resistors Rto RN are coupled in series between an upper voltage rail VDD and a lower voltage rail (e.g., ground). The upper terminals (closest to the upper voltage rail VDD) of the set of N+1 resistors Rto RN may be referred to as taps Tto T, respectively. The first set of N+1 switching devices SWto SWN are coupled between a first reference voltage (V) output of the resistor ladder-based multi-reference voltage generatorand the set of taps Tto T, respectively. The second set of N+1 switching devices SWto SWN are coupled between a second reference voltage (V) output of the resistor ladder-based multi-reference voltage generatorand the set of taps Tto T, respectively.

10 1 440 540 1 10 1 10 1 20 2 2 440 540 2 20 2 20 2 th th th th The states ON/OFF (closed/open) of the first set of N+1 switching devices SWto SWIN may be controlled by a first select control signal sel, for example, generated by calibration control circuitor. The first select control signal selis configured to set one (e.g., the j) of the first set of N+1 switching devices SWto SWN to an ON (closed) state, and the remaining (e.g., ≠j) of the first set of N+1 switching devices SWto SWN to OFF (open) states. Similarly, the states ON/OFF (closed/open) of the second set of N+1 switching devices SWto SWN may be controlled by a second select control signal sel, for example, also generated by calibration control circuitor. The second select control signal selis configured to set one (e.g., the k) of the second set of N+1 switching devices SWto SWN to an ON (closed) state, and the remaining (e.g., ≠k) of the second set of N+1 switching devices SWto SWN to OFF (open) states.

710 0 700 1 0 1 1 0 0 B 0 N REFI j REF1 REF B th j The current sourceis configured to generate a bias current Ithat flows through the set or resistors Rto RN to generate a set of selectable voltages at the set of taps Tto T, respectively. In such configuration, the resistor ladder-based multi-reference voltage generatoris configured to output a first reference voltage Vat the tap (e.g., T) coupled to the switching device (e.g., the j) of the first set whose state is ON (closed) as set by the first select control signal sel. Accordingly, the first reference voltage Vmay be given by the following equation: V1=I*(j*R+R), where R is the resistance of each of the resistors Rto RN, j is the switching device SWthat is turned ON (closed), and Ris the resistance of resistor R.

700 2 0 2 REF2 REF2 REF B th k Similarly, the resistor ladder-based multi-reference voltage generatoris configured to generate a second reference voltage Vat the tap (e.g., Tk) coupled to the switching device (e.g., the k) of the second set whose state is ON (closed) as set by the second select control signal sel. Accordingly, the second reference voltage Vmay be given by the following equation: V2=I*(k*R+R), where k is the switching device SW. It shall be understood that j and k may be equal to or different from each other (e.g., j=k or j≠k).

600 610 710 700 0 710 710 710 B B B B B B In contrast to the resistor ladder-based single reference voltage generatorwhere the bias voltage V(e.g., at the lower terminal (e.g., drain) of the current source(e.g., PFET)) is set to approximately the target reference voltage (e.g., 0.6V), the bias voltage V(e.g., at the lower terminal (e.g., drain) of the current source(e.g., PFET)) of the resistor ladder-based multi-reference voltage generatoris set to the maximum of the range of the set of selectable voltages (e.g., V=I*(N*R+R)). As a consequence, the bias voltage Vmay present headroom issues for the current sourceespecially for a high voltage process corner. For example, the bias voltage Vfor a high voltage process corner at above 0.9V may result in the current source (PFET)operating with a drain-to-source voltage Vds lower than its minimum saturation voltage Vdsat. As a result, the current source (PFET)operates in its triode region, and consequently, ineffectively as a current source.

8 FIG.A 800 800 710 700 800 700 810 0 10 1 20 2 illustrates a schematic/block diagram of another example resistor ladder-based multi-reference voltage generatorin accordance with another aspect of the disclosure. The resistor ladder-based multi-reference voltage generatorincludes circuitry that addresses the headroom issue associated with the current sourceof the resistor ladder-based multi-reference voltage generator. The resistor ladder-based multi-reference voltage generatoris similar to resistor ladder-based multi-reference voltage generatorincluding a current source, a set of N+1 resistors Rto RN, a first set of N+1 switching devices SWto SWN, and a second set of N+1 switching devices SWto SWN in the same arrangement as previously discussed in detail.

800 720 820 1 1 1 820 820 1 1 N n+m REF2 REFI The resistor ladder-based multi-reference voltage generatorfurther includes a control circuitand a “shorting” switching device SWs. The control circuitis configured to receive one of the select control signals (e.g., sel) and generate a control signal (CS) that controls a state ON/OFF (closed/open) of the shorting switching device SWs based on the select control signal sel. The shorting switching device SWs is coupled between a first tap (e.g., the top tap T) and a second tap (e.g., an intermediate tap T). The variable “n” refers to a tap threshold value of the first select control signal selat (or below) which the control circuitgenerates the control signal (CS) to close the shorting switching device SWs, or above which the control circuitgenerates the control signal (CS) to open the shorting switching device SWs (e.g., sel≤n→CS→SWs is closed; sel>n→CS→SWS is open). The variable “m” is a margin in the case where the second reference voltage Vneeds to be higher than the first reference voltage Vas discussed further herein. As an example, the tap threshold n may be equal to N/2 (e.g., n=16 where N=32) and m may be equal to four (4) (e.g., m=4).

1 1 810 820 800 700 n REF1 B For example, if the first select signal selis greater than the tap threshold “n” (e.g., sel>n), it implies a relatively low process corner because a voltage at a higher tap (e.g., above T) is required to generate the target first reference voltage V. Because a relatively low process corner is relevant in this example, the bias voltage Vshould likewise be relatively low to provide a sufficient voltage drop across the current source (PFET)so that it operates effectively as a current source (e.g., operates in the saturation region of the corresponding PFET). Accordingly, the control circuitgenerates the control signal (CS) to open the shorting switching device SWs; and thereby, the resistor ladder-based multi-reference voltage generatoris functionally configured per resistor ladder-based multi-reference voltage generator.

1 1 810 820 0 0 820 810 n REF1 B B B B B B N n+m If the first select signal selis less than or equal to the tap threshold “n” (e.g., sel≤n), it implies a relatively high process corner because a voltage at a lower tap (e.g., at or below T) is required to generate the target first reference voltage V. Because a relatively high process corner is relevant in this example, the high bias voltage Vmay cause a headroom issue for the current source. Accordingly, the control circuitgenerates the control signal (CS) to close the shorting switching device SWs. As a result of closing the shorting switching device SWs, the bias voltage Vmay be lowered in accordance with the following equation: V=I*((n+m)*R+R) where n+m<N. This may be significantly less than the maximum range of the set of selectable voltage given by V=I*(N)*R+R). Thus, the control circuitand shorting switching device SWs coupled between taps Tand Tprotect the current sourcefrom headroom issues.

REF2 REF1 n REF2 REF1 REF2 1 2 1 800 With regard to the variable “m”, the second reference voltage Vmay be greater than the first reference voltage V. So, if the first select signal selindicates a tap slightly below or at “n”, and the second select signal selindicates a tap slightly higher than the first select signal sel, the variable “m” provides m taps above tap Tavailable for generating the second reference voltage V. As the first and second reference voltages Vand Vshould be close to each other, a value of four (4) for “m” may be appropriate for a resistor ladder with N=32. The value of “m” may be different for other configurations of the resistor ladder-based multi-reference voltage generator.

8 FIG.B B B B B B HR 0 800 0 0 810 illustrates a graph of an example bias voltage Vversus product of total resistance and bias current (I*(N)*R+R) associated with the resistor ladder-based reference voltage generatorin accordance with another aspect of the disclosure. The horizontal axis of the graph represents the process corner as indicated by the product of the bias current Iand the total resistance of the set of resistors Rto RN (e.g., I*(N*R+R)). The vertical axis represents the bias voltage V. A horizontal dash line represents the headroom threshold THabove which the current sourceencounters headroom issues.

B B B HR B 0 810 810 The thin-solid line represents the bias voltage Vincrease with increase in the process corner in the hypothetical case where the shorting switching device SWs remains open for the entire range of the process corner (e.g., I*(N)*R+R)). As shown, at high process corners, the bias voltage Vapproaches and may exceed the headroom threshold TH; thereby causing headroom issues for the current source. The long-dashed line presents the increase in the bias voltage Vwith process corner for the case where the shorting switching device SWs is closed. As shown, even for high process corners, the closing of the shorting switching device SWs provides extra headroom so as to prevent headroom issues for the current source.

800 0 1 820 B 0 N REF1 REF2 B The thick-solid line represents the operation of the resistor ladder-based multi-reference voltage generator. That is, at relative low process corners (e.g., I*(N)*R+R)) as indicated by the first select signal selbeing greater than the tap threshold “n”, the control circuitgenerates the control signal (CS) to set the shorting switching device SWs in its open state. This makes available the set of voltages at the entire set of taps Tto Tfor generating the first and second reference voltages Vand Vfollowing the bias voltage Vthin-sold line associated with the case where the shorting switching device SWs is open.

B 0 n REF1 0 n+m REF2 B 0 1 820 810 At relative high process corners (e.g., I*(N)*R+R)) as indicated by the first select signal selbeing equal to or less than “n”, the control circuitgenerates the control signal (CS) to set the shorting switching device SWs in its closed state. This makes available the set of voltages at a subset of taps Tto Tfor generating the first reference voltage Vand taps Tto Tfor generating the second reference voltage Vas indicated by the thick-solid line following the bias voltage Vlong-dashed line associated with the case where the shorting switching device SWs is closed. This prevents headroom issues for the current sourceas indicated by the extra headroom margin indicated in the graph.

9 FIG. 900 900 910 illustrates a flow diagram of an example methodof generating multiple reference voltages (e.g., a first reference voltage and a second reference voltage) in accordance with another aspect of the disclosure. The methodincludes generating a current through a set of resistors to generate a set of voltages at a set of taps coupled to the set of resistors, respectively (block). Examples of means for generating a current through a set of resistors to generate a set of voltages at a set of taps coupled to the set of resistors, respectively, include any of the current sources described herein.

900 920 10 1 900 930 20 2 The methodfurther includes outputting one of the set of voltages at a first selected tap as the first reference voltage (block). Examples of a means for outputting one of the set of voltages at a first selected tap as the first reference voltage include any of the first set of switching devices SWto SWN. Additionally, the methodincludes outputting the one or another of the set of voltages at a second selected tap as the second reference voltage (block). Examples of means for outputting the one or another of the set of voltages at a second selected tap as the second reference voltage include any of the second set of switching devices SWto SWN.

900 940 820 Further, the methodincludes coupling a first tap to a second tap of the set of taps based on the first selected tap (block). Examples of means for coupling a first tap to a second tap of the set of taps based on the first selected tap include the control circuitand the shorting switching device SWs.

Aspect 1: A multi-reference voltage generator, comprising: a current source; a set of resistors coupled in series with the current source between an upper voltage rail and a lower voltage rail; a first set of switching devices coupled between a first output and a set of taps at respective terminals of the set of resistors, wherein the set of taps includes a first tap and a second tap; a second set of switching devices coupled between a second output and the set of taps, respectively; a switching device coupled between the first tap and the second tap; and a control circuit including an output coupled to a control input of the switching device. Aspect 2: The multi-reference voltage generator of aspect 1, wherein the first tap is situated between the current source and the set of resistors. Aspect 3: The multi-reference voltage generator of aspect 1 or 2, wherein a subset of the set of resistors are situated between the current source and the second tap. Aspect 4: The multi-reference voltage generator of any one of aspects 1-3, wherein the control circuit includes an input coupled to a set of control inputs of the first set of switching devices, respectively. Aspect 5: The multi-reference voltage generator of any one of aspects 1-4, wherein: the set of taps are arranged consecutively from the lower voltage rail to the current source; the first set of switching devices are configured to receive a control signal indicating a number of one of the set of taps, the control signal closing the switching device coupled between the one of the set of taps and the first output, and opening the remaining ones of the first set of switching devices, wherein a first reference voltage is generated at the first output; and the control signal is configured to: close the switching device if the number of the one of the set of taps is at or below a tap threshold; and open the switching device if the number of the one of the set of taps is above the tap threshold. Aspect 6: The multi-reference voltage generator of aspect 5, wherein a number of the second tap is higher than the number of the one of the set of taps. Aspect 7: The multi-reference voltage generator of aspect 5 or 6, wherein the second set of switching devices are configured to receive a second control signal indicating a number of the one or another one of the set of taps, the second control signal closing the switching device of the second set of switching devices coupled between the one or the another one of the set of taps and the second output, and opening the remaining ones of the second set of switching devices, wherein a second reference voltage is generated at the second output. Aspect 8: The multi-reference voltage generator of any one of aspects 1-4, wherein: the first set of switching devices are configured to receive a first control signal identifying one of the first set of switching devices to close; and the control circuit is configured to close the switching device based on the one of the first set of switching devices to close. Aspect 9: The multi-reference voltage generator of aspect 8, wherein the control circuit is configured to close the switching device based on a number of the set of resistors between one of the set of taps to which the one of the first set of switching device is coupled and the lower voltage rail. Aspect 10: The multi-reference voltage generator of aspect 9, wherein the control circuit is configured to close the switching device if the number of the set of resistors the one of the set of taps and the lower voltage rail is at or below a tap threshold. Aspect 11: A method of generating first and second reference voltages, comprising: generating a current through a set of resistors to generate a set of voltages at a set of taps coupled to the set of resistors, respectively; outputting one of the set of voltages at a first selected tap as the first reference voltage; outputting the one or another of the set of voltages at a second selected tap as the second reference voltage; and coupling a first tap to a second tap of the set of taps based on the first selected tap. Aspect 12: The method of aspect 11, wherein the first tap is situated between a source of the current and the set of resistors. Aspect 13: The method of aspect 11 or 12, wherein a subset of the set of resistors are situated between a source of the current and the second tap. 11 Aspect 14: The method of claim, wherein: the set of taps are numbered in consecutive order from the tap farthest away from to the tap closest to a source of the current; and coupling the first tap to the second tap is based on the number of the first selected tap being at or below a tap threshold. Aspect 15: The method of aspect 14, further comprising decoupling the first tap from the second tap based on the number of the first selected tap being above the tap threshold. Aspect 16: The method of aspect 14 or 15, wherein the first tap is the tap closest to a source of the current. Aspect 17: The method of any one of aspects 14-16, wherein the number of the second tap is at or above the tap threshold. Aspect 18: The method of any one of aspects 11-13, wherein the coupling of the first tap to the second tap is based on a number of taps between the first selected tap and the tap farthest away from a source of the current. Aspect 19: The method of any one of aspects 11-18, wherein: outputting the one of the set of voltages at the first selected tap as the first reference voltage comprises closing a first switching device coupled between the first selected tap and a first output; and outputting the one or the another of the set of voltages at the second selected tap as the second reference voltage comprises closing a second switching device coupled between the second selected tap and a second output. Aspect 20: The method of any one of aspects 11-19, wherein coupling the first tap to the second tap comprises closing a switching device coupled between the first tap and the second tap. The following provides an overview of aspects of the present disclosure:

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.