Radio unit time alignment and delay characterization

In communication networks, such as networks utilizing the Open Radio Access Network (O-RAN) architecture, network throughput can be improved by accurately characterizing and accounting for network and/or device latency. However, accurately determining latency in a network device can be challenging due to, e.g., the use of ethernet packet data that can have variable latency due to the variable nature of network communications as well as the representation of packet data in the frequency domain. These challenges are a particular concern for use cases such as Ultra-Reliable-Low-Latency-Communication (URLLC) applications or the like, which require low and accurate latency designs for proper functionality.

The following summary is a general overview of various embodiments disclosed herein and is not intended to be exhaustive or limiting upon the disclosed embodiments. Embodiments are better understood upon consideration of the detailed description below in conjunction with the accompanying drawings and claims.

In an implementation, radio unit equipment is described herein. The radio unit equipment can include a buffer that stores input data received via a signal ingress point of the radio unit equipment, resulting in buffered data, and clock generation logic that provides a synchronized frame number (SFN) pulse to the buffer. The buffer can release the buffered data at a time corresponding to the SFN pulse and modified by a timing adjustment parameter, resulting in the buffered data proceeding from the buffer to a signal egress point of the radio unit equipment. The buffer can additionally determine the timing adjustment parameter based on a defined signal propagation delay between the buffer and the signal egress point of the radio unit equipment.

In another implementation, a system is described herein. The system can include a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can include transmitting a downlink test signal to a radio unit via a fronthaul connection of the radio unit, the downlink test signal having a defined frame start boundary; buffering the downlink test signal at the radio unit, resulting in buffered data; in response to an SFN pulse being observed at the radio unit, releasing the buffered data to an antenna port of the radio unit; and computing a downlink time delay associated with the radio unit as a difference between a first time, corresponding to the SFN pulse, and a second time, corresponding to the defined frame start boundary of the downlink test signal being observed at the antenna port of the radio unit.

In an additional implementation, another system is described herein. The system can include a processor and a memory that stores executable instructions that, when executed by the processor, facilitate performance of operations. The operations can include transmitting an uplink test signal to an antenna port of a radio unit, the uplink test signal having a defined frame start boundary; buffering the uplink test signal at the radio unit, resulting in buffered data; converting the uplink test signal to a baseband input signal; and determining an uplink time delay associated with the radio unit based on a result of cross correlating the baseband input signal with the buffered data.

Various specific details of the disclosed embodiments are provided in the description below. One skilled in the art will recognize, however, that the techniques described herein can in some cases be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring subject matter.

Various implementations described herein facilitate time alignment and delay characterization for a radio unit (RU), such as an Open Radio Unit (O-RU) operating in an Open Radio Access Network (O-RAN) architecture. While various examples provided herein relate specifically to O-RAN architectures, it is noted that these examples are provided merely for descriptive purposes and are not intended to limit the description or claimed subject matter to any particular technology, or combination of technologies, unless explicitly stated otherwise.

In the example of O-RAN operation, accurately determining RU latency can be challenging due to the use of ethernet packet data by an Enhanced Common Public Radio Interface (eCPRI), e.g., that provides fronthaul connectivity between an RU and a Distributed Unit (DU) and/or other devices, as such data can have variable latency due to the variability of fronthaul connectivity. Additionally, ethernet packet data is represented in the frequency domain, which can further contribute to the challenge in accurately characterizing latency.

Additionally, network devices, such as an O-RU or the like, can be associated with network standards that impose limits on time alignment error (TAE) and/or other timing properties. For instance, the Third Generation Partnership Project (3GPP) standards limit an acceptable relative TAE for multiple-input multiple-output (MIMO) and transmit diversity to 65 ns in either direction and an acceptable relative TAE for carrier aggregation to 260 ns in either direction. Other network standards, such as the O-RAN standard, also provide similar timing specifications. Furthermore, Ultra-Reliable-Low-Latency-Communication (URLLC) applications, such as those in an O-RAN Private Fifth Generation (P5G) network, can provide additional use cases that benefit from low and accurate latency designs.

As a result of the above, both low latency radio unit design and accurate timing characterization methodologies are desirable for optimal system performance and user experience. By way of example, timing issues and/or poor TAE can result in user equipment (UE) attachment failure, reduced throughput, and/or other degradations to network performance.

3 FIG. 5 FIG. To the furtherance of these and/or related ends, various implementations herein provide radio unit timing models for both downlink and uplink communication. As used herein, “downlink” refers to communications to a radio unit, e.g., from a distributed unit or other devices, while “uplink” refers to communications from a radio unit, e.g., to a distributed unit or the like. In contrast to approaches that involve complex delay models with multiple functional blocks that are prone to error, implementations described herein implement a buffer design for downlink and uplink communication that is triggered by a Synchronized Frame Number (SFN) pulse, which is in turn synchronized with a system grand master clock through Precision Time Protocol (PTP). As a result, in the downlink, only the time error (TE) after the buffer (e.g., as will be shown in) contributes to the downlink end-to-end TE. In the uplink, only the TE before the buffer (e.g., as will be shown in) contributes to the uplink end-to-end TE. As a result, the use of simpler timing models can be enabled. Additionally, various implementations herein provide a radio unit delay characterization apparatus that can leverage timing models as noted above to implement accurate and reliable methodologies to characterize downlink/uplink delay. As a result of the aforementioned buffer design and downlink/uplink delay characterization techniques, time alignment among antennas of an RU can be made independent of fronthaul delay. Other advantages of the implementations described herein are also possible.

1 FIG. 1 FIG. 100 100 10 10 10 With reference now to the drawings,illustrates a block diagram of a systemthat facilitates radio unit time alignment and delay characterization in accordance with various implementations described herein. Systemas shown inincludes a radio unit, also referred to herein as radio unit equipment, that can be utilized to facilitate wireless communication in a wireless communication network. In an implementation in which the radio unitoperates in an O-RAN network, the radio unitcan also be referred to as an O-RU. Other naming conventions can also be used.

10 110 12 10 110 110 110 110 110 1 FIG. 1 FIG. The radio unitshown inincludes a bufferthat can store input data received via a signal ingress pointof the radio unit. As used herein, data held by the bufferin this manner is referred to as buffered data. In various implementations, the buffercan include data storage devices, controller devices, and/or any other suitable physical components that enable the bufferto conditionally store input data. While not shown in, the buffercould also be controlled via a separate control unit that includes associated hardware and/or software components for controlling operation of the buffer.

10 120 110 110 110 110 110 14 10 1 FIG. The radio unitshown infurther includes clock generation logicthat can provide, among other signals or other information, an SFN pulse to the buffer. Based on the SFN pulse, the buffercan be configured to release its buffered data at a time corresponding to the SFN pulse and modified by a timing adjustment parameter. Stated another way, the buffercan apply a time delay or timing advance to the SFN pulse based on the timing adjustment parameter, resulting in a modified time, and release buffered data at the modified time. The buffered data, once released from the buffer, can then proceed from the bufferto a signal egress pointof the radio unit.

120 10 The clock generation logiccan be implemented in hardware, e.g., via an oscillator or other hardware components, in software, or as a combination of hardware and software. For a software-based implementation, the clock generation logic can operate based on instructions stored in a memory or other data store associated with the radio unitand executed by a processor. Other implementations could also be used.

12 14 10 12 14 12 14 3 4 FIGS.- 5 6 FIGS.- In various implementations, the identity of the signal ingress pointand signal egress pointcan vary depending on whether the radio unitis engaged in downlink or uplink communication. For the example of downlink communication, the signal ingress pointcan be an eCPRI or other interface that facilitates fronthaul communication with other network devices (e.g., a distributed unit) over a fiber connection or other suitable fronthaul communication medium, and the signal egress pointcan be an antenna port that facilitates over-the-air data communication to UEs and/or other suitable devices. Conversely, for uplink communication, the signal ingress pointcan be an antenna port and the signal egress pointcan be a fronthaul interface, e.g., as described above for downlink communication. An example model for downlink communication in this manner is described in further detail below with respect to, and an example model for uplink communication is described in further detail below with respect to.

110 110 14 10 110 12 110 10 110 14 110 10 7 9 FIGS.- In downlink implementations, the buffercan determine the timing adjustment parameter as noted above based on a defined signal propagation delay between the bufferand the signal egress point(e.g., an antenna port for downlink communication) of the radio unit. In uplink implementations, the buffercan determine the timing adjustment parameter as noted above based on a defined signal propagation delay between the signal ingress point(e.g., an antenna port for uplink communication) and the bufferof the radio unit. For instance, the timing adjustment parameter can account for data processing that occurs between the bufferand the signal egress point, such as time-frequency domain conversion or the like. In other implementations, the timing adjustment parameter can be provided to the buffervia external control logic and/or other means. In still other implementations, the signal propagation delay utilized to determine the timing adjustment parameter can be determined in advance, e.g., as will be described below with respect to, and stored in a database and/or another suitable data store at the radio unit.

2 FIG. 200 200 200 1 4 1 4 2 3 200 200 Referring now to, a diagramdepicting an example O-RAN delay model that can be utilized by various implementations described herein is illustrated. In particular, diagramshows a delay model for communications between an Open Distributed Unit (O-DU) and an O-RU. Additionally, diagramdenotes the reference points R-Rdefined for eCPRI, where Rand Rare the transmit and receive interfaces at the O-DU, respectively, and Rand Rare the receive and transmit interfaces at the O-RU, respectively. Additionally, the antenna interface at the O-RU is denoted in diagramas Ra. It is noted that while diagramillustrates an O-RAN delay model between an O-RU and an O-DU, similar concepts would also apply to other, non-O-RAN devices and networks.

200 1 4 1 2 12 3 4 34 12 34 Illustrated between the O-DU and O-RU in diagramis a fronthaul connection (e.g., a fiber connection, a transport connection, etc.) that connects the O-DU and O-RU through reference points R-R. The downlink transport delay, e.g., the delay from reference point Rto reference point R, is denoted as T, and the uplink transport delay, e.g., the delay from reference point Rto reference point R, is denoted as T. Here, the delay parameters Tand Tare equivalent to the fronthaul delay between the O-DU and O-RU.

12 34 2 3 200 200 1 4 a a In some implementations, the DU can compute the values of Tand Tusing techniques such as a defined transport method, a measured transport method, and/or other techniques generally known in the art. In addition, various implementations described herein provide simple timing models for the internal delay associated with the O-RU, e.g., delay parameters Tand Taas shown in diagram, and provide accurate and reliable characterization of those parameters in order for the O-DU to determine the total delay represented in diagramby Tand Ta.

2 3 200 a Accurate characterization of RU delay, e.g., Tand Ta, can be utilized by the network represented by diagramto facilitate time alignment between the O-DU and O-RU. In an example, the O-DU and O-RU can each structure communications into radio frames of a given time length (e.g., 10 ms) that utilize a common clock as a reference. This common clock can be provided to the O-RU by the O-DU, or alternatively a local clock can be utilized at the O-RU. In addition, the system can maintain a master clock signal, referred to as a grand master clock, that generates an SFN pulse at regular intervals (e.g., every 10 ms) that is aligned to the radio frames.

1 200 4 200 12 34 2 3 a a Based on the above framework, communications can be structured such that data is configured to arrive at the antenna port of the O-RU concurrently with the SFN pulse. Accordingly, the O-DU can be configured to send downlink data to the O-RU at an advance equal to the total downlink delay, e.g., Tas shown in diagram, such that data arrives at the antenna port of the O-RU at the SFN pulse. For uplink communication, the O-DU can utilize the total uplink delay, e.g., Taas shown in diagram, to determine a time at which uplink data, originating from the antenna port of the O-RU at the SFN pulse, can be received. As Tand Tare fixed parameters based on the properties of the fiber connection between the O-DU and O-RU, knowledge of the RU-side delay parameters Tand Taat the O-DU is advantageous to avoid excessive time alignment error.

2 3 a In some implementations, the RU delay parameters Tand Tacan be dependent on the design of the RU. Additionally, the RU delay parameters can be based on a carrier bandwidth used by the RU, as different bandwidths (e.g., 10 MHZ 20 MHZ, 40 MHZ, etc.) could have different values even on the same device. While various implementations are described herein with respect to a single carrier bandwidth, it is noted that the concepts described herein could also be applied to delay characterization for multiple carrier bandwidths without departing from the scope of this description or the claimed subject matter.

3 FIG. 3 FIG. 1 FIG. 3 FIG. 3 FIG. 3 FIG. 300 300 300 10 10 12 10 310 110 10 320 14 10 360 Turning now to, a block diagram of a radio unit downlink (DL) timing model, referred to herein as simply “model,” that can be utilized in accordance with various implementations described herein. Repetitive description of like parts described above with regard to other implementations is omitted for brevity. Modelas shown inrepresents a downlink signal path for a radio unit. With reference to the simplified radio unitshown in, the signal ingress pointof the radio unitshown inis an interface for a fronthaul connection to a distributed unit, e.g., an eCPRI/O-RAN interface, the bufferof the radio unitshown incorresponds to a frame delay variation (FDV) buffer, and the signal egress pointof the radio unitshown inis an antenna port.

10 330 310 320 10 340 350 360 310 350 300 10 3 FIG. The radio unitshown inincludes additional processing blocks, such as domain conversion logic (here, inverse fast Fourier transform (iFFT) logic) that can convert frequency domain data received via the eCPRI/O-RAN interfaceand buffered by the FDV bufferto time domain data. The radio unitfurther includes digital front-end logicand radio frequency (RF) front-end logicthat can perform respective operations to convert incoming downlink data to a format that can be transmitted via the antenna port. The blocks-shown in modelcan be implemented in hardware, software, or a combination of hardware and software, e.g., as appropriate for a given implementation of the radio unit.

300 2 10 2 1 2 2 320 320 120 2 2 10 a a a a 2 FIG. 1 FIG. As shown in model, the delay parameter Tof the radio unit(e.g., as described above with respect to) can be divided into two parts, referred to here as T_partand T_part, that are divided by the FDV buffer. Operation of the FDV buffercan be triggered based on an SFN pulse, e.g., provided by clock generation logicas described above with respect toand/or via other sources, which can result in only T_partcontributing to the total downlink delay of the radio unit.

400 402 120 310 120 4 FIG. With further reference to methodin, example operations that can be performed to achieve downlink time alignment in actual operation are described in further detail. At, the clock generation logiccan be synchronized with a grand master clock signal, e.g., as provided by a distributed unit via the eCPRI/O-RAN interfaceand/or by other sources, via PTP and/or other suitable protocols. Based on this synchronization, the clock generation logiccan generate an SFN pulse, which can also be synchronized with the system grand master through PTP or the like.

404 402 320 300 2 1 320 320 10 310 320 320 2 1 10 320 2 2 320 330 2 1 a a a a Next, at, the SFN pulse generated via the clock generation logic atcan be used to trigger the FDV bufferand/or another suitable downlink buffer. In model, the delay T_partprior to the FDV bufferdoes not contribute to the end-to-end TAE since the FDV buffercan accurately control the time to read out data. For instance, a distributed unit communicatively coupled to the radio unitvia the eCPRI/O-RAN interfacecan provide downlink data with a rough time advance relative to the SFN pulse that is larger than the advance utilized by the FDV buffer. In such an example, the FDV buffercan hold the incoming data based on a local, smaller frame advance, thereby excluding T_partas a contributor to the total delay. As a result, the total delay of the radio unitfrom the perspective of the FDV buffercan be equivalent to T_part, which can be a constant value due to data leaving the FDV bufferbeing converted to the time domain via the iFFT block, removing the uncertainty in T_partassociated with frequency domain data.

406 320 2 2 408 360 10 320 406 a As a result of the above, at, the FDV buffercan start to read out downlink data at a time determined by advancing the time of the SFN pulse by a timing adjustment parameter equal to T_part. At, the downlink data can reach the antenna portsimultaneously with, substantially concurrently to, a time at which the SFN pulse arrives at the radio unit, e.g., as a result of the advance applied by the FDV bufferat. As used herein, “substantially concurrently” refers to events that occur within a defined interval of time (e.g., as specified via a tolerance) of each other.

10 400 10 10 FIG. In an implementation in which the radio unitincludes multiple antennas, similar procedures to those described with respect to methodcan be applied, thereby achieving time alignment among multiple antennas. An example of a downlink signal path for a radio unitwith multiple antennas is described below with respect to.

5 FIG. 5 FIG. 1 FIG. 5 FIG. 5 FIG. 500 500 500 10 10 12 10 360 110 10 510 14 310 Referring now to, a block diagram of a radio unit uplink (UL) timing model, referred to herein as simply “model,” that can be utilized in accordance with various implementations described herein. Repetitive description of like parts described above with regard to other implementations is omitted for brevity. Modelas shown inrepresents an uplink signal path for a radio unit. With reference to the simplified radio unitshown in, the signal ingress pointof the radio unitshown inis the antenna port, the bufferof the radio unitshown incorresponds to an uplink buffer, and the signal egress pointof the radio unit is the fronthaul connection, e.g., implemented via the eCPRI/O-RAN interface.

10 10 520 360 510 340 350 310 340 350 510 520 500 10 3 FIG. 5 FIG. Similar to the radio unitshown in, the radio unitshown inincludes additional processing blocks, such as domain conversion logic (here, fast Fourier transform (FFT) logic) that can convert time domain data received via the antenna portand buffered by the uplink bufferto frequency domain data, digital front-end logic, and radio frequency (RF) front-end logic. The blocks,,,,shown in modelcan be implemented in hardware, software, or a combination of hardware and software, e.g., as appropriate for a given implementation of the radio unit.

300 3 10 500 3 1 3 2 510 510 120 3 1 10 3 FIG. 1 FIG. Similar to modelin, the delay parameter Taof the radio unitshown in modelcan be divided into two parts, referred to here as Ta_partand Ta_part, that are divided by the uplink buffer. Operation of the uplink buffercan be triggered based on an SFN pulse, e.g., provided by clock generation logicas described above with respect toand/or via other sources, which can result in only Ta_partcontributing to the total uplink delay of the radio unit.

600 600 602 120 402 400 6 FIG. With further reference to methodin, example operations that can be performed to achieve uplink time alignment in actual operation are described in further detail. Methodcan begin atwith synchronization of the clock generation logicand SFN pulse generation, which can be done in a similar manner to that described above atof method.

604 602 510 606 0 3 1 510 3 1 Next, at, the SFN pulse generated via the clock generation logic atcan be used to trigger the uplink buffer. At, the buffer can timestamp buffered uplink data (e.g., corresponding to a frame start S) with a delay parameter equal to Ta_partafter the SFN pulse arrives. This results in the uplink buffereffectively releasing buffered uplink data at a delay relative to the SFN pulse by a timing adjustment parameter that is equal to Ta_part.

600 608 3 1 608 310 10 10 In some implementations, methodcan conclude at, in which the delay parameter associated with the uplink data (e.g., Ta_part) is indicated to a distributed unit and/or other network equipment at. This can be performed by, e.g., the eCPRI/O-RAN interfaceof the radio unitand/or other suitable components operating as delay notification logic for the radio unit.

500 3 2 510 510 520 10 510 3 1 510 3 2 In model, the delay Ta_partfollowing the uplink bufferdoes not contribute to the end-to-end TAE since the frame start time is established in the uplink bufferand the FFT logic. As a result, the total delay of the radio unitfrom the perspective of the uplink buffercan be equivalent to Ta_part, which can be a constant value due to data entering the uplink bufferbeing time domain data, removing the uncertainty in Ta_partassociated with converting said time domain data to the frequency domain.

10 600 10 11 FIG. In an implementation in which the radio unitincludes multiple antennas, similar procedures to those described with respect to methodcan be applied, thereby achieving time alignment among multiple antennas. An example of an uplink signal path for a radio unitwith multiple antennas is described below with respect to.

7 FIG. 7 FIG. 700 700 710 Referring now to, a block diagram of a systemthat facilitates radio unit delay characterization in accordance with various implementations described herein is illustrated. Repetitive description of like parts described above with regard to other implementations is omitted for brevity. Systemas shown inincludes a DU emulator, which can be composed of appropriate hardware and/or software elements to mimic various operations performed by distributed equipment.

710 10 712 10 700 320 510 10 720 730 720 730 714 10 3 FIG. 5 FIG. 3 FIG. 5 FIG. 7 FIG. The DU emulatoris connected to a radio unitvia a fronthaul (FH) interface. The radio unitshown in systemincludes an FDV bufferand an uplink buffer, which can operate as described above with respect toand, respectively. The radio unitalso includes a downlink pathand an uplink path, which can operate in a similar manner to the blocks described above with respect toand, respectively, and are illustrated inas single blocks for simplicity. The DL pathand uplink pathare communicatively coupled to an antennaof the radio unit.

7 FIG. 740 714 10 750 760 10 740 714 10 750 740 760 714 120 10 320 510 760 770 710 750 760 700 As further shown in, an RF switchselectively couples the antennaof the radio unitto a scopeand/or a signal generatorbased on whether the radio unitis operating in the uplink or downlink. For instance, the RF switchin downlink mode can connect the antennaof the radio unitto the scope, and in uplink mode the RF switchcan connect the signal generatorto the antenna. Clock generation logicof the radio unitcan provide a SFN pulse to the buffers,and the signal generator, e.g., as generally described above. Additionally, a splitteris connected to the DU emulator, scope, and signal generatorto facilitate provisioning of signals within system.

710 750 760 710 750 760 770 710 120 The DU emulatorcan provide a reference signal corresponding to a carrier frequency, e.g., a 10 MHz reference signal or another suitable frequency, which can be aligned to the scopeand the signal generatorin time. Additionally, the DU emulatorcan generate a 10 ms trigger signal, which can function as a SFN pulse that is supplied to the scopeand signal generatorvia the splitterto facilitate switching between uplink and downlink operation. It is noted that the SFN pulse generated via the DU emulatorand the SFN pulse generated by the clock generation logiccan be independently generated.

7 FIG. 740 750 760 770 10 In the implementation shown in, the RF switch, scope, signal generator, and/or splittercan be external equipment, i.e., equipment that is not part of the radio unit. Any associated delays associated with these external components and/or connections therebetween (e.g., via cables or the like) can be calibrated and subtracted from the final overall delay.

700 10 2 2 3 1 10 10 10 10 10 a 7 FIG. In some implementations, systemcan be utilized in the development process of the radio unitto determine the timing parameters (e.g., T_partand Ta_part) associated with the radio unit. Once these timing parameters are determined, they can be stored in a database or other data store of the radio unit(not shown in) and used by software associated with the radio unit. As these parameters do not change during operation of the radio unitfor a given carrier bandwidth, they can be stored and utilized at the radio unitonce determined.

8 9 FIGS.- 7 FIG. 7 FIG. 8 9 FIGS.- 12 FIG. 800 900 700 800 900 10 800 900 10 Turning to, and with further reference to, respective methods,that can be performed by systemare illustrated. In an implementation, the operations described in methodsandcan be performed via software, e.g., by a processor executing instructions stored on a memory which, when executed by the processor, cause the processor to perform the listed operations. A processor and memory used in this manner can be associated with the radio unititself, or alternatively an external orchestration device (not shown in) could be used. An example of a computer architecture that can be utilized to facilitate the operations shown inis described in further detail below with respect to. It is noted that methodsandare automated in this manner due to the amount and frequency of associated data (e.g., on the order of millions of data points per second), as well as the operations to be performed on said data not being capable of being performed by a human with the precision necessary for proper operation of the radio unit(e.g., on the order of nanosecond-level precision) in a useful or reasonable timeframe.

8 FIG. 800 700 802 10 710 712 10 0 710 10 710 802 710 10 Referring first to, an example methodfor downlink operation of systembegins at, in which a downlink test signal, also referred to as a test vector, can be transmitted to the radio unit(e.g., from the DU emulator) via the fronthaul interfaceof the radio unit. For instance, a test pattern with a defined frame start boundary Scan be created and loaded into the DU emulatorfor transmittal to the radio unit. Unlike typical distributed unit operation in which data is provided to the radio unit with an advance, a transmission advance of the DU emulatoratcan be set to zero in order to remove the impact of an advance applied by the DU emulatoron the resulting delay of the radio unit.

804 10 710 802 10 320 806 714 10 720 120 10 Next, at, the radio unitis activated, and the downlink test signal transmitted by the DU emulatoratcan be buffered by the radio unit, e.g., via the FDV buffer, resulting in buffered data. At, the buffered data is released to the antennaof the radio unit, e.g., via the downlink path, in response to an SFN pulse generated by the clock generation logicbeing observed at the radio unit.

320 806 714 750 808 750 10 120 710 0 714 10 2 2 808 0 750 a Data released by the FDV bufferatcan then be conveyed via the antennato the scopeat, where the data is captured by the scopeand a downlink time delay associated with the radio unitcan be computed as a difference between a first time, corresponding to the time of the SFN pulse associated with the clock generation logicand/or the trigger signal produced by the DU emulator, and a second time, corresponding to the frame start boundary Sof the test signal being observed at the antennaof the radio unit. Stated another way, the downlink delay of the radio unit, e.g., T_part, can be determined atas the delay from the SFN pulse to the frame start Sas observed via the scope.

9 FIG. 900 700 902 0 760 10 714 900 800 Turning next to, an example methodfor downlink operation of systembegins at, in which an uplink test signal (e.g., a test vector) with a known frame start boundary Scan be loaded into the signal generator, from which the uplink test signal can be transmitted from the signal generator to the radio unitvia the antenna. In some implementations, the uplink test signal used by methodcan be the same signal, or a similar signal, to the downlink test signal used by methodas described above.

904 10 902 10 510 906 760 904 Next, at, the radio unitis activated, and the uplink test signal transmitted atcan be buffered by the radio unit, e.g., via the uplink buffer, resulting in buffered data. At, the uplink test signal provided via the signal generatorcan be converted to a baseband input signal, e.g., either in parallel with or in response to the buffering performed at.

908 900 10 906 904 908 At, methodcan conclude by determining an uplink time delay associated with the radio unitbased on a result of cross correlating the baseband input signal generated atwith the buffered data produced at. By way of example, one or more digital signal processing techniques can be utilized atto determine a sliding distance (e.g., from the buffered data to the baseband input signal) that results in at least a threshold amount of correlation between the baseband input signal and the buffered data.

800 900 700 10 800 900 While both methodand methodillustrate operations that can be performed by systemto determine radio unit delay parameters for a single carrier frequency (e.g., 10 MHZ), similar operations could be performed to determine delay parameters for the radio unitat different carrier frequencies. For instance, each of the operations shown in method(for downlink delay) and/or method(for uplink delay) could be repeated for additional test signals that are associated with different carrier bandwidths, e.g., a second test signal associated with a second carrier frequency (e.g., 20 MHz), a third test signal associated with a third carrier frequency (e.g., 40 MHZ), etc., resulting in additional time delay parameters associated with those additional carrier bandwidths.

700 800 900 10 10 10 10 10 712 714 As noted above, operation of system, e.g., as described above with respect to methodsand, can be performed during a development stage for the radio unit. Upon determining the timing parameters associated with the radio unitas described above, those parameters can be stored at the radio unit, e.g., in a database or other data store associated with the radio unit, and/or otherwise stored at a location accessible by the radio unit, e.g., a remote device that is communicatively coupled to the radio unitvia the fronthaul interfaceand/or antenna.

10 10 In some implementations, the accuracy of the timing parameters associated with the radio unitcan be verified during a conformance test, e.g., a 3GPP TAE test, an end-to-end data throughput test, and/or other suitable tests. During this stage, tuning can be performed to improve throughput and facilitate conformity to 3GPP TAE specifications. Once finalized, however, the timing parameters of the radio unitcan be expected to remain substantially constant during deployment in the field.

10 FIG. 10 FIG. 3 FIG. 1000 10 360 360 1000 300 360 360 360 360 a n a n a n Referring next to, a block diagram of a downlink timing modelthat can be utilized by a radio unitwith multiple antenna ports-in accordance with various implementations described herein is illustrated. Repetitive description of like parts described above with regard to other implementations is omitted for brevity. Modelshown inis similar to modeldescribed above with respect to, with the addition of multiple antenna ports-. It is noted that the naming convention utilized for the antenna ports-is merely for purposes of illustration and is not intended to imply a specific number of antenna ports.

3 FIG. 7 8 FIGS.- 320 2 2 360 360 10 360 360 360 360 360 360 a a n a n a n a n. As noted above with respect to, the FDV buffercan be designed such that it is triggered by an SFN pulse and reads out data in advance of the SFN. This advance amount can be equivalent to T_part, which can be characterized as described above with respect to. Use of this advance can ensure that downlink data arrives at the antenna ports-when the SFN pulse arrives at the radio unit. The same procedures can be applied to each of the antenna ports-, which can ensure that downlink data at all antenna ports-is synchronized and meets 3GPP TAE requirements. In this manner, fronthaul delay does not contribute to the TAE for any of the antenna ports-

11 FIG. 11 FIG. 5 FIG. 10 360 360 1000 1100 500 360 360 a n a n. Turning to, a block diagram of an uplink timing model that can be utilized by a radio unitwith multiple antenna ports-in accordance with various implementations described herein is illustrated. Repetitive description of like parts described above with regard to other implementations is omitted for brevity. Similar to model, modelshown inis similar to modelabove with respect towith the addition of multiple antenna ports-

11 FIG. 7 9 FIGS.and 120 510 510 0 3 1 360 360 360 360 360 360 a n a n a n. For uplink operation as shown in, the same SFN pulse from the clock generation logiccan be used to trigger the uplink buffer. The buffercan then read out uplink data (e.g., corresponding to a frame start S) with a delay equal to Ta_part(e.g., as characterized as described above with respect to) after the SFN pulse arrives. The same procedures can be applied to each of the antenna ports-, which can ensure that uplink data to the distributed unit from all antenna ports-is synchronized and meets 3GPP TAE requirements. In this manner, fronthaul delay does not contribute to the TAE for any of the antenna ports-

4 6 8 9 FIGS.,,, and as described above illustrate methods in accordance with certain embodiments of this disclosure. While, for purposes of simplicity of explanation, the methods have been shown and described as series of acts, it is to be understood and appreciated that this disclosure is not limited by the order of acts, as some acts may occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that methods can alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement methods in accordance with certain embodiments of this disclosure.

12 FIG. 1200 In order to provide additional context for various embodiments described herein,and the following discussion are intended to provide a brief, general description of a suitable computing environmentin which the various embodiments of the embodiment described herein can be implemented. While the embodiments have been described above in the general context of computer-executable instructions that can run on one or more computers, those skilled in the art will recognize that the embodiments can be also implemented in combination with other program modules and/or as a combination of hardware and software.

Generally, program modules include routines, programs, components, data structures, etc., that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the various methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, Internet of Things (IoT) devices, distributed computing systems, as well as personal computers, hand-held computing devices, microprocessor-based or programmable consumer electronics, and the like, each of which can be operatively coupled to one or more associated devices.

The illustrated embodiments of the embodiments herein can be also practiced in distributed computing environments where certain tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

Computing devices typically include a variety of media, which can include computer-readable storage media, machine-readable storage media, and/or communications media, which two terms are used herein differently from one another as follows. Computer-readable storage media or machine-readable storage media can be any available storage media that can be accessed by the computer and includes both volatile and nonvolatile media, removable and non-removable media. By way of example, and not limitation, computer-readable storage media or machine-readable storage media can be implemented in connection with any method or technology for storage of information such as computer-readable or machine-readable instructions, program modules, structured data or unstructured data.

Computer-readable storage media can include, but are not limited to, random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray disc (BD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state drives or other solid state storage devices, or other tangible and/or non-transitory media which can be used to store desired information. In this regard, the terms “tangible” or “non-transitory” herein as applied to storage, memory or computer-readable media, are to be understood to exclude only propagating transitory signals per se as modifiers and do not relinquish rights to all standard storage, memory or computer-readable media that are not only propagating transitory signals per se.

Computer-readable storage media can be accessed by one or more local or remote computing devices, e.g., via access requests, queries or other data retrieval protocols, for a variety of operations with respect to the information stored by the medium.

Communications media typically embody computer-readable instructions, data structures, program modules or other structured or unstructured data in a data signal such as a modulated data signal, e.g., a carrier wave or other transport mechanism, and includes any information delivery or transport media. The term “modulated data signal” or signals refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in one or more signals. By way of example, and not limitation, communication media include wired media, such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

12 FIG. 1200 1202 1202 1204 1206 1208 1208 1206 1204 1204 1204 With reference again to, the example environmentfor implementing various embodiments described herein includes a computer, the computerincluding a processing unit, a system memoryand a system bus. The system buscouples system components including, but not limited to, the system memoryto the processing unit. The processing unitcan be any of various commercially available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit.

1208 1206 1210 1212 1202 1212 The system buscan be any of several types of bus structure that can further interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memoryincludes ROMand RAM. A basic input/output system (BIOS) can be stored in a non-volatile memory such as ROM, erasable programmable read only memory (EPROM), EEPROM, which BIOS contains the basic routines that help to transfer information between elements within the computer, such as during startup. The RAMcan also include a high-speed RAM such as static RAM for caching data.

1202 1214 1216 1220 1214 1202 1214 1200 1214 1214 1216 1220 1208 1224 1226 1228 1224 The computerfurther includes an internal hard disk drive (HDD)(e.g., EIDE, SATA), one or more external storage devices(e.g., a magnetic floppy disk drive (FDD), a memory stick or flash drive reader, a memory card reader, etc.) and an optical disk drive(e.g., which can read or write from a CD-ROM disc, a DVD, a BD, etc.). While the internal HDDis illustrated as located within the computer, the internal HDDcan also be configured for external use in a suitable chassis (not shown). Additionally, while not shown in environment, a solid state drive (SSD) could be used in addition to, or in place of, an HDD. The HDD, external storage device(s)and optical disk drivecan be connected to the system busby an HDD interface, an external storage interfaceand an optical drive interface, respectively. The interfacefor external drive implementations can include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies. Other external drive connection technologies are within contemplation of the embodiments described herein.

1202 The drives and their associated computer-readable storage media provide nonvolatile storage of data, data structures, computer-executable instructions, and so forth. For the computer, the drives and storage media accommodate the storage of any data in a suitable digital format. Although the description of computer-readable storage media above refers to respective types of storage devices, it should be appreciated by those skilled in the art that other types of storage media which are readable by a computer, whether presently existing or developed in the future, could also be used in the example operating environment, and further, that any such storage media can contain computer-executable instructions for performing the methods described herein.

1212 1230 1232 1234 1236 1212 A number of program modules can be stored in the drives and RAM, including an operating system, one or more application programs, other program modulesand program data. All or portions of the operating system, applications, modules, and/or data can also be cached in the RAM. The systems and methods described herein can be implemented utilizing various commercially available operating systems or combinations of operating systems.

1202 1230 1230 1202 1230 1232 1232 1230 1232 12 FIG. Computercan optionally comprise emulation technologies. For example, a hypervisor (not shown) or other intermediary can emulate a hardware environment for operating system, and the emulated hardware can optionally be different from the hardware illustrated in. In such an embodiment, operating systemcan comprise one virtual machine (VM) of multiple VMs hosted at computer. Furthermore, operating systemcan provide runtime environments, such as the Java runtime environment or the .NET framework, for applications. Runtime environments are consistent execution environments that allow applicationsto run on any operating system that includes the runtime environment. Similarly, operating systemcan support containers, and applicationscan be in the form of containers, which are lightweight, standalone, executable packages of software that include, e.g., code, runtime, system tools, system libraries and settings for an application.

1202 1202 Further, computercan be enable with a security module, such as a trusted processing module (TPM). For instance with a TPM, boot components hash next in time boot components, and wait for a match of results to secured values, before loading a next boot component. This process can take place at any layer in the code execution stack of computer, e.g., applied at the application execution level or at the operating system (OS) kernel level, thereby enabling security at any level of code execution.

1202 1238 1240 1242 1204 1244 1208 A user can enter commands and information into the computerthrough one or more wired/wireless input devices, e.g., a keyboard, a touch screen, and a pointing device, such as a mouse. Other input devices (not shown) can include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, a joystick, a virtual reality controller and/or virtual reality headset, a game pad, a stylus pen, an image input device, e.g., camera(s), a gesture sensor input device, a vision movement sensor input device, an emotion or facial detection device, a biometric input device, e.g., fingerprint or iris scanner, or the like. These and other input devices are often connected to the processing unitthrough an input device interfacethat can be coupled to the system bus, but can be connected by other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR interface, a BLUETOOTH® interface, etc.

1246 1208 1248 1246 A monitoror other type of display device can be also connected to the system busvia an interface, such as a video adapter. In addition to the monitor, a computer typically includes other peripheral output devices (not shown), such as speakers, printers, etc.

1202 1250 1250 1202 1252 1254 1256 The computercan operate in a networked environment using logical connections via wired and/or wireless communications to one or more remote computers, such as a remote computer(s). The remote computer(s)can be a workstation, a server computer, a router, a personal computer, portable computer, microprocessor-based entertainment appliance, a peer device or other common network node, and typically includes many or all of the elements described relative to the computer, although, for purposes of brevity, only a memory/storage deviceis illustrated. The logical connections depicted include wired/wireless connectivity to a local area network (LAN)and/or larger networks, e.g., a wide area network (WAN). Such LAN and WAN networking environments are commonplace in offices and companies, and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to a global communications network, e.g., the Internet.

1202 1254 1258 1258 1254 1258 When used in a LAN networking environment, the computercan be connected to the local networkthrough a wired and/or wireless communication network interface or adapter. The adaptercan facilitate wired or wireless communication to the LAN, which can also include a wireless access point (AP) disposed thereon for communicating with the adapterin a wireless mode.

1202 1260 1256 1256 1260 1208 1244 1202 1252 When used in a WAN networking environment, the computercan include a modemor can be connected to a communications server on the WANvia other means for establishing communications over the WAN, such as by way of the Internet. The modem, which can be internal or external and a wired or wireless device, can be connected to the system busvia the input device interface. In a networked environment, program modules depicted relative to the computeror portions thereof, can be stored in the remote memory/storage device. It will be appreciated that the network connections shown are example and other means of establishing a communications link between the computers can be used.

1202 1216 1202 1254 1256 1258 1260 1202 1226 1258 1260 1226 1202 When used in either a LAN or WAN networking environment, the computercan access cloud storage systems or other network-based storage systems in addition to, or in place of, external storage devicesas described above. Generally, a connection between the computerand a cloud storage system can be established over a LANor WANe.g., by the adapteror modem, respectively. Upon connecting the computerto an associated cloud storage system, the external storage interfacecan, with the aid of the adapterand/or modem, manage storage provided by the cloud storage system as it would other types of external storage. For instance, the external storage interfacecan be configured to provide access to cloud storage sources as if those sources were physically connected to the computer.

1202 The computercan be operable to communicate with any wireless devices or entities operatively disposed in wireless communication, e.g., a printer, scanner, desktop and/or portable computer, portable data assistant, communications satellite, any piece of equipment or location associated with a wirelessly detectable tag (e.g., a kiosk, news stand, store shelf, etc.), and telephone. This can include Wireless Fidelity (Wi-Fi) and BLUETOOTH® wireless technologies. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices.

The above description includes non-limiting examples of the various embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed subject matter, and one skilled in the art may recognize that further combinations and permutations of the various embodiments are possible. The disclosed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

With regard to the various functions performed by the above described components, devices, circuits, systems, etc., the terms (including a reference to a “means”) used to describe such components are intended to also include, unless otherwise indicated, any structure(s) which performs the specified function of the described component (e.g., a functional equivalent), even if not structurally equivalent to the disclosed structure. In addition, while a particular feature of the disclosed subject matter may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

The terms “exemplary” and/or “demonstrative” as used herein are intended to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any embodiment or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other embodiments or designs, nor is it meant to preclude equivalent structures and techniques known to one skilled in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive—in a manner similar to the term “comprising” as an open transition word—without precluding any additional or other elements.

The term “or” as used herein is intended to mean an inclusive “or” rather than an exclusive “or.” For example, the phrase “A or B” is intended to include instances of A, B, and both A and B. Additionally, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless either otherwise specified or clear from the context to be directed to a singular form.

The term “set” as employed herein excludes the empty set, i.e., the set with no elements therein. Thus, a “set” in the subject disclosure includes one or more elements or entities. Likewise, the term “group” as utilized herein refers to a collection of one or more entities.

The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is for clarity only and doesn't otherwise indicate or imply any order in time. For instance, “a first determination,” “a second determination,” and “a third determination,” does not indicate or imply that the first determination is to be made before the second determination, or vice versa, etc.

The description of illustrated embodiments of the subject disclosure as provided herein, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as one skilled in the art can recognize. In this regard, while the subject matter has been described herein in connection with various embodiments and corresponding drawings, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.