Electronic devices comprising pillars extending through a semiconductor material and adjacent to a source implant region, and related electronic systems and methods

The subject matter of this application is related to the subject matter of U.S. patent application Ser. No. 17/813,818, titled “ELECTRONIC DEVICES COMPRISING AN OXIDE FILL REGION, AND RELATED ELECTRONIC SYSTEMS AND METHODS,” and U.S. patent application Ser. No. 17/813,847, titled “ELECTRONIC DEVICES INCLUDING AN IMPLANT STRUCTURE, AND RELATED SYSTEMS AND METHODS,” each of which was filed on Jul. 20, 2022, the same date as this application.

Embodiments of the disclosure relate to the field of electronic device design and fabrication. More particularly, the disclosure relates to electronic devices having a source implant region in a source stack, and to related electronic systems and methods for forming the electronic devices.

Memory devices provide data storage for electronic systems. A Flash memory device is one of various memory device types and has numerous uses in modern computers and other electrical devices. A conventional Flash memory device may include a memory array that has a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In a NAND architecture type of Flash memory, memory cells arranged in a column are coupled in series, and a first memory cell of the column is coupled to a data line (e.g., a bit line). In a three-dimensional (3D) NAND memory device, not only are the memory cells arranged in rows and columns in a horizontal array, but tiers of the horizontal arrays are stacked over one another (e.g., as vertical strings of memory cells) to provide a 3D array of the memory cells. The stack of tiers vertically alternate conductive materials with dielectric materials, with the conductive materials functioning as access lines (e.g., word lines) and gate structures (e.g., control gates) for the memory cells. Pillars comprising channels and tunneling structures extend along and form portions of the memory cells of individual vertical strings of memory cells. A drain end of a string is adjacent one of the top or bottom of the pillar, while a source end of the string is adjacent the other of the top or bottom of the pillar. The drain end is operably connected to a bit line, and the source end is operably connected to a source line. A 3D NAND memory device also includes electrical connections between, e.g., access lines (e.g., word lines) and other conductive structures of the device so that the memory cells of the vertical strings can be selected for writing, reading, and erasing operations.

In conventional 3D NAND memory devices, the pillars including the channels are formed through multiple polysilicon materials, and contact between the channels and other electrically conductive components of the memory devices is achieved by a laterally-oriented, doped polysilicon material. However, etching the multiple polysilicon materials may cause processing challenges, such as over-etching, since multiple polysilicon materials are present. The over-etching may, for example, lead to corrosion of conductive materials of the source stack.

Electronic devices (e.g., apparatus, microelectronic devices) and systems (e.g., electronic systems) according to embodiments of the disclosure include a source implant region below a slit that is used to form a lateral contact (e.g., a source contact) to a channel of pillars of the electronic devices. The source implant region provides additional process margin for etching materials of the electronic device and into a source contact region while protecting a source stack below the source contact region. By including the source implant region in a source stack of the electronic device, etching into and through the source contact is controllable. The source implant region protects underlying conductive materials of the source stack, and improves sidewall etching into the source contact region. By appropriately selecting a material of the source implant region, polysilicon materials of the electronic device may be selectively removed without exposing portions of the source stack beneath the source implant region to the removal condition. By protecting the source stack, corrosion of conductive materials of the source stack is reduced or eliminated.

Fabrication of the electronic device includes forming and removing multiple sacrificial structures during the formation of the source contact. A source contact sacrificial structure is used to form the source contact in a desired location and a slit is formed through the source contact sacrificial structure to expose the source implant region. A material selected for the source implant region may be substantially similar to the material of an upper surface of the surface stack, with implantation to provide etch selectivity. A dimension (e.g., a width) of the source implant region in a lateral direction is equal to or wider than the width of a lower portion of the slit. Therefore, portions of a source contact material may be laterally etched without etching portions of the source stack underlying the source implant region. In contrast to conventional electronic devices, the electronic devices according to embodiments of the disclosure include the source implant region in an upper portion of the source stack and below a fill material subsequently formed in the slit.

The following description provides specific details, such as material types, material thicknesses, and process conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of an electronic device or a complete process flow for manufacturing the electronic device and the structures described below do not form a complete electronic device. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete electronic device may be performed by conventional techniques.

The fabrication processes described herein do not form a complete process flow for processing apparatus (e.g., devices, systems) or the structures thereof. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and structures necessary to understand embodiments of the present apparatus (e.g., devices, systems) and methods are described herein.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), epitaxial growth, or ion implanting (e.g., plasma doping ion implantation). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art unless the context indicates otherwise. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, electronic device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/of” includes any and all combinations of one or more of the associated listed items.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the terms “comprising,” “including,” “containing,” “characterized by,” and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps, but also include the more restrictive terms “consisting of” and “consisting essentially of” and grammatical equivalents thereof.

y x x y x y x z z As used herein, the term “conductive material” means and includes an electrically conductive material. The conductive material may include, but is not limited to, one or more of a doped polysilicon, undoped polysilicon, a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. By way of example only, the conductive material may be one or more of tungsten (W), tungsten nitride (WNy), nickel (Ni), tantalum (Ta), tantalum nitride (TaNy), tantalum silicide (TaSix), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium (Ir), iridium oxide (IrO), ruthenium (Ru), ruthenium oxide (RuO), n-doped polysilicon, p-doped polysilicon, undoped polysilicon, and conductively doped silicon, where x, y, or z are integers or non-integers.

As used herein, the term “configured” refers to a size, shape, material composition, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operably connected with each other, such as electrically connected through a direct ohmic connection or through an indirect connection (e.g., via another structure).

x 2 x x x x x x x x x y x z y x y x z y As used herein, the term “dielectric material” means and includes an electrically insulative material. The dielectric material may include, but is not limited to, one or more of an insulative oxide material, an insulative nitride material, an insulative oxynitride material, an insulative carboxynitride material, and/or air. A dielectric oxide material may be an oxide material, a metal oxide material, or a combination thereof. The dielectric oxide material may include, but is not limited to, a silicon oxide (SiO, silicon dioxide (SiO)), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), aluminum oxide (AlO), barium oxide, gadolinium oxide (GdO), hafnium oxide (HfO), magnesium oxide (MgO), molybdenum oxide, niobium oxide (NbO), strontium oxide, tantalum oxide (TaO), titanium oxide (TiO), yttrium oxide, zirconium oxide (ZrO), hafnium silicate, a dielectric oxynitride material (e.g., SiON), a dielectric carbon nitride material (SiCN), a dielectric carboxynitride material (e.g., SiOCN), a combination thereof, or a combination of one or more of the listed materials with silicon oxide, where values of “x,” “y,” and “z” may be integers or may be non-integers. A dielectric nitride material may include, but is not limited to, silicon nitride. A dielectric oxynitride material may include, but is not limited to, a silicon oxynitride (SiON). A dielectric carboxynitride material may include, but is not limited to, a silicon carboxynitride (SiOCN). The dielectric material may be a stoichiometric compound or a non-stoichiometric compound.

As used herein, the term “electronic device” includes, without limitation, a memory device, as well as semiconductor devices which may or may not incorporate memory, such as a logic device, a processor device, or a radiofrequency (RF) device. Further, an electronic device may incorporate memory in addition to other functions such as, for example, a so-called “system on a chip” (SoC) including a processor and memory, or an electronic device including logic and memory. The electronic device may, for example, be a 3D electronic device, such as a 3D NAND Flash memory device.

x 2 As used herein, the term “high-k dielectric material” means and includes a dielectric oxide material having a dielectric constant greater than the dielectric constant of silicon oxide (SiO), such as silicon dioxide (SiO). The dielectric constant of silicon dioxide is from about 3.7 to about 3.9. The high-k dielectric material may include, but is not limited to, a high-k oxide material, a high-k metal oxide material, or a combination thereof. By way of example only, the high-k dielectric material may be aluminum oxide, gadolinium oxide, hafnium oxide, niobium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium silicate, a combination thereof, or a combination of one or more of the listed high-k dielectric materials with silicon oxide. The term “high-k dielectric material” is a relative term and is distinguished from the term “dielectric material” by a relative value of its dielectric constant. Materials listed above as examples of a “dielectric material” may overlap with some of the materials listed above as examples of a “high-k dielectric material” since the terms are relative.

As used herein, the term “may” with respect to a material, structure, feature or method act indicates that such is contemplated for use in implementation of an embodiment of the disclosure and such term is used in preference to the more restrictive term “is” so as to avoid any implication that other, compatible materials, structures, features and methods usable in combination therewith should or must be excluded.

As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intervening elements are present.

As used herein, the terms “opening” and “slit” mean and include a volume extending through at least one structure or at least one material, leaving a void (e.g., gap) in the at least one structure or at least one material, or a volume extending between structures or materials, leaving a gap between the structures or materials. Unless otherwise described, the opening and/or slit is not necessarily empty of material. That is, an opening and/or slit is not necessarily void space. An opening and/or slit formed in or between structures or materials may comprise structure(s) or material(s) other than that in or between which the opening and/or slit is formed. And, structure(s) or material(s) “exposed” within an opening and/or slit is (are) not necessarily in contact with an atmosphere or non-solid environment. Structure(s) or material(s) exposed within an opening and/or slit may be adjacent or in contact with other structure(s) or material(s) that is (are) disposed within the opening and/or slit.

As used herein, the term “sacrificial,” when used in reference to a material or a structure, means and includes a material or structure that is formed during a fabrication process but at least a portion of which is removed (e.g., substantially removed) prior to completion of the fabrication process. The sacrificial material or sacrificial structure may be present in some portions of the electronic device and absent in other portions of the electronic device.

As used herein, the terms “selectively removable” or “selectively etchable” mean and include a material that exhibits a greater etch rate responsive to exposure to a given etch chemistry and/or process conditions (collectively referred to as etch conditions) relative to another material exposed to the same etch chemistry and/or process conditions. For example, the material may exhibit an etch rate that is at least about five times greater than the etch rate of another material, such as an etch rate of about ten times greater, about twenty times greater, or about forty times greater than the etch rate of the another material. Etch chemistries and process conditions for selectively removing (e.g., selectively etching) a desired material may be selected by a person of ordinary skill in the art.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even at least 99.9% met.

As used herein, the term “substrate” means and includes a material (e.g., a base material) or construction upon which additional materials or components, such as those within memory cells, are formed. The substrate may be an electronic substrate, a semiconductor substrate, a base semiconductor layer on a supporting structure, an electrode, an electronic substrate having one or more materials, layers, structures, or regions formed thereon, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the electronic substrate or semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped. Furthermore, when reference is made to a “substrate” or “base material” in the following description, previous process acts may have been conducted to form materials or structures in or on the substrate or base material.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by Earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

100 1 1 2 2 102 104 106 104 108 106 104 106 108 104 106 108 104 106 108 104 106 108 16 17 FIGS.and 1 17 FIGS.through 1 FIG. 2 FIG. 2 FIG. 1 FIG. 1 FIG. x A method of forming an electronic device() according to embodiments of the disclosure is shown in.is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. As shown in, a source stackis formed adjacent to a base material (not shown) and includes one or more conductive materials, with a conductive liner materialformed adjacent to the base material, a source materialformed adjacent to the conductive liner material, and a first doped semiconductive materialformed adjacent to the source material. In some embodiments, the conductive liner materialis formed of and includes titanium nitride, the source materialis formed of and includes tungsten silicide (WSi), and the first doped semiconductive materialis formed of and includes a doped polysilicon material. However, the conductive liner material, the source material, and the first doped semiconductive materialmay be formed of and include other conductive materials. Each of the conductive liner material, source material, and first doped semiconductive materialmay be formed by conventional techniques and to a desired thickness. By way of example only, the conductive liner materialmay be formed to a thickness of from about 200 Å to about 400 Å, the source materialmay be formed to a thickness of from about 800 Å to about 1000 Å, and the first doped semiconductive materialmay be formed to a thickness of from about 2000 Å to about 4000 Å.

112 102 108 112 108 108 112 112 108 100 112 112 108 112 108 108 112 108 112 A source implant regionis present within the source stack, such as within an upper portion of the first doped semiconductive material. To form the source implant region, the first doped semiconductive materialmay be patterned using a patterned hardmask (not shown) formed adjacent to the upper portion of the first doped semiconductive material. The patterned hardmask may be used to form the source implant regionat a desired location and at desired dimensions. The source implant regionmay exhibit an etch rate that is substantially different than (e.g., substantially less than) the etch rate of the first doped semiconductive materialand exposed polysilicon materials in the electronic devicewhen exposed to the same etch conditions. The source implant regionmay, for example, be resistant to a tetramethylammonium hydroxide (TMAH)-based chemistry or other etch chemistry formulated to selectively remove polysilicon. By way of non-limiting example, the source implant regionmay be formed by implanting a dopant into the first doped semiconductive material. The dopant may provide etch selectivity to the source implant regionrelative to the first doped semiconductive materialand other materials exposed to the same etch conditions. By way of example only, the first doped semiconductive materialmay be implanted with boron, carbon, oxygen, gallium, or a combination thereof to form the source implant region. The implant conditions and the dopant concentration may be tailored to achieve the desired etch selectivity of the first doped semiconductive materialand other exposed materials relative to the source implant region.

108 112 108 112 The dopant implant conditions and the patterned hardmask are used to control the distribution of the dopant in the first doped semiconductive material, forming the source implant region. The dopant may be implanted to a desired depth into the first doped semiconductive material, such as to a depth of from about 1 nm to about 10 nm, such as about 5 nm. The lateral dimension (e.g., the width) of the source implant regionmay range from about 150 nm to about 300 nm.

148 102 148 150 152 154 150 152 154 100 150 154 150 152 154 150 152 154 148 1 FIG. A source contact sacrificial structureis formed over the source stack, as shown in. The source contact sacrificial structuremay include a first sacrificial material, a second sacrificial material, and a third sacrificial material, each of which is formed by conventional techniques. Materials of the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be selectively etchable relative to one another and relative to other materials of the electronic device. However, the first sacrificial materialand the third sacrificial materialmay be the same material (e.g., the same chemical composition) or may be a different material (e.g., a different chemical composition). By way of example only, the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be dielectric materials, such as a silicon oxide material or a silicon nitride material, that are selectively etchable. In some embodiments, the first sacrificial materialis a highly conformal silicon dioxide, the second sacrificial materialis silicon nitride, and the third sacrificial materialis tetraethylorthosilicate (TEOS). However, other combinations of dielectric materials may be used. In addition, the source contact sacrificial structuremay be formed of and include two materials or more than three materials.

148 120 130 120 130 148 120 148 120 150 152 154 120 150 152 154 150 152 154 130 102 130 16 17 FIGS.and Removal of the source contact sacrificial structureprovides lateral access for the subsequently-formed source contact(see) to contact the pillars, electrically coupling the source contactto the pillars. The location of the source contact sacrificial structurecorresponds to the location at which the source contactis ultimately formed, and a total thickness of the as-formed source contact sacrificial structuremay be determined by a desired thickness of the source contact. Individual thicknesses of each of the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be selected based on the desired thickness of the source contact. By way of example only, the first sacrificial materialmay be formed to a thickness of from about 30 Å to about 400 Å, the second sacrificial materialmay be formed to a thickness of from about 100 Å to about 300 Å, and the third sacrificial materialmay be formed to a thickness of from about 30 Å to about 200 Å. The thickness of each of the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be sufficient to protect cell film materials of the pillarsand the source stackduring subsequently conducted process acts that provide access to the pillarsby sequentially removing portions of the cell films.

122 148 122 122 A second doped semiconductive materialis formed adjacent to the source contact sacrificial structureand may be formed by conventional techniques. The second doped semiconductive materialmay be a dielectric material that is resistant to etch conditions (e.g., etch chemistries and process conditions) used during subsequent process acts, such as to etch conditions used to remove polysilicon-based materials. By way of example only, the second doped semiconductive materialmay be resistant to phosphoric acid-based etch chemistries, to TMAH, to ammonium hydroxide, to hydrogen fluoride (HF), or to other halogen-based etch chemistries.

122 122 122 122 122 120 140 x x x x x x x x x x x The second doped semiconductive materialmay be a doped silicon nitride material or a doped silicon oxide (e.g., silicon dioxide) material. By way of example only, the second doped semiconductive materialmay be a carbon-doped semiconductive material, such as a carbon-doped silicon nitride material, a carbon-doped silicon material, or a carbon-doped silicon oxynitride material. In some embodiments, the second doped semiconductive materialis carbon-doped silicon. Alternatively, the second doped semiconductive materialmay be a boron-doped semiconductive material, such as a boron-doped silicon nitride material, a boron-doped silicon material, or a boron-doped silicon oxynitride material. The dopant in the semiconductive material may be present at a concentration sufficient to provide the desired etch selectivity without providing conductivity to the semiconductive material. The dopant concentration may be tailored to achieve the desired etch selectivity of the second doped semiconductive material. The dopant may be present in the semiconductive material at a concentration of from about 1% by weight to about 12% by weight. While embodiments herein describe the semiconductive material between the source contactand the tier stack′ as being a doped semiconductive material, a high-k dielectric material that exhibits the desired etch selectivity may, alternatively, be used. The high-k dielectric material may include, but is not limited to, hafnium oxide (HfO), aluminum oxide (AlO), antimony oxide (SbO), cerium oxide (CeO), gallium oxide (GaO), lanthanum oxide (LaO), niobium oxide (NbO), titanium oxide (TiO), zirconium oxide (ZrO), tantalum oxide (TaO), magnesium oxide (MgO), or a combination thereof.

160 122 164 166 126 160 122 164 160 164 160 160 122 154 148 160 112 160 112 160 170 160 160 1 2 FIGS.and 1 FIG. 4 FIG. A slit sacrificial structureis formed in the second doped semiconductive material, as shown in. Tiersof alternating nitride materialsand dielectric materialsare formed adjacent to (e.g., on) the slit sacrificial structureand the second doped semiconductive material, as shown in. The tiersmay be formed by conventional techniques. The slit sacrificial structuremay be formed of and include one or more materials that are selective etchable relative to the materials of tiers. The slit sacrificial structuremay also function as an etch stop during subsequent process acts. The slit sacrificial structuremay extend through the second doped semiconductive materialand, optionally, partially into the third sacrificial materialof the source contact sacrificial structure. The slit sacrificial structureis formed vertically above the source implant region. Additionally, the slit sacrificial structureis formed with a lateral width configured to be less than the lateral width of the source implant region. A location of the slit sacrificial structurecorresponds to a location adjacent to which (e.g., over which) a slit(see) is subsequently formed. The slit sacrificial structuremay, for example, include a dielectric material, a liner, and a etch stop material. By way of example only, the dielectric material may be a silicon oxide material, the liner may be a titanium nitride material, and the etch stop material may be tungsten or a tungsten-containing material. The etch stop material may be configured as a plug. Alternatively, the slit sacrificial structuremay be formed of a single material, such as aluminum oxide, two materials, or more than three materials as long as the material(s) provide the desired etch selectivity and etch stop functions.

164 108 164 122 148 108 164 122 148 108 130 140 138 136 134 132 132 140 138 136 134 132 130 130 160 130 1 FIG. 2 FIG. A pillar opening is formed through the tiersand at least partially into the first doped semiconductive material, exposing surfaces of the tiers, the second doped semiconductive material, the source contact sacrificial structure, and the first doped semiconductive material. The pillar opening may be formed by conventional techniques, such as by conventional photolithography and removal processes. The portions of the tiers, the second doped semiconductive material, the source contact sacrificial structure, and the first doped semiconductive materialmay be removed by one or more conventional etch processes, such as a conventional dry etch process. Cell films of the pillarsare formed in the pillar opening, as shown in. The charge blocking material, the charge trap material, the tunnel dielectric material, and the channelmay be conformally formed in the pillar opening by conventional techniques. The first fill materialmay be formed in a remaining volume of the pillar opening by conventional techniques. One or more voids may be present in the interior of the first fill material. The charge blocking material, the charge trap material, the tunnel dielectric material, the channel, and the first fill materialare positioned in order from the outermost material to the innermost material relative to an axial centerline of the pillar. As shown in, pillarsare positioned between adjacent slit sacrificial structures. By way of example only, the pillarsmay be arranged in columns of staggered rows and laterally spaced from one another.

140 140 140 The charge blocking materialmay be formed of and include a dielectric material. By way of example only, the charge blocking materialmay be one or more of an oxide (e.g., silicon dioxide), a nitride (silicon nitride), and an oxynitride (silicon oxynitride), or another material. In some embodiments, the charge blocking materialis silicon dioxide.

138 138 138 The charge trap materialmay be formed of and include at least one memory material and/or one or more conductive materials. The charge trap materialmay be formed of and include one or more of silicon nitride, silicon oxynitride, polysilicon (doped polysilicon), a conductive material (e.g., tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof), a semiconductive material (e.g., polycrystalline or amorphous semiconductor material, including at least one elemental semiconductor element and/or including at least one compound semiconductor material, such as conductive nanoparticles (e.g., ruthenium nanoparticles) and/or metal dots). In some embodiments, the charge trap materialis silicon nitride.

136 136 The tunnel dielectric materialmay include one or more dielectric materials, such as one or more of a silicon nitride material or a silicon oxide material. In some embodiments, the tunnel dielectric materialis a so-called “ONO” structure that includes silicon dioxide, silicon nitride, and silicon dioxide.

134 134 134 132 The channelmay be formed of and include a semiconductive material, a non-silicon channel material, or other channel material. The material of the channel may include, but is not limited to, a polysilicon material (e.g., polycrystalline silicon), a III-V compound semiconductive material, a II-VI compound semiconductive material, an organic semiconductive material, GaAs, InP, GaP, GaN, an oxide semiconductive material, or a combination thereof. In some embodiments, the channelis polysilicon, such as a doped polysilicon. The channelmay be configured as a so-called doped hollow channel (DHC) or other configuration. The first fill materialmay be a dielectric material, such as silicon dioxide.

164 160 170 164 172 122 148 164 160 160 160 122 164 160 160 170 160 170 172 170 160 112 160 112 170 164 122 154 170 154 3 FIG. 3 FIG. A portion of the tiersand the slit sacrificial structureis removed, as shown in, to form a slitthrough the tiersand a lower openingin the second doped semiconductive material, exposing the source contact sacrificial structure. The tiersand the slit sacrificial structuremay be removed by one or more etch processes, such as by using conventional etch conditions. The slit sacrificial structuremay be substantially completely removed or at least the liner and the etch stop material of the slit sacrificial structureare removed, with a portion of the dielectric material, optionally, remaining adjacent to the second doped semiconductive material. If a single etch process is conducted, the tiersand the slit sacrificial structuremay be substantially removed by the single etch process. If more than one etch process is conducted, the etch stop material of the slit sacrificial structuremay function as an etch stop during the first etch process to form the slitand a second etch process may be conducted to remove the slit sacrificial structure. For convenience, the slitand the lower openingare collectively referred to hereinafter as the slit. The slit sacrificial structureis formed vertically above the source implant region. Additionally, the slit sacrificial structureis formed with a lateral width configured to be less than the lateral width of the source implant region. Whileillustrates the slitas extending through the tiersand the second doped semiconductive materialto an upper surface of the third sacrificial material, the slitmay extend partially into the third sacrificial material.

4 FIG. 5 FIG. 5 FIG. 4 FIG. 4 5 FIGS.and 4 4 5 5 174 164 160 154 170 174 170 174 174 174 174 170 176 154 148 174 154 170 is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. As shown in, a slit lineris formed on exposed surfaces of the tiers, the slit sacrificial structure, and the third sacrificial materialin the slit. The slit linermay be conformally formed by conventional techniques such that a portion (e.g., a volume) of the slitremains open (e.g., unoccupied). The slit linermay be formed of and include a dielectric material, a semiconductive material, or a conductive material. In some embodiments, the slit lineris undoped polysilicon. The slit linermay be formed to a thickness of from about 200 Å to about 400 Å. A portion of the slit lineris removed from a bottom surface of the slitto form a slit liner opening, exposing the third sacrificial materialof the source contact sacrificial structure, which is also removed. The slit linerand the third sacrificial materialat the bottom surface of the slitmay be removed by conventional techniques.

130 148 140 138 136 148 122 148 122 148 152 170 178 178 130 148 6 10 FIGS.- 6 FIG. To provide access to the pillars, the source contact sacrificial structureand portions of the cell films (charge blocking material, charge trap material, tunnel dielectric material) are sequentially removed, as shown in. The source contact sacrificial structureis removed while a majority of the second doped semiconductive materialremains intact (e.g., unetched) by selecting the etch conditions used to remove the source contact sacrificial structure. In other words, the second doped semiconductive materialis substantially resistant to the etch conditions used to remove the source contact sacrificial structure. The second sacrificial materialis removed through the slit, as shown in, and a first source contact openingformed. As described below, the size of the first source contact openingis sequentially increased (e.g., enlarged) to provide access to the pillarsfollowing the removal of the source contact sacrificial structure.

152 148 150 154 140 152 152 150 154 140 152 152 150 154 140 150 154 140 152 122 174 164 154 The second sacrificial materialof the source contact sacrificial structureis selectively removed without substantially removing the first and third sacrificial materials,or the charge blocking material. The second sacrificial materialmay be selectively etched by conventional techniques, such as by conventional etch conditions, which are selected depending on the chemical composition of the second sacrificial materialrelative to the chemical composition of other exposed materials. Since the first sacrificial material, the third sacrificial material, and the charge blocking materialmay be similar materials and exhibit slower etch rates than the etch rate of the second sacrificial material, the second sacrificial materialis substantially removed relative to the first sacrificial material, the third sacrificial material, and the charge blocking material. By way of example only, if the first sacrificial material, the third sacrificial material, and the charge blocking materialare silicon oxide materials and the second sacrificial materialis a silicon nitride material, an etch chemistry formulated to remove silicon nitride may be used, such as a phosphoric acid-based etch chemistry. The second doped semiconductive materialis not exposed to (e.g., is protected from) the etch conditions by the slit liner, the tiers, and the third sacrificial material.

7 FIG. 140 150 154 174 140 150 154 140 150 154 140 178 150 154 150 154 140 178 150 154 140 178 178 122 148 130 As shown in, an exposed portion of the charge blocking material, the first sacrificial material, and the third sacrificial materialare selectively removed without substantially removing the slit liner. The charge blocking material, the first sacrificial material, and the third sacrificial materialmay be selectively etched by conventional techniques, which are selected depending on the chemical composition of the charge blocking material, the first sacrificial material, and the third sacrificial materialrelative to the chemical composition of other exposed materials. By selecting the etch conditions, the charge blocking materialadjacent to the first source contact opening, the first sacrificial material, and the third sacrificial materialare removed. The first sacrificial materialand third sacrificial materialmay be substantially completely removed while the exposed portion of the charge blocking material, adjacent (e.g., laterally adjacent) to the first source contact opening, is removed. Removing the first sacrificial material, the third sacrificial material, and the portions of the charge blocking materialincreases the size of the first source contact opening, forming first source contact opening′. In some embodiments, the second doped semiconductive materialis carbon-doped silicon nitride and is selectively etchable relative to silicon dioxide of the source contact sacrificial structureand silicon dioxide of the pillars.

150 154 140 178 108 112 178 122 138 122 174 140 122 174 By way of example only, if the first sacrificial material, the third sacrificial material, and the charge blocking materialare silicon oxide materials, an etch chemistry formulated to selectively remove silicon oxide materials may be used, such as an HF-based etch chemistry. Forming the first source contact opening′ exposes a top surface of the first doped semiconductive materialand a top surface of the source implant region. Forming the first source contact opening′ also exposes a bottom horizontal surface of the second doped semiconductive materialand exposes a portion of the charge trap material. The bottom surface of the second doped semiconductive materialmay be substantially coplanar with a bottom surface of the slit liner, while a bottom horizontal surface of the charge blocking materialmay be recessed relative to (e.g., not coplanar with) the bottom surfaces of the second doped semiconductive materialand the slit liner.

184 178 178 184 108 112 122 174 138 140 184 184 A source contact opening lineris formed within the first source contact opening′ forming the first source contact opening″. The source contact opening linermay be formed along the top surfaces of the first doped semiconductive materialand the source implant region, along the bottom surfaces of the second doped semiconductive materialand the slit liner, and along the exposed portions of the charge trap materialand the charge blocking material. By way of example only, the source contact opening linermay be a dielectric material, such as a silicon oxide material or a silicon nitride material, that exhibits etch selectivity relative to other exposed materials. In some embodiments, the source contact opening lineris a highly conformal silicon dioxide.

138 174 184 138 184 178 138 136 138 184 138 138 178 9 FIG. The exposed portion of the charge trap materialis then selectively removed, as shown in, without substantially removing the slit lineror the source contact opening liner′ from vertical surfaces. The portion of the charge trap materialand portion of the source contact opening linerthat is laterally adjacent to the first source contact opening′″ is removed by selectively etching the charge trap material, which exposes a portion of the tunnel dielectric material. The charge trap materialand source contact opening linermay be removed by conventional techniques. By way of example only, if the charge trap materialis a silicon nitride material, an etch chemistry formulated to remove silicon nitride may be used, such as a phosphoric acid-based etch chemistry. By selecting the etch conditions, the charge trap materiallaterally adjacent to the first source contact opening′″ is removed.

10 FIG. 11 17 FIGS.- 136 184 178 178 136 178 136 122 136 134 136 136 178 136 134 120 As shown in, the exposed portion of the tunnel dielectric materialis selectively removed, along with the remaining portion of the source contact opening liner′, increasing the size of the first source contact opening′″ and forming first source contact opening″″. The portion of the tunnel dielectric materiallaterally adjacent to the first source contact opening″″ is removed by selectively etching the tunnel dielectric materialrelative to the second doped semiconductive material. Removing the tunnel dielectric materialalso exposes a portion of the channel. The exposed portion of the tunnel dielectric materialmay be removed by conventional techniques. By selecting the etch conditions, the tunnel dielectric materiallaterally adjacent to the first source contact opening″″ is removed. By way of example only, if the tunnel dielectric materialis an ONO material, the etch chemistry may include, but is not limited to, an HF-based etch chemistry. The exposed portion of the channelmay ultimately be in contact with the source contact(see).

122 102 124 100 150 152 154 148 150 152 154 134 130 178 120 178 120 148 120 148 16 FIG. 4 7 FIGS.- 16 FIG. 3 FIG. The second doped semiconductive materialmay function as an offset between the source stackand the tiersduring the fabrication of the electronic device(see). Since the first sacrificial material, the second sacrificial material, and the third sacrificial materialof the source contact sacrificial structureprovide protection to (e.g., masking of) various materials during the process acts indicated in, the initial thicknesses of the first sacrificial material, the second sacrificial material, and the third sacrificial materialare selected to be sufficiently thick to survive (e.g., withstand) the etch conditions used to provide lateral access to the channelof the pillars. The first source contact opening″″ exhibits a height Hi, which corresponds to a thickness of the source contactultimately formed in the first source contact opening″″. The thickness of the source contact(see) is greater than or equal to a combined thickness of the materials of the as-formed source contact sacrificial structure(see). By determining the desired thickness of the source contact, the thickness of the source contact sacrificial structuremay be selected.

150 152 154 148 100 100 170 148 100 148 108 122 100 120 122 102 100 100 148 122 102 16 FIG. 11 17 FIGS.- While the first sacrificial material, the second sacrificial material, and the third sacrificial materialhave been removed (e.g., are not present) in the perspective of, these materials of the source contact sacrificial structuremay be present in other portions (not shown) of the electronic device, such as in portions of the electronic devicedistal to the slit. The source contact sacrificial structuremay be present (e.g., visible), for example, in peripheral regions of the electronic device. In other words, the source contact sacrificial structuremay be positioned between the first doped semiconductive materialand the second doped semiconductive materialin the other portions of the electronic device. Therefore, although the source contactis present between the second doped semiconductive materialand the source stackof the electronic devicein the perspectives shown in, the other portions of the electronic devicewill include the source contact sacrificial structurebetween the second doped semiconductive materialand the source stack.

178 130 148 134 136 138 122 122 138 136 138 140 136 136 122 138 178 130 16 FIG. The first source contact opening″″ may provide access (e.g., lateral access) to the pillarsfollowing the substantially complete removal of the source contact sacrificial structure, which exposes the channel. Whileillustrates the exposed horizontal surfaces of the tunnel dielectric materialand the charge trap materialproximal to the second doped semiconductive materialas being substantially coplanar with each other and with the exposed horizontal surfaces of the second doped semiconductive material, the exposed horizontal surfaces of the charge trap materialmay, alternatively, be recessed relative to the exposed horizontal surfaces of the tunnel dielectric materialdepending on the etch conditions used. The exposed horizontal surfaces of the charge trap materialmay be recessed to a point intermediate that of the exposed horizontal surfaces of the charge blocking materialand the tunnel dielectric material. The exposed horizontal surfaces of the tunnel dielectric materialmay also be recessed relative to the exposed horizontal surfaces of the second doped semiconductive materialand of the charge trap material. Therefore, the size of the first source contact opening″″ may be further increased proximal to the pillars.

11 FIG. 12 FIG. 12 FIG. 11 FIG. 11 12 FIGS.and 11 11 12 12 120 120 178 120 178 178 170 120 120 120 122 108 130 120 120 + is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. As shown in, a conductive material′ of the source contactis formed within the first source contact opening″″. The conductive material′ may be conformally formed in the first source contact opening″″, substantially completely filling the first source contact opening″″ and filling a portion of the slit. In some embodiments, the conductive material′ is polysilicon, such as Ndoped polysilicon. The conductive material′ may be formed at a thickness of from about 500 Å to about 2000 Å, such as from about 700 Å to about 1500 Å, from about 700 Å to about 1800 Å, from about 800 Å to about 1500 Å, from about 800 Å to about 1800 Å, or from about 800 Å to about 1800 Å. The conductive material′ extends in a horizontal direction between the second doped semiconductive materialand the first doped semiconductive materialand contacts the pillars. An oxidation act may be conducted to activate dopants in the conductive material′ and so that the conductive material′ is substantially continuous and includes few holes, voids, or a seam.

13 FIG. 14 FIG. 14 FIG. 13 FIG. 13 14 FIGS.and 13 14 FIGS.and 13 FIG. 13 13 14 14 112 120 108 180 120 170 178 112 120 178 120 180 120 180 122 180 180 180 180 120 180 112 120 180 112 120 120 122 108 134 136 138 140 130 120 122 108 120 136 138 140 134 120 164 122 is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. Referring to, the etch selectivity of the source implant regionenables the conductive material′ to be removed laterally without removing the first doped semiconductive materialto form a second source contact opening. The conductive material′ is removed from the slitand from the portion of the first source contact opening″″ proximal to the source implant regionwhile the conductive material′ remains in the remaining first source contact opening″″, which forms the source contact. As shown in, the second source contact openingmay include an undercut region that extends in a lateral direction relative to the source contact. The second source contact openingmay also extend in a lateral direction below the second doped semiconductive material. A bottom portion of the second source contact opening, therefore, is wider than other portions of the second source contact opening. Whileillustrates that sidewalls defining the second source contact openingmay be curved, the sidewalls defining the second source contact openingmay, alternatively, be linear or substantially linear. An amount of the conductive material′ may be removed so that a width of the second source contact openingin the lateral direction is narrower than the width in the lateral direction of the source implant region. The amount of the conductive material′ may be removed so that the width of the second source contact openingin the lateral direction is substantially the same as, or wider than, the width in the lateral direction of the source implant region. The conductive material′ is removed by conventional techniques. The resulting source contactextends between the second doped semiconductive materialand the first doped semiconductive materialand contacts (e.g., directly contacts) the channel, the tunnel dielectric material, the charge trap material, and the charge blocking materialof the pillars. The source contactdirectly contacts a lower surface of the second doped semiconductive materialand an upper surface of the first doped semiconductive material. The source contactalso directly contacts upper and lower horizontal surfaces of the tunnel dielectric material, the charge trap material, and the charge blocking materialand sidewalls of the channel. The source contactis separated from the tiersby the second doped semiconductive material.

15 FIG. 120 170 180 120 180 120 182 120 182 122 120 112 182 126 164 182 126 122 120 112 Referring to, a portion of the source contactexposed through the slitand second source contact openingmay be removed, further recessing the source contactadjacent to (e.g., horizontal to) the second source contact opening. The exposed portion of the source contactmay be oxidized by conventional techniques to form a source contact linerof the source contact. The source contact linermay be present on sidewalls of the second doped semiconductive material, the source contact, and the source implant region. The source contact linermay extend to a bottom surface of the lowermost dielectric materialsof the tiers. In this way the source contact linermay form a continuous liner from the bottom surface of the lowermost dielectric materialsof the tiers, along sidewalls of the second doped semiconductive materialand the source contact, and along the upper surface of the source implant region.

136 138 140 130 120 136 138 140 120 120 The tunnel dielectric material, the charge trap material, and the charge blocking materialare not continuous over the entire height of the pillarssince the portions adjacent to (e.g., laterally adjacent to) the source contacthave been removed. Therefore, the portions of the tunnel dielectric material, the charge trap material, and the charge blocking materialbelow the source contactare not in direct contact with the portions above the source contact.

100 16 16 17 17 166 164 128 124 166 164 164 166 164 100 100 16 17 FIGS.and 16 FIG. 17 FIG. 17 FIG. 16 FIG. 1 17 FIGS.- Subsequent process acts are then conducted by conventional techniques to form the electronic deviceas shown in.is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. By way of example only, a replacement gate process is conducted to remove the nitride materialsof the tiersand to form the conductive materialsof the tiers. The nitride materialsmay be removed by exposing the tiersto a wet etch chemistry formulated to remove, for example, silicon nitride of the tiers. The wet etchant may include, but is not limited to, one or more of phosphoric acid, sulfuric acid, hydrochloric acid, nitric acid, or a combination thereof. In some embodiments, the nitride materialsof the tiersare removed using a so-called “wet nitride strip” that includes phosphoric acid. Whileillustrate the formation of the electronic deviceby the replacement gate process, methods according to embodiments of the disclosure may be used to form the electronic deviceby a floating gate process.

146 170 180 146 146 146 146 180 146 146 146 112 146 120 112 146 112 146 122 112 146 122 112 146 100 100 16 FIG. 2 1 2 1 3 1 3 2 A second fill materialmay be formed in the slitand second source contact opening. The second fill materialmay comprise one or more materials such as a single dielectric material, a combination of a dielectric material and silicon, or a combination of a dielectric material and a conductive material. As shown in the cross-section view of, the second fill materialexhibits different widths in the lateral direction, with a lower portion of the second fill materialexhibiting one or more different widths than an upper portion of the second fill material. As the undercut regions of the second source contact openingare filled with the second fill material, the second fill materialexhibits different widths in the lower portion than in the upper portion. The second fill materialis formed above (e.g., vertically above) the source implant region, and the width Wof the second fill materiallaterally adjacent to the source contactmay be narrower than the width Wof the source implant region. In some embodiments the width Wof the portion of the second fill materialmay be substantially the same as or wider than the width Wof the source implant region. The width Wof the portion of the second fill materiallaterally adjacent to the second doped semiconductive materialmay be smaller than the width Wof the source implant region. The width Wof the portion of the second fill materiallaterally adjacent to the second doped semiconductive materialmay be more narrow than the width Wof the source implant region. The different widths of the second fill materialmay be present in some regions of the electronic device, such as in one or more or array regions, periphery regions of the electronic device.

100 102 112 120 102 182 122 120 122 1 FIG. The electronic deviceincludes a source stackas described in the processing act described in reference to, including a source implant region. A source contactis adjacent to (e.g., vertically adjacent to, on) the source stackand includes a source contact liner. A second doped semiconductive materialis adjacent to (e.g., vertically adjacent to, on) the source contact. A material of the second doped semiconductive materialis selected to be selectively removable under some etch conditions and to be resistant to removal under other etch conditions.

124 126 128 122 128 128 128 142 128 Tiersof alternating dielectric materialsand conductive materialsare adjacent to (e.g., vertically adjacent to, on) the second doped semiconductive material. Some of the conductive materialsare configured as so-called “replacement gate” word lines (e.g., word lines formed by a so-called “replacement gate” or “gate late” process). Other conductive materials, such as one or more of the lowermost conductive materials, are configured as select gate sources (SGS)and one or more of the uppermost conductive materialsare configured as select gate drains.

122 100 122 126 124 122 120 142 124 In addition to providing the desired etch selectivity, the second doped semiconductive materialmay be easily integrated into the process of forming the electronic deviceaccording to embodiments of the disclosure. The second doped semiconductive materialmay function as a so-called “capping material” to prevent removal processes from removing portions of the dielectric materialsof the tiersduring removal of the cell films. The second doped semiconductive materialalso provides improved channel conductance at the source contact, by avoiding shielding the electrical field from the SGSof the tiers.

122 120 142 140 122 120 142 122 122 16 FIG. The thickness of the second doped semiconductive materialmay be selected depending on a desired distance between the source contactand the SGSof the tier stack′ (see). The thickness of the second doped semiconductive materialmay be sufficient to separate (e.g., physically separate) the source contactfrom the SGSby a desired distance. The second doped semiconductive materialmay also function as an etch stop material during subsequent process acts. In some embodiments, the thickness of the second doped semiconductive materialis about 500 Å.

130 124 122 120 108 130 132 134 136 138 140 136 138 140 130 100 124 122 142 124 122 124 140 122 120 142 124 122 126 124 Pillars(e.g., memory pillars) extend through the tiers, the second doped semiconductive material, the source contact, and at least partially into the first doped semiconductive material. The pillarsinclude a first fill material, a channel, a tunnel dielectric material, a charge trap material, and a charge blocking material. The tunnel dielectric material, the charge trap material, and the charge blocking materialfunction as tunneling structures of the pillarsof the electronic device. One or more of the tiersproximal to the second doped semiconductive materialfunctions as a select gate source (SGS)and one or more of the tiersdistal to the second doped semiconductive materialfunctions as a select gate drain (SGD). The tiersform a tier stack′ adjacent to the second doped semiconductive material. The distance separating the source contactfrom the SGSof the tiers, corresponds to the thickness of the second doped semiconductive materialand the adjacent dielectric materialof the tiers.

146 112 120 122 124 182 146 112 120 122 The second fill materialis adjacent to (e.g., vertically adjacent to, on) the source implant region, and adjacent to (e.g., laterally adjacent to, next to) the source contact, the second doped semiconductive material, and the tiers stack′. The source contact lineris deposed between the second fill materialand the source implant region, the source contact, and the second doped semiconductive material.

100 100 100 100 100 130 100 100 1 17 FIGS.- One or more electronic deviceaccording to embodiments of the disclosure may be present in an apparatus or in an electronic system. The apparatus including the one or more electronic device, or the electronic system including the one or more electronic devicemay include additional components, which are formed by conventional techniques. The additional components may include, but are not limited to, staircase structures, interdeck structures, contacts, interconnects, data lines (e.g., bit lines), access lines (e.g., word lines), etc. The additional components may be formed during the fabrication of the electronic deviceor after the electronic devicehas been fabricated. By way of example only, one or more of the additional components may be formed before or after the cell films of the pillarsare formed, while other additional components may be formed after the electronic devicehas been fabricated. The additional components may be present in locations of the electronic deviceor the apparatus that are not depicted in the perspectives of.

100 112 102 120 128 106 120 106 134 136 138 140 134 142 122 100 100 During formation of the electronic deviceaccording to embodiments of the disclosure, the source implant regionprovides corrosion protection to the source stack. This protection allows for the source contactto contact the conductive materials, while mitigating corrosion of the source material, through which the source contactmay electrically short to the source material. The electron flow through the channelis also improved. In addition, by eliminating the cell films (the tunnel dielectric material, the charge trap material, the charge blocking material) in a conductive path between the channeland the SGS, sources of charge trap within the conductive path are reduced or eliminated. The second doped semiconductive materialalso provides a process margin during the fabrication of the electronic device. Therefore, electrical control of the electronic deviceaccording to embodiments of the disclosure is improved relative to that of conventional electronic devices having a doped polysilicon material in a similar location, where interactions between a channel and memory cells of the conventional electronic devices occur.

18 33 FIGS.through 1 17 FIGS.- 18 FIG. 19 FIG. 19 FIG. 18 FIG. 18 FIG. 1 2 FIGS.and 200 200 18 18 19 19 214 252 160 250 212 212 An additional embodiment of the invention is shown in, which illustrate the formation of electronic device. The elements and materials of the electronic deviceare substantially the same as those described above for, unless the context indicates otherwise.is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. As shown in, a plugis formed in the second sacrificial materialrather than using the slit sacrificial structureas described above with. A hardmask may be formed adjacent to the first sacrificial material. The hardmask may be used to control the distribution of the source implant region. The source implant regionmay be formed substantially similarly to the previous embodiment.

214 250 214 214 212 214 212 214 270 214 214 250 212 214 200 100 1 20 FIG. The plugmay be formed adjacent (e.g., vertically adjacent to) to the first sacrificial material. The hardmask may be used to control the longitudinal width and location of the plug. The plugmay be located vertically (e.g., above) the source implant region. The plugis formed with a lateral width configured to be the substantially the same as the lateral width Wof the source implant region. The location of the plugcorresponds to a location adjacent to which (e.g., over which) a slit(see) is subsequently formed. The plugmay, for example, include a dielectric material, a liner, and a etch stop material. By way of example only, the dielectric material may be a silicon oxide material, the liner may be a titanium nitride material, and the etch stop material may be tungsten or a tungsten-containing material. Alternatively, the plugmay be formed of a single material, such as aluminum oxide, two materials, or more than three materials as long as the material(s) provide the desired etch selectivity and etch stop functions. The hardmask may be removed to expose the upper surface of the first sacrificial material. By using the same hardmask to form the implant regionand the plug, this embodiment may employ one less process act for preparing the electronic devicewhen compared to the electronic device.

248 202 214 252 250 254 214 222 264 230 230 18 FIG. Similar to the first embodiment, a source contact sacrificial structureis formed over the source stack, as shown in. In this second embodiment, the plug, is within (e.g., embedded in) the second sacrificial material, with the first and a third sacrificial materials,, respectively, below and above the plug. The second doped semiconductive material, tiers, and pillarmay be formed as described in the previous embodiment. Pillarsmay be positioned as described in the previous embodiment.

248 220 248 220 250 252 254 220 214 252 250 214 252 254 250 252 254 230 202 230 A location of the source contact sacrificial structurecorresponds to the location at which the source contactis ultimately formed, and a total thickness of the as-formed source contact sacrificial structuremay be determined by a desired thickness of the source contact. Individual thicknesses of each of the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be selected based on the desired thickness of the source contact. The thickness of the plugand the second sacrificial materialmay be configured to be the same, such that they are collectively form a single plane. By way of example only, the first sacrificial materialmay be formed to a thickness of from about 30 Å to about 400 Å, the plugand second sacrificial materialmay be formed to a thickness of from about 100 Å to about 300 Å, and the third sacrificial materialmay be formed to a thickness of from about 30 Å to about 200 Å. The thickness of each of the first sacrificial material, the second sacrificial material, and the third sacrificial materialmay be sufficient to protect cell film materials of the pillarsand the source stackduring subsequently conducted process acts that provide access to the pillarsby sequentially removing portions of the cell films.

20 FIG. 21 FIG. 21 FIG. 20 FIG. 20 21 FIGS.and 14 FIG. 20 20 21 21 264 222 254 214 270 264 254 276 252 248 264 254 214 264 254 214 214 270 214 270 276 270 270 212 270 212 270 264 222 254 270 254 is a cross-sectional schematic illustration taken through the line-in, andis a cross-sectional schematic illustration taken through the line-in. A portion of the tiers, a portion of the second doped semiconductive material, a portion of the third sacrificial material, and the plugare removed, as shown in, to form a slitthrough the tiers, the third sacrificial materialand to a slit liner openingin the second sacrificial materialof the source contact sacrificial structure. The tiers, the third sacrificial material, and the plugmay be removed by one or more etch processes, such as by using conventional etch conditions. If a single etch process is conducted, the tiers, the third sacrificial material, and the plugmay be substantially removed by the single etch process. If more than one etch process is conducted, the etch stop material of the plugmay function as an etch stop during the first etch process to form the slitand a second etch process may be conducted to remove the plug. For convenience, the slitand the slit liner openingare collectively referred to hereinafter as the slit. The slitis formed vertically above the source implant region. The vertically lowermost portion (e.g., the bottom) of the slitis formed with a lateral width that is less than the lateral width of the source implant region. Whileillustrates the slitas extending through the tiersand the second doped semiconductive materialto an upper surface of the third sacrificial material, the slitmay extend partially into the third sacrificial material.

20 21 FIGS.and 274 270 264 222 276 274 270 274 274 274 As shown in, a slit lineris formed on exposed surfaces in the slitof the tiers, the second doped semiconductive material, and into the slit liner opening. The slit linermay be conformally formed by conventional techniques such that a portion of the slitremains open (e.g., unoccupied). The slit linermay be formed of and include a dielectric material, a semiconductive material, or a conductive material. In some embodiments, the slit lineris undoped polysilicon. The slit linermay be formed to a thickness of from about 200 Å to about 400 Å.

230 248 240 238 236 248 222 22 26 FIGS.- 6 10 FIGS.- To provide access to the pillars, the source contact sacrificial structureand portions of the cell films (charge blocking material, charge trap material, tunnel dielectric material) are sequentially removed, as shown in. The materials may be removed substantially similarly to the acts of the first embodiment describing. The source contact sacrificial structureis removed while a majority of the second doped semiconductive materialremains intact.

22 FIG. 23 FIG. 24 FIG. 25 FIG. 26 FIG. 27 33 FIGS.- 252 248 250 254 240 240 250 254 274 284 278 278 284 238 274 236 284 278 278 234 220 As shown in, the second sacrificial materialof the source contact sacrificial structureis selectively removed without substantially removing the first and third sacrificial materials,or the charge blocking material. This is followed by selective removal of an exposed portion of the charge blocking material, the first sacrificial material, and the third sacrificial materialwithout substantially removing the slit lineras shown in. As shown in, a source contact opening lineris introduced within the source contact opening′ forming the source contact opening″. The exposed vertical portion of the source contact opening linerand the underlying charge trap materialis then selectively removed, as shown in, without substantially removing the slit lineror the source contact opening liner from vertical surfaces. As shown in, the exposed portion of the tunnel dielectric materialis selectively removed, along with the remaining portion of the source contact opening liner′, increasing the size of the first source contact opening″ and forming first source contact opening′″. The exposed portion of the channelmay ultimately be in contact with the source contact(see).

220 280 282 27 31 FIGS.- 11 15 FIGS.- Methods and features described in the formation of the source contact, source contact opening, and the source contact lineras shown inare substantially similar to the methods and features described in the previous embodiment, shown in.

200 100 32 33 FIGS.and 16 17 FIGS.and Subsequent process acts are then conducted to form the electronic deviceas shown in. These subsequent acts are substantially similar to those described in the previous embodiment to describe the electronic device, shown in.

Accordingly, disclosed is an electronic device comprising a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, and a doped semiconductive material adjacent to the source contact. A source implant region is within a top portion of the source stack. Tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material and pillars extend through the tiers, the doped semiconductive material, and the source contact and into the source stack.

Accordingly, disclosed is an electronic device comprising a source stack comprising one or more conductive materials, with a source implant region in the source stack. A source contact is adjacent to the source stack, with sidewalls of the source contact vertically adjacent to the source implant region, and a doped semiconductive material is adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material, and pillars extend through the tiers and into the source stack. A fill material is laterally adjacent to the pillars and extends through the tiers and into the source contact. The fill material laterally adjacent to the source contact exhibits a smaller width in a lateral direction than a width of the source implant region in the lateral direction.

Accordingly, disclosed is a method of forming an electronic device that comprises forming a source implant region within a doped semiconductor material of a source stack. A source contact sacrificial structure is formed adjacent to the source implant region, and a doped semiconductive material is formed adjacent to the source contact sacrificial structure. Tiers are formed adjacent to the doped semiconductive material, the tiers comprising alternating dielectric materials and nitride materials. Pillars are formed through the tiers, the doped semiconductive material and into the source stack, the pillars including a channel, a charge blocking material, and a charge trap material. A slit is formed through the tiers to expose the source contact sacrificial structure, and a portion of the source contact sacrificial structure is removed to form a source contact opening. The source contact opening defined by sidewalls of the source contact and the sidewalls comprise a non-linear profile. A source contact is formed in the source contact opening and the slit. A portion of the source contact opening is removed above the source implant region, and a liner is formed on sidewalls of the source contact and on sidewalls of the doped semiconductive material. The nitride materials in the tiers are replaced with conductive materials and a fill material is formed in the slit.

34 FIG. 16 32 FIGS.and 34 FIG. 16 32 FIGS.and 16 FIG. 300 302 302 100 200 302 326 312 310 302 130 230 314 130 230 314 310 304 308 102 312 316 318 320 142 316 330 328 With reference toillustrated is a partial cutaway, perspective, schematic illustration of a portion of an apparatus(e.g., a memory device) including an electronic deviceaccording to embodiments of the disclosure. The electronic devicemay be substantially similar to the embodiments of the electronic device described above (e.g., the electronic device,of) and may have been formed by the methods described above. By way of example only, the memory device may be a 3D NAND Flash memory device, such as a multideck 3D NAND Flash memory device. As illustrated in, the electronic devicemay include a staircase structuredefining contact regions for connecting access lines (e.g., word lines)to conductive tiers(e.g., conductive regions, conductive materials of tiers). The electronic devicemay include pillars,(see) with strings(e.g., strings of memory cells) that are coupled to each other in series. The pillars,with the stringsmay extend at least somewhat vertically (e.g., in the Z-direction) and orthogonally relative to the conductive tiers, relative to data lines, relative to a source tier(e.g., within one or more base materials under the source stack(see)), relative to the access lines, relative to first select gates(e.g., upper select gates, drain select gates (SGDs)), relative to select lines, and/or relative to second select gates(e.g., SGS). The first select gatesmay be horizontally divided (e.g., in the X-direction) into multiple blocksby slits.

322 318 316 312 310 300 324 304 312 324 304 308 312 316 320 324 324 Vertical conductive contactsmay electrically couple components to each other, as illustrated. For example, the select linesmay be electrically coupled to the first select gates, and the access linesmay be electrically coupled to the conductive tiers. The apparatusmay also include a control unitpositioned under the memory array, which may include at least one of string driver circuitry, pass gates, circuitry for selecting gates, circuitry for selecting conductive lines (e.g., the data lines, the access lines), circuitry for amplifying signals, and circuitry for sensing signals. The control unitmay be electrically coupled to the data lines, the source tier, the access lines, the first select gates, and/or the second select gates, for example. In some embodiments, the control unitincludes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control unitmay be characterized as having a so-called “CMOS under Array” (CuA) configuration.

316 314 306 314 320 314 314 306 The first select gatesmay extend horizontally in a first direction (e.g., the Y-direction) and may be coupled to respective first groups of stringsof memory cellsat a first end (e.g., an upper end) of the strings. The second select gatemay be formed in a substantially planar configuration and may be coupled to the stringsat a second, opposite end (e.g., a lower end) of the stringsof memory cells.

304 316 304 314 314 314 316 314 314 304 314 316 304 316 306 314 306 The data lines(e.g., bit lines) may extend horizontally in a second direction (e.g., in the X-direction) that is at an angle (e.g., perpendicular) to the first direction in which the first select gatesextend. The data linesmay be coupled to respective second groups of the stringsat the first end (e.g., the upper end) of the strings. A first group of stringscoupled to a respective first select gatemay share a particular stringwith a second group of stringscoupled to a respective data line. Thus, a particular stringmay be selected at an intersection of a particular first select gateand a particular data line. Accordingly, the first select gatesmay be used for selecting memory cellsof the stringsof memory cells.

310 104 310 310 314 306 314 306 310 310 306 310 310 306 314 306 316 320 314 306 304 308 306 304 316 320 310 306 16 FIG. The conductive tiers(e.g., word lines, conductive liner materials(e.g.,)) may extend in respective horizontal planes. The conductive tiersmay be stacked vertically, such that each conductive tieris coupled to all of the stringsof memory cells, and the stringsof the memory cellsextend vertically through the stack of conductive tiers. The conductive tiersmay be coupled to or may function as control gates of the memory cellsto which the conductive tiersare coupled. Each conductive tiermay be coupled to one memory cellof a particular stringof memory cells. The first select gatesand the second select gatesmay operate to select a particular stringof the memory cellsbetween a particular data lineand the source tier. Thus, a particular memory cellmay be selected and electrically coupled to a data lineby operation of (e.g., by selecting) the appropriate first select gate, second select gate, and conductive tierthat are coupled to the particular memory cell.

326 312 310 322 310 312 322 310 304 314 332 The staircase structuremay be configured to provide electrical connection between the access linesand the conductive materials of the tiersthrough the vertical conductive contacts. In other words, a particular level of the conductive tiersmay be selected via one of the access linesthat is in electrical communication with a respective one of the vertical conductive contactsin electrical communication with the particular conductive tier. The data linesmay be electrically coupled to the stringsthrough conductive structures(e.g., conductive contacts).

300 100 200 400 400 400 402 100 400 404 404 100 200 35 FIG. The apparatusincluding the electronic devices,may be used in embodiments of electronic systems of the disclosure.is a block diagram of an electronic system, in accordance with embodiments of the disclosure. The electronic systemincludes, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet (e.g., an iPAD® or SURFACE® tablet, an electronic book, a navigation device), etc. The electronic systemincludes at least one memory devicethat includes, for example, one or more electronic devices. The electronic systemmay further include at least one electronic signal processor device(e.g., a microprocessor). The electronic signal processor devicemay, optionally, include one or more electronic devices,.

500 500 506 500 500 508 506 508 500 506 508 502 504 502 504 100 36 FIG. A processor-based system(e.g., an electronic processor-based system), shown in, includes one or more input devicesfor inputting information into the processor-based systemby a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The processor-based systemmay further include one or more output devicesfor outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input deviceand the output devicemay comprise a single touchscreen device that can be used both to input information into the processor-based systemand to output visual information to a user. The input deviceand the output devicemay communicate electrically with one or more of the memory deviceand the electronic signal processor device. The memory deviceand the electronic signal processor devicemay include one or more of the electronic devices.

37 FIG. 600 600 600 100 300 600 600 602 600 602 600 100 300 With reference to, shown is a block diagram of an additional processor-based system(e.g., an electronic processor-based system). The processor-based systemmay include various electronic devicesand apparatusmanufactured in accordance with embodiments of the disclosure. The processor-based systemmay be any of a variety of types, such as a computer, a pager, a cellular phone, a personal organizer, a control circuit, or another electronic device. The processor-based systemmay include one or more processors, such as a microprocessor, to control the processing of system functions and requests in the processor-based system. The processorand other subcomponents of the processor-based systemmay include electronic devicesand apparatusmanufactured in accordance with embodiments of the disclosure.

600 604 602 600 604 604 600 604 600 The processor-based systemmay include a power supplyin operable communication with the processor. For example, if the processor-based systemis a portable system, the power supplymay include one or more of a fuel cell, a power scavenging device, permanent batteries, replaceable batteries, and/or rechargeable batteries. The power supplymay also include an AC adapter if, for example, the processor-based systemmay be plugged into a wall outlet. The power supplymay also include a DC adapter such that the processor-based systemmay be plugged into a vehicle cigarette lighter or a vehicle power port, for example.

602 600 602 606 608 602 608 610 602 610 612 612 602 612 614 Various other devices may be coupled to the processordepending on the functions that the processor-based systemperforms. For example, a user interface may be coupled to the processor. The user interface may include one or more input devices, such as buttons, switches, a keyboard, a light pen, a mouse, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, or a combination thereof. A displaymay also be coupled to the processor. The displaymay include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. Furthermore, an RF subsystem/baseband processormay also be coupled to the processor. The RF subsystem/baseband processormay include an antenna that is coupled to an RF receiver and to an RF transmitter. A communication port, or more than one communication port, may also be coupled to the processor. The communication portmay be adapted to be coupled to one or more peripheral devices(e.g., a modem, a printer, a computer, a scanner, a camera) and/or to a network (e.g., a local area network (LAN), a remote area network, an intranet, or the Internet).

602 600 616 602 602 616 616 616 616 300 100 The processormay control the processor-based systemby implementing software programs stored in the memory (e.g., system memory). The software programs may include an operating system, database software, drafting software, word processing software, media editing software, and/or media-playing software, for example. The memory is operably coupled to the processorto store and facilitate execution of various programs. For example, the processormay be coupled to system memory, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and/or other known memory types. The system memorymay include volatile memory, nonvolatile memory, or a combination thereof. The system memoryis typically large so it can store dynamically loaded applications and data. The system memorymay include one or more apparatusand one or more electronic devicesaccording to embodiments of the disclosure.

602 618 616 618 616 618 618 618 300 100 The processormay also be coupled to non-volatile memory, which is not to suggest that system memoryis necessarily volatile. The non-volatile memorymay include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and Flash memory to be used in conjunction with the system memory. The size of the non-volatile memoryis typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memorymay include a high-capacity memory (e.g., disk drive memory, such as a hybrid-drive including resistive memory or other types of nonvolatile solid-state memory, for example). The non-volatile memorymay include one or more apparatusand one or more electronic devicesaccording to embodiments of the disclosure.

Accordingly, disclosed is an electronic system comprising an input device, an output device, a processor device operably coupled to the input device and to the output device, and one or more memory devices operably coupled to the processor device. The one or more memory devices comprises a source contact adjacent to a source stack, a source implant region in the source stack, sidewalls of the source contact are above the source implant region, a semiconductive material adjacent to the source contact, tiers of alternating conductive materials and dielectric materials adjacent to the semiconductive material, and memory pillars extending through the tiers, the semiconductive material, the source contact, and partially into the source stack.

While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure.