Techniques for improved data transfer

The present Application for Patent claims priority to U.S. Patent Application No. 63/478,537 by Mulani et al., entitled “TECHNIQUES FOR IMPROVED DATA TRANSFER.” filed Jan. 5, 2023, which is assigned to the assignee hereof, and which is expressly incorporated by reference herein.

The following relates to one or more systems for memory, including techniques for improved data transfer.

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.

Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D cross point), not-or (NOR) and not-and (NAND) memory devices, and others. Memory devices may be described in terms of volatile configurations or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed states over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND) may maintain their programmed states for extended periods of time even in the absence of an external power source.

In some cases, a memory device (e.g., Not-AND (NAND) memory device) may include memory cells configured to each store one bit of information, which may be referred to as single level cells (SLCs). Additionally, or alternatively, a memory device may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, as penta-level cells (PLCs) if configured to each store five bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

Some memory systems may include multiple layers of error correction codes for data stored to sets of memory cells storing multiple bits and associated with weak word lines. Such memory cells may be associated with a higher probability of memory errors during a read or write operation (e.g., memory cells associated with a weak word line may produce bit errors more frequently than word lines in other cells). Accordingly, as part of a data transfer operation to transfer data from a source set of memory cells, such as SLC blocks, TLC blocks, QLC blocks, or PLC blocks, to a destination QLC or PLC block associated with a weak word line, some memory systems may transfer the data from the source set of memory cells of a memory device to an associated memory controller. The memory controller may detect or correct errors in the data using first parity information included in the data. Further, the memory controller may generate additional parity information to provide added protection, and may transfer the data, along with the additional parity information, back to the memory device, which may store the data and the parity information in the destination set of memory cells. However, such implementations may cause additional overhead costs (e.g., increased power consumption from transferring data back to the memory device, increased latency) and may cause decreased overall performance. Such implementations may also use larger memory buffers (e.g., a buffer on the memory controller) to hold source data while data and parity information is prepared to transfer to the memory device. Accordingly, techniques to improve memory device data transfers, and error detection and correction during such transfers, are desired

As described herein, as part of a data transfer operation from a first set of memory cells to a second set of memory cells associated with a weak word line, a memory controller may read one or more data units from the first set of memory cells. In some cases, the memory device may store a copy of the one or more data units in a set of latches, and may transmit the set of data units to the memory controller. The memory controller may decode the set of data units, and, if the memory controller detects and corrects an error, may generate one or more corrected data units. The memory controller may then generate parity information for the set of data units, and may encode and transmit the parity information, along with any corrected data units (e.g., without transferring the uncorrected data units), to the memory device. The memory device may update the set of latches to include any corrected data units, and may store the set of data units written to the latches in the second set of memory cells. Such a process may reduce traffic memory space used to perform data transfer operations, which may improve efficiency of the memory system.

1 2 FIGS.through 3 4 FIGS.through 5 6 FIGS.through Features of the disclosure are initially described in the context of systems, devices, and circuits with reference to. Features of the disclosure are described in the context of systems with reference to. These and other features of the disclosure are further illustrated by and described in the context of an apparatus diagram and flowchart that relate to techniques for improved data transfer with reference to.

1 FIG. 100 100 105 110 illustrates an example of a systemthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The systemincludes a host systemcoupled with a memory system.

110 110 A memory systemmay be or include any device or collection of devices, where the device or collection of devices includes at least one memory array. For example, a memory systemmay be or include a Universal Flash Storage (UFS) device, an embedded Multi-Media Controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

100 The systemmay be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

100 105 110 106 105 105 105 110 105 105 110 110 110 110 105 110 1 FIG. The systemmay include a host system, which may be coupled with the memory system. In some examples, this coupling may include an interface with a host system controller, which may be an example of a controller or control component configured to cause the host systemto perform various operations in accordance with examples as described herein. The host systemmay include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host systemmay include an application configured for communicating with the memory systemor a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system), a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., peripheral component interconnect express (PCIe) controller, serial advanced technology attachment (SATA) controller). The host systemmay use the memory system, for example, to write data to the memory systemand read data from the memory system. Although one memory systemis shown in, the host systemmay be coupled with any quantity of memory systems.

105 110 105 110 110 105 106 105 115 110 105 110 106 115 130 110 130 110 The host systemmay be coupled with the memory systemvia at least one physical host interface. The host systemand the memory systemmay, in some cases, be configured to communicate via a physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory systemand the host system). Examples of a physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fiber Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., DIMM socket interface that supports DDR), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces may be included in or otherwise supported between a host system controllerof the host systemand a memory system controllerof the memory system. In some examples, the host systemmay be coupled with the memory system(e.g., the host system controllermay be coupled with the memory system controller) via a respective physical host interface for each memory deviceincluded in the memory system, or via a respective physical host interface for each type of memory deviceincluded in the memory system.

110 115 130 130 130 130 110 130 110 130 130 110 a b 1 FIG. The memory systemmay include a memory system controllerand one or more memory devices. A memory devicemay include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although two memory devices-and-are shown in the example of, the memory systemmay include any quantity of memory devices. Further, if the memory systemincludes more than one memory device, different memory deviceswithin the memory systemmay include the same or different types of memory cells.

115 105 110 115 130 130 115 105 130 130 115 105 130 115 105 130 105 115 130 105 The memory system controllermay be coupled with and communicate with the host system(e.g., via the physical host interface) and may be an example of a controller or control component configured to cause the memory systemto perform various operations in accordance with examples as described herein. The memory system controllermay also be coupled with and communicate with memory devicesto perform operations such as reading data, writing data, erasing data, or refreshing data at a memory device—among other such operations—which may generically be referred to as access operations. In some cases, the memory system controllermay receive commands from the host systemand communicate with one or more memory devicesto execute such commands (e.g., at memory arrays within the one or more memory devices). For example, the memory system controllermay receive commands or operations from the host systemand may convert the commands or operations into instructions or appropriate commands to achieve the desired access of the memory devices. In some cases, the memory system controllermay exchange data with the host systemand with one or more memory devices(e.g., in response to or otherwise in association with commands from the host system). For example, the memory system controllermay convert responses (e.g., data packets or other signals) associated with the memory devicesinto corresponding signals for the host system.

115 130 115 105 130 The memory system controllermay be configured for other operations associated with the memory devices. For example, the memory system controllermay execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host systemand physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices.

115 115 115 The memory system controllermay include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware may include circuitry with dedicated (e.g., hard-coded) logic to perform the operations ascribed herein to the memory system controller. The memory system controllermay be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

115 120 120 115 115 120 115 115 120 115 120 130 120 105 130 The memory system controllermay also include a local memory. In some cases, the local memorymay include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) executable by the memory system controllerto perform functions ascribed herein to the memory system controller. In some cases, the local memorymay additionally, or alternatively, include static random access memory (SRAM) or other memory that may be used by the memory system controllerfor internal storage or calculations, for example, related to the functions ascribed herein to the memory system controller. Additionally, or alternatively, the local memorymay serve as a cache for the memory system controller. For example, data may be stored in the local memoryif read from or written to a memory device, and the data may be available within the local memoryfor subsequent retrieval for or manipulation (e.g., updating) by the host system(e.g., with reduced latency relative to a memory device) in accordance with a cache policy.

110 115 110 115 110 105 135 130 115 115 105 135 130 115 1 FIG. Although the example of the memory systeminhas been illustrated as including the memory system controller, in some cases, a memory systemmay not include a memory system controller. For example, the memory systemmay additionally, or alternatively, rely on an external controller (e.g., implemented by the host system) or one or more local controllers, which may be internal to memory devices, respectively, to perform the functions ascribed herein to the memory system controller. In general, one or more functions ascribed herein to the memory system controllermay, in some cases, be performed instead by the host system, a local controller, or any combination thereof. In some cases, a memory devicethat is managed at least in part by a memory system controllermay be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

130 130 130 130 A memory devicemay include one or more arrays of non-volatile memory cells. For example, a memory devicemay include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magneto RAM (MRAM), NOR (e.g., NOR flash) memory. Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally, or alternatively, a memory devicemay include one or more arrays of volatile memory cells. For example, a memory devicemay include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

130 135 130 135 115 115 130 135 130 135 1 FIG. a a b b. In some examples, a memory devicemay include (e.g., on a same die or within a same package) a local controller, which may execute operations on one or more memory cells of the respective memory device. A local controllermay operate in conjunction with a memory system controlleror may perform one or more functions ascribed herein to the memory system controller. For example, as illustrated in, a memory device-may include a local controller-and a memory device-may include a local controller-

130 130 160 130 160 160 160 165 165 170 170 175 175 In some cases, a memory devicemay be or include a NAND device (e.g., NAND flash device). A memory devicemay be or include a die(e.g., a memory die). For example, in some cases, a memory devicemay be a package that includes one or more dies. A diemay, in some examples, be a piece of electronics-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each diemay include one or more planes, and each planemay include a respective set of blocks, where each blockmay include a respective set of pages, and each pagemay include a set of memory cells.

165 170 165 170 170 165 170 180 170 170 170 170 170 165 165 165 165 170 170 170 170 180 170 130 130 130 170 165 170 165 170 165 165 175 165 165 a b c d a b c d a b c d a b a a b b In some cases, planesmay refer to groups of blocks, and in some cases, concurrent operations may be performed on different planes. For example, concurrent operations may be performed on memory cells within different blocksso long as the different blocksare in different planes. In some cases, an individual blockmay be referred to as a physical block, and a virtual blockmay refer to a group of blockswithin which concurrent operations may occur. For example, concurrent operations may be performed on blocks-,-,-, and-that are within planes-,-,-, and-, respectively, and blocks-,-,-, and-may be collectively referred to as a virtual block. In some cases, a virtual block may include blocksfrom different memory devices(e.g., including blocks in one or more planes of memory device-and memory device-). In some cases, the blockswithin a virtual block may have the same block address within their respective planes(e.g., block-may be “block 0” of plane-, block-may be “block 0” of plane-, and so on). In some cases, performing concurrent operations in different planesmay be subject to one or more restrictions, such as concurrent operations being performed on memory cells within different pagesthat have the same page address within their respective planes(e.g., related to command decoding, page address decoding circuitry, or other circuitry being shared across planes).

170 175 175 In some cases, a blockmay include memory cells organized into rows (pages) and columns (e.g., strings, not shown). For example, memory cells in a same pagemay share (e.g., be coupled with) a common word line, and memory cells in a same string may share (e.g., be coupled with) a common digit line (which may alternatively be referred to as a bit line).

175 170 175 170 175 For some NAND architectures, memory cells may be read and programmed (e.g., written) at a first level of granularity (e.g., at the page level of granularity) but may be erased at a second level of granularity (e.g., at the block level of granularity). That is, a pagemay be the smallest unit of memory (e.g., set of memory cells) that may be independently programmed or read (e.g., programed or read concurrently as part of a single program or read operation), and a blockmay be the smallest unit of memory (e.g., set of memory cells) that may be independently erased (e.g., erased concurrently as part of a single erase operation). Further, in some cases, NAND memory cells may be erased before they can be re-written with new data. Thus, for example, a used pagemay, in some cases, not be updated until the entire blockthat includes the pagehas been erased.

170 170 130 170 170 130 135 115 170 170 170 170 130 170 165 135 115 In some cases, to update some data within a blockwhile retaining other data within the block, the memory devicemay copy the data to be retained to a new blockand write the updated data to one or more remaining pages of the new block. The memory device(e.g., the local controller) or the memory system controllermay mark or otherwise designate the data that remains in the old blockas invalid or obsolete and may update a logical-to-physical (L2P) mapping table to associate the logical address (e.g., LBA) for the data with the new, valid blockrather than the old, invalid block. In some cases, such copying and remapping may be performed instead of erasing and rewriting the entire old blockdue to latency or wearout considerations, for example. In some cases, one or more copies of an L2P mapping table may be stored within the memory cells of the memory device(e.g., within one or more blocksor planes) for use (e.g., reference and updating) by the local controlleror memory system controller.

115 135 130 130 170 175 175 175 170 170 170 170 175 175 175 170 175 170 170 170 105 In some cases, a memory system controlleror a local controllermay perform operations (e.g., as part of one or more media management algorithms) for a memory device, such as wear leveling, background refresh, garbage collection, scrub, block scans, health monitoring, or others, or any combination thereof. For example, within a memory device, a blockmay have some pagescontaining valid data and some pagescontaining invalid data. To avoid waiting for all of the pagesin the blockto have invalid data in order to erase and reuse the block, an algorithm referred to as “garbage collection” may be invoked to allow the blockto be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting a blockthat contains valid and invalid data, selecting pagesin the block that contain valid data, copying the valid data from the selected pagesto new locations (e.g., free pagesin another block), marking the data in the previously selected pagesas invalid, and erasing the selected block. As a result, the quantity of blocksthat have been erased may be increased such that more blocksare available to store subsequent data (e.g., data subsequently received from the host system).

110 115 135 In some cases, a memory systemmay utilize a memory system controllerto provide a managed memory system that may include, for example, one or more memory arrays and related circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller). An example of a managed memory system is a managed NAND (MNAND) system.

100 105 106 110 115 130 135 105 110 130 105 106 110 115 130 135 105 110 130 The systemmay include any quantity of non-transitory computer readable media that support techniques for improved data transfer. For example, the host system(e.g., a host system controller), the memory system(e.g., a memory system controller), or a memory device(e.g., a local controller) may include or otherwise may access one or more non-transitory computer readable media storing instructions (e.g., firmware, logic, code) for performing the functions ascribed herein to the host system, the memory system, or a memory device. For example, such instructions, if executed by the host system(e.g., by a host system controller), by the memory system(e.g., by a memory system controller), or by a memory device(e.g., by a local controller), may cause the host system, the memory system, or the memory deviceto perform associated functions as described herein.

130 130 115 110 175 130 135 115 115 115 115 130 130 110 a a a a a a In some cases, as part of a data transfer operation from a first set of memory cells of a memory device-to a second set of memory cells of the memory device-associated with a weak word line, a memory system controllerof the memory systemmay read one or more data units (e.g., corresponding to one or more pages) from the first set of memory cells. In some cases, the memory device-may store a copy of the one or more data units in a set of latches (e.g., a set of latches of the local controller-), and may transmit the set of data units to the memory system controller. The memory system controllermay decode the set of data units, and, if the memory system controllerdetects and corrects an error, may generate one or more corrected data units. The memory system controllermay then generate parity information for the set of data units, and may encode and transmit the parity information, along with any corrected data units (e.g., without transferring the uncorrected data units), to the memory device-. The memory device-may update the set of latches to include any corrected data units, and may store the set of data units written to the latches in the second set of memory cells. Such a process may reduce traffic memory space used to perform data transfer operations, which may improve efficiency of the memory system.

2 FIG. 1 FIG. 1 FIG. 200 200 100 200 210 205 205 205 200 100 210 205 110 105 illustrates an example of a systemthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The systemmay be an example of a systemas described with reference to, or aspects thereof. The systemmay include a memory systemconfigured to store data received from the host systemand to send data to the host system, if requested by the host systemusing access commands (e.g., read commands or write commands). The systemmay implement aspects of the systemas described with reference to. For example, the memory systemand the host systemmay be examples of the memory systemand the host system, respectively.

210 240 210 205 205 240 240 1 FIG. The memory systemmay include one or more memory devicesto store data transferred between the memory systemand the host system(e.g., in response to receiving access commands from the host system). The memory devicesmay include one or more memory devices as described with reference to. For example, the memory devicesmay include NAND memory, PCM, self-selecting memory, 3D cross point or other chalcogenide-based memories, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM, among other examples.

210 230 240 230 240 240 230 240 210 230 230 240 230 135 1 FIG. The memory systemmay include a storage controllerfor controlling the passing of data directly to and from the memory devices(e.g., for storing data, for retrieving data, for determining memory locations in which to store data and from which to retrieve data). The storage controllermay communicate with memory devicesdirectly or via a bus (not shown), which may include using a protocol specific to each type of memory device. In some cases, a single storage controllermay be used to control multiple memory devicesof the same or different types. In some cases, the memory systemmay include multiple storage controllers(e.g., a different storage controllerfor each type of memory device). In some cases, a storage controllermay implement aspects of a local controlleras described with reference to.

210 220 205 225 205 240 220 225 230 205 240 250 The memory systemmay include an interfacefor communication with the host system, and a bufferfor temporary storage of data being transferred between the host systemand the memory devices. The interface, buffer, and storage controllermay support translating data between the host systemand the memory devices(e.g., as shown by a data path), and may be collectively referred to as data path components.

225 225 225 225 225 Using the bufferto temporarily store data during transfers may allow data to be buffered while commands are being processed, which may reduce latency between commands and may support arbitrary data sizes associated with commands. This may also allow bursts of commands to be handled, and the buffered data may be stored, or transmitted, or both (e.g., after a burst has stopped). The buffermay include relatively fast memory (e.g., some types of volatile memory, such as SRAM or DRAM), or hardware accelerators, or both to allow fast storage and retrieval of data to and from the buffer. The buffermay include data path switching components for bi-directional data transfer between the bufferand other components.

225 225 225 225 225 205 225 A temporary storage of data within a buffermay refer to the storage of data in the bufferduring the execution of access commands. For example, after completion of an access command, the associated data may no longer be maintained in the buffer(e.g., may be overwritten with data for additional access commands). In some examples, the buffermay be a non-cache buffer. For example, data may not be read directly from the bufferby the host system. In some examples, read commands may be added to a queue without an operation to match the address to addresses already in the buffer(e.g., without a cache address match or lookup operation).

210 215 205 215 115 235 1 FIG. The memory systemalso may include a memory system controllerfor executing the commands received from the host system, which may include controlling the data path components for the moving of the data. The memory system controllermay be an example of the memory system controlleras described with reference to. A busmay be used to communicate between the system components.

260 265 270 205 210 260 265 270 220 215 230 210 In some cases, one or more queues (e.g., a command queue, a buffer queue, a storage queue) may be used to control the processing of access commands and the movement of corresponding data. This may be beneficial, for example, if more than one access command from the host systemis processed concurrently by the memory system. The command queue, buffer queue, and storage queueare depicted at the interface, memory system controller, and storage controller, respectively, as examples of a possible implementation. However, queues, if implemented, may be positioned anywhere within the memory system.

205 240 210 210 235 250 235 215 205 240 235 210 Data transferred between the host systemand the memory devicesmay be conveyed along a different path in the memory systemthan non-data information (e.g., commands, status information). For example, the system components in the memory systemmay communicate with each other using a bus, while the data may use the data paththrough the data path components instead of the bus. The memory system controllermay control how and if data is transferred between the host systemand the memory devicesby communicating with the data path components over the bus(e.g., using a protocol specific to the memory system).

205 210 220 220 210 220 215 235 260 220 215 If a host systemtransmits access commands to the memory system, the commands may be received by the interface(e.g., according to a protocol, such as a UFS protocol or an eMMC protocol). Thus, the interfacemay be considered a front end of the memory system. After receipt of each access command, the interfacemay communicate the command to the memory system controller(e.g., via the bus). In some cases, each command may be added to a command queueby the interfaceto communicate the command to the memory system controller.

215 220 215 260 260 215 215 220 235 260 The memory system controllermay determine that an access command has been received based on the communication from the interface. In some cases, the memory system controllermay determine the access command has been received by retrieving the command from the command queue. The command may be removed from the command queueafter it has been retrieved (e.g., by the memory system controller). In some cases, the memory system controllermay cause the interface(e.g., via the bus) to remove the command from the command queue.

215 240 205 205 240 215 225 205 225 210 225 220 225 230 After a determination that an access command has been received, the memory system controllermay execute the access command. For a read command, this may include obtaining data from one or more memory devicesand transmitting the data to the host system. For a write command, this may include receiving data from the host systemand moving the data to one or more memory devices. In either case, the memory system controllermay use the bufferfor, among other things, temporary storage of the data being received from or sent to the host system. The buffermay be considered a middle end of the memory system. In some cases, buffer address management (e.g., pointers to address locations in the buffer) may be performed by hardware (e.g., dedicated circuits) in the interface, buffer, or storage controller.

205 215 225 215 225 To process a write command received from the host system, the memory system controllermay determine if the bufferhas sufficient available space to store the data associated with the command. For example, the memory system controllermay determine (e.g., via firmware, via controller firmware), an amount of space within the bufferthat may be available to store data associated with the write command.

265 225 265 225 260 265 215 265 225 265 225 225 265 205 In some cases, a buffer queuemay be used to control a flow of commands associated with data stored in the buffer, including write commands. The buffer queuemay include the access commands associated with data currently stored in the buffer. In some cases, the commands in the command queuemay be moved to the buffer queueby the memory system controllerand may remain in the buffer queuewhile the associated data is stored in the buffer. In some cases, each command in the buffer queuemay be associated with an address at the buffer. For example, pointers may be maintained that indicate where in the bufferthe data associated with each command is stored. Using the buffer queue, multiple access commands may be received sequentially from the host systemand at least portions of the access commands may be processed concurrently.

225 215 220 205 220 205 220 225 250 220 225 265 225 220 215 235 225 If the bufferhas sufficient space to store the write data, the memory system controllermay cause the interfaceto transmit an indication of availability to the host system(e.g., a “ready to transfer” indication), which may be performed in accordance with a protocol (e.g., a UFS protocol, an eMMC protocol). As the interfacereceives the data associated with the write command from the host system, the interfacemay transfer the data to the bufferfor temporary storage using the data path. In some cases, the interfacemay obtain (e.g., from the buffer, from the buffer queue) the location within the bufferto store the data. The interfacemay indicate to the memory system controller(e.g., via the bus) if the data transfer to the bufferhas been completed.

225 220 225 240 230 215 230 225 250 240 230 210 230 215 235 240 After the write data has been stored in the bufferby the interface, the data may be transferred out of the bufferand stored in a memory device, which may involve operations of the storage controller. For example, the memory system controllermay cause the storage controllerto retrieve the data from the bufferusing the data pathand transfer the data to a memory device. The storage controllermay be considered a back end of the memory system. The storage controllermay indicate to the memory system controller(e.g., via the bus) that the data transfer to one or more memory deviceshas been completed.

270 215 235 265 270 270 270 225 240 230 225 265 270 225 230 240 270 215 270 230 215 In some cases, a storage queuemay support a transfer of write data. For example, the memory system controllermay push (e.g., via the bus) write commands from the buffer queueto the storage queuefor processing. The storage queuemay include entries for each access command. In some examples, the storage queuemay additionally include a buffer pointer (e.g., an address) that may indicate where in the bufferthe data associated with the command is stored and a storage pointer (e.g., an address) that may indicate the location in the memory devicesassociated with the data. In some cases, the storage controllermay obtain (e.g., from the buffer, from the buffer queue, from the storage queue) the location within the bufferfrom which to obtain the data. The storage controllermay manage the locations within the memory devicesto store the data (e.g., performing wear-leveling, performing garbage collection). The entries may be added to the storage queue(e.g., by the memory system controller). The entries may be removed from the storage queue(e.g., by the storage controller, by the memory system controller) after completion of the transfer of the data.

205 215 225 215 225 To process a read command received from the host system, the memory system controllermay determine if the bufferhas sufficient available space to store the data associated with the command. For example, the memory system controllermay determine (e.g., via firmware, via controller firmware), an amount of space within the bufferthat may be available to store data associated with the read command.

265 225 215 230 240 225 250 230 215 235 225 In some cases, the buffer queuemay support buffer storage of data associated with read commands in a similar manner as discussed with respect to write commands. For example, if the bufferhas sufficient space to store the read data, the memory system controllermay cause the storage controllerto retrieve the data associated with the read command from a memory deviceand store the data in the bufferfor temporary storage using the data path. The storage controllermay indicate to the memory system controller(e.g., via the bus) when the data transfer to the bufferhas been completed.

270 215 270 230 225 270 240 230 265 225 230 270 225 215 270 260 In some cases, the storage queuemay be used to aid with the transfer of read data. For example, the memory system controllermay push the read command to the storage queuefor processing. In some cases, the storage controllermay obtain (e.g., from the buffer, from the storage queue) the location within one or more memory devicesfrom which to retrieve the data. In some cases, the storage controllermay obtain (e.g., from the buffer queue) the location within the bufferto store the data. In some cases, the storage controllermay obtain (e.g., from the storage queue) the location within the bufferto store the data. In some cases, the memory system controllermay move the command processed by the storage queueback to the command queue.

225 230 225 205 215 220 225 250 205 220 260 215 235 205 Once the data has been stored in the bufferby the storage controller, the data may be transferred from the bufferand sent to the host system. For example, the memory system controllermay cause the interfaceto retrieve the data from the bufferusing the data pathand transmit the data to the host system(e.g., according to a protocol, such as a UFS protocol or an eMMC protocol). For example, the interfacemay process the command from the command queueand may indicate to the memory system controller(e.g., via the bus) that the data transmission to the host systemhas been completed.

215 260 215 225 225 265 265 215 225 265 The memory system controllermay execute received commands according to an order (e.g., a first-in-first-out order, according to the order of the command queue). For each command, the memory system controllermay cause data corresponding to the command to be moved into and out of the buffer, as discussed herein. As the data is moved into and stored within the buffer, the command may remain in the buffer queue. A command may be removed from the buffer queue(e.g., by the memory system controller) if the processing of the command has been completed (e.g., if data corresponding to the access command has been transferred out of the buffer). If a command is removed from the buffer queue, the address previously storing the data associated with that command may be available to store data associated with a new command.

215 240 215 205 240 205 215 230 215 215 230 230 In some examples, the memory system controllermay be configured for operations associated with one or more memory devices. For example, the memory system controllermay execute or manage operations such as wear-leveling operations, garbage collection operations, error control operations such as error-detecting operations or error-correcting operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., LBAs) associated with commands from the host systemand physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices. For example, the host systemmay issue commands indicating one or more LBAs and the memory system controllermay identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs may correspond to noncontiguous physical block addresses. In some cases, the storage controllermay be configured to perform one or more of the described operations in conjunction with or instead of the memory system controller. In some cases, the memory system controllermay perform the functions of the storage controllerand the storage controllermay be omitted.

240 24 215 210 240 215 215 215 215 240 240 210 In some cases, as part of a data transfer operation from a first set of memory cells of a memory deviceto a second set of memory cells of the memory deviceassociated with a weak word line, a memory system controllerof the memory systemmay read one or more data units from the first set of memory cells. In some cases, the memory devicemay store a copy of the one or more data units in a set of latches, and may transmit the set of data units to the memory system controller. The memory system controllermay decode the set of data units, and, if the memory system controllerdetects and corrects an error, may generate one or more corrected data units. The memory system controllermay then generate parity information for the set of data units, and may encode and transmit the parity information, along with any corrected data units (e.g., without transferring the uncorrected data units), to the memory device. The memory devicemay update the set of latches to include any corrected data units, and may store the set of data units written to the latches in the second set of memory cells. Such a process may reduce traffic memory space used to perform data transfer operations, which may improve efficiency of the memory system.

3 FIG. 1 2 FIGS.and 300 300 330 130 240 330 105 205 illustrates an example of a systemthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The systemmay include a memory device, which may be an example of a memory deviceor a memory device, as described with reference to. In some cases, the memory devicemay include one or more sets of memory cells, which may be used to store data received from a host system, such as the host systemor the host system.

330 350 350 355 330 330 335 355 335 335 335 335 300 335 340 340 340 335 300 340 300 340 For example, the memory devicemay be integrated within a memory system, which may be configured to store data received from a host system. The memory systemmay include a memory system controller, which may transmit data received from the host system to the memory device. The memory devicemay include a set of memory cell as part of a cache, which may store data received from the memory system controller(e.g., as part of a write command). In some cases, the memory cells of the cachemay include memory cells that each store a single bit of data (e.g., the cachemay include one or more SLC blocks), which may improve speed and reliability of performing write commands from the host. In some examples, as the cachebecomes full or nearly full (e.g., if the amount of data stored in the cacheexceeds a threshold), the systemmay initiate a data transfer operation to transfer data from the cacheto a second set of memory cells, such as a storage. The storagemay include memory cells that each store multiple bits of data, such as four bits of data or five bits of data (e.g., the storagemay include one or more QLC or PLC blocks), which may free storage space within the cache. In some examples, such a data transfer operation may be referred to as a folding operation. Additionally or alternatively, the systemmay transfer data to the storageas part of other data management operations, such as a garbage collection operation. For example, the systemmay transfer data to the storagefrom one or more blocks of memory cells, such as one or more SLC blocks, one or more MLC blocks, one or more TLC blocks, one or more QLC blocks, one or more PLC blocks, or any combination thereof.

340 335 340 335 340 340 In some cases, memory cells of the storagemay be associated with a smaller read margin than memory cells of the cache(e.g., due to the memory cells of the storagestoring more bits than the memory cells of the cache). Accordingly, data stored in the storagemay include additional parity information to improve data reliability. For example, if the storageincludes memory cells coupled with a weak word line, data stored in those memory cells may include additional parity information compared with data stored in memory cells not coupled with a weak word line.

330 300 300 335 340 300 A weak word line may include or may refer to a word line having a physical characteristic associated with increased bit error rates, such as a word line that is located at an edge of a memory array. Additionally or alternatively, weak word lines may be word lines identified as having defects, such as mechanical defects caused during manufacturing or other conditions which may increase the likelihood of errors in data associated with the weak word line. In some cases, weak word lines of a memory devicemay be identified during manufacturing, such as during a testing phase, and an indication of the weak word lines (e.g., an address) may be stored in the system. Additionally, the systemmay not support transferring data directly from the cacheto the memory cells associated with a weak word line of the storage(e.g., may not support an internal copyback operation), for example due to an increased likelihood for error from cross-temperature read (e.g., reading data from memory cells at a temperature to which data was written at a substantially different temperature) or high temperature transfers, or because the systemmay not be configured to perform an internal copyback.

335 305 340 330 325 325 335 325 320 325 320 330 325 320 340 a f Instead, to transfer data from a first set of memory cells of the cacheto a second set of memory cells of associated with a word lineof the storage(e.g., a weak word line), the memory devicemay transfer one or more sets of data units, such as the sets of data units-through-from the cacheto a memory controller. The memory controller may perform an error correction operation, such as a decoding operation, on each data unit of the set of data unitsto determine whether the data units contain errors, and correct at least a portion of detected errors. Further, the memory controller may generate parity informationfor the set of data unitsand transfer the parity information, along with any corrected data units, to the memory deviceto store the set of data unitsand the parity informationin the second set of memory cells of the storage.

305 325 310 310 310 310 315 315 315 315 310 325 320 310 325 320 310 a f a b c d 3 FIG. In some cases, the word linemay store one or more sets of data unitsacross a set of planes, such as the planes-through-. The set of planesmay include memory cells having multiple levels, such as memory cells of a QLC block having a first level-, a second level-, a third level-, and a fourth level-, a set of data units may be distributed across the set of planeson a word line. In some examples, a set of data units, along with the corresponding parity information, may be stored across multiple planes, as illustrated in. Additionally or alternatively, the set of data unitsand associated parity informationmay be stored in a single plane.

3 FIG. Although the example described with reference tomay use memory cells of a QLC block as an illustrative example, one skilled in the art may appreciate that the techniques described herein may be similarly applied to memory cells which store any quantity of levels (e.g., SLC blocks, MLC blocks, TLC blocks, QLC blocks, PLC blocks, and so on).

4 FIG. 1 3 FIGS.through 400 400 440 415 415 420 425 435 455 415 440 illustrates an example of a systemthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The systemmay include a memory deviceand a memory controller, which may be examples of the corresponding devices as described with reference to. The memory controllermay include a buffer, a decoder, an encoder, and a parity generator. The memory controllerand the memory devicemay support communication of various data units containing parity information, codeword data, or any combination thereof.

415 410 410 405 450 415 450 415 440 410 410 440 410 410 405 415 440 410 440 410 415 a e a e a e As part of a data transfer operation (e.g., a folding operation, a garbage collection operation), the memory controllermay determine to transfer a set of data units, such as the data units-through-, from a source set of memory cellsto a destination set of memory cells. If the memory controllerdetermines that the destination set of memory cellsis associated with a weak word line, the memory controllermay transmit a command (e.g., a read command) to the memory deviceto retrieve the data units-through-. Upon receiving the command, the memory devicemay transmit the data units-through-from the source set of memory cellsto the memory controller. In some cases, prior to transmitting the data units, the memory devicemay store the data unitsone or more latches of the memory device, and may retain the data unitsafter transmitting the data units to the memory controller.

440 410 415 410 425 415 425 425 425 425 412 In some examples, data units stored in the memory devicemay be encoded and stored as codewords (e.g., using an encoding or error correction scheme, such as a low density parity check (LDPC) scheme). Accordingly, upon receiving the set of encoded data units, the memory controllermay initiate a decoding process on the set of encoded data unitsusing the decoder. As part of the decoding process, the memory controllermay perform an LDPC decoding procedure. For example, the decodermay decode each data unit (e.g., using a sparse parity-check matrix used to define the codewords), which may allow the decoderto detect errors, correct errors, or both using parity data included in the received codewords. If the decodercorrects an error or a threshold quantity of errors, the decodermay generate one or more corrected data units, such as the corrected data unit.

415 410 425 420 410 435 455 The memory controllermay issue and store the set of decoded data units, and in cases in which the decodercorrected at least one error, the one or more corrected data units, to the buffer. In some cases, the decoded data unitsmay remain in the buffer until the encoderand the parity generatorare available.

415 410 412 425 420 435 410 412 410 410 412 455 445 410 435 445 The memory controllermay transfer the decoded set of data units, including the corrected data unit, if generated by the decoder, from the bufferto the encoderto encode the set of data unitsand the corrected data unit, if present, to obtain encoded representations of the set of data units(e.g., the original encoded data unitsand/or any reencoded data units generated from the corrected data units). The parity generatormay perform an error control procedure to generate parity information(e.g., dynamic exclusive-or (XOR) parity information) associated with the encoded set of data units. In some examples, the encodermay additionally encode the parity information.

425 410 415 445 440 445 440 415 410 412 415 412 440 412 440 412 412 410 425 410 425 410 440 412 In some cases, such as if the decoderdid not correct an error in the set of data units, the memory controllermay transmit the parity informationto the memory device, and may store the parity informationin a latch of the memory device. In such cases, the memory controllermay not transmit data unitsto the memory device. Additionally or alternatively, if the decoder generated the corrected data unit, the memory controllermay optionally transmit the encoded corrected data unitto the memory device. Upon receiving the corrected data unit, the memory devicemay store the corrected data unitin a latch, such as by overwriting the corrected data unitto the latch which held the data unitin which the decodercorrected an error. In such cases, latches storing data unitsin which the decoderdid not correct an error may not be overwritten (e.g., the latches may retain their respective data units). Alternatively, the memory devicemay store the corrected data unitin a separate latch.

415 410 412 412 445 440 450 410 The memory controllermay transmit a command (e.g., a QLC program command) to write the data units, including data units which have been corrected (e.g., the corrected data unit, an encoded representation of the corrected data unit), and the parity informationfrom the set of latches of the memory deviceto the destination set of memory cells. In some cases, the command may include an indication of respective addresses of latches from which to transfer the encoded representation of the set of data unitsto the destination set of memory cells.

405 410 455 445 405 445 410 450 415 410 405 415 445 410 445 412 440 410 445 450 450 410 In some examples, the source set of memory cellsmay be associated with (e.g., may be coupled with) a weak word line. Is such cases, the data unitsmay include a data unit comprising parity information (e.g., parity information generated as part of an earlier data transfer operation using the parity generator). Accordingly, the data unit comprising parity information may be overwritten (e.g., replaced) with the parity information. Additionally or alternatively, if the source set of memory cellsis not associated with a weak word line, then the parity informationmay added to the set of data units. As an illustrative example, if the destination set of memory cells(e.g., pages associated with a weak word line) has a capacity of 16 data units, the memory controllermay read 15 data unitsfrom the source set of memory cells(e.g., from a same word line, from more than one word line). The memory controllermay generate the parity informationusing the 15 data units, and may transmit the parity information, as well as corrected data units, if present, to the memory deviceto write the received data units, as well as uncorrected data unitsstored in one or more latches, to the destination set of memory cells. Accordingly, the party informationmay use a fraction of the capacity of the destination set of memory cells(e.g., 1/16 of the capacity of the destination set of memory cells). Although an example of 15 data unitswas used, those skilled in the art may appreciated that other quantities are possible.

440 410 445 450 440 410 445 450 440 410 445 450 3 FIG. Upon receiving the command, the memory devicemay store the set of data unitsand the parity informationto one or more planes on the destination set of memory cells. In some cases, the memory devicemay store the set of data unitsand the parity informationacross multiple planes of the destination set of memory cells, as described with reference to. Additionally or alternatively, the memory devicemay store the set of data unitsand the parity informationacross a single plane of the destination set of memory cells.

5 FIG. 1 4 FIGS.through 500 520 520 520 520 525 530 535 540 545 550 555 shows a block diagramof a managed memory system controllerthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The managed memory system controllermay be an example of aspects of a managed memory system controller as described with reference to. The managed memory system controller, or various components thereof, may be an example of means for performing various aspects of techniques for improved data transfer as described herein. For example, the managed memory system controllermay include a reception component, a decoding component, an encoding component, a parity generation component, a transmission component, a command transmission component, a buffering component, or any combination thereof. Each of these components may communicate, directly or indirectly, with one another (e.g., via one or more buses).

525 530 535 540 545 550 The reception componentmay be configured as or otherwise support a means for receiving, at a controller, a set of encoded data units from a first set of memory cells of a memory device. The decoding componentmay be configured as or otherwise support a means for performing, at the controller, respective decoding operations on the set of encoded data units to obtain a corresponding set of data units and respective error correction information for the set of encoded data units. The encoding componentmay be configured as or otherwise support a means for encoding a first subset of the set of data units based at least in part on the respective error correction information for the first subset of the set of data units to obtain one or more reencoded data units. The parity generation componentmay be configured as or otherwise support a means for generating a parity unit associated with encoded representations of the set of data units based at least in part on performing the respective decoding operations. The transmission componentmay be configured as or otherwise support a means for transmitting the one or more reencoded data units and the parity unit to the memory device. The command transmission componentmay be configured as or otherwise support a means for transmitting a command to the memory device to write the one or more reencoded data units, a second subset of the set of data units, and the parity unit to a second set of memory cells of the memory device, where the second subset of the set of data units is exclusive of the first subset of the set of data units.

545 In some examples, to support transmitting the one or more reencoded data units and the parity unit, the transmission componentmay be configured as or otherwise support a means for suppressing transmitting the second subset of the set of data units to the memory device.

In some examples, the command includes a latch address associated with a subset of a set of latches of the memory device, and the subset of the set of latches corresponds to the first subset of the set of data units.

555 In some examples, the buffering componentmay be configured as or otherwise support a means for storing, based at least in part on performing the respective decoding operations, the set of data units in a buffer of the controller, where generating the parity unit is based at least in part on the storing.

525 530 540 545 550 In some examples, the reception componentmay be configured as or otherwise support a means for receiving, at the controller, a second set of encoded data units from a third set of memory cells of the memory device. In some examples, the decoding componentmay be configured as or otherwise support a means for performing, at the controller, respective decoding operations on the second set of encoded data units to obtain a corresponding second set of data units. In some examples, the parity generation componentmay be configured as or otherwise support a means for generating a second parity unit associated with the second set of data units based at least in part on performing the respective decoding operations. In some examples, the transmission componentmay be configured as or otherwise support a means for transmitting the parity unit to the memory device. In some examples, the command transmission componentmay be configured as or otherwise support a means for transmitting a second command to the memory device to write the second set of encoded data units and the panty unit to a fourth set of memory cells of the memory device.

In some examples, a first data unit of the set of data units is associated with a first plane of the first set of memory cells and a second data unit of the set of data units is associated with a second plane of the first set of memory cells different than the first plane.

550 In some examples, the command transmission componentmay be configured as or otherwise support a means for transmitting, to the memory device and as part of a memory management operation to transfer the set of encoded data units from the first set of memory cells to the second set of memory cells, a second command to retrieve the set of encoded data units, where receiving the set of encoded data units is based at least in part on transmitting the second command.

530 In some examples, the decoding componentmay be configured as or otherwise support a means for determining that the second set of memory cells is associated with a word line of a set of word lines of the memory device, where transmitting the parity unit is based at least in part on the determining.

In some examples, the set of word lines includes word lines of the memory device not satisfying a performance threshold.

In some examples, each encoded data unit of the set of encoded data units includes respective parity information associated with a first type of error correction and the parity unit is associated with a second type of error correction different than the first type.

In some examples, each memory cell of the first set of memory cells stores one bit of data, two bits of data, three bits of data, or four bits of data, and each memory cell of the second set of memory cells stores four bits of data.

6 FIG. 1 5 FIGS.through 600 600 600 shows a flowchart illustrating a methodthat supports techniques for improved data transfer in accordance with examples as disclosed herein. The operations of methodmay be implemented by a managed memory system controller or its components as described herein. For example, the operations of methodmay be performed by a managed memory system controller as described with reference to. In some examples, a managed memory system controller may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the managed memory system controller may perform aspects of the described functions using special-purpose hardware.

605 605 605 525 5 FIG. At, the method may include receiving, at a controller, a set of encoded data units from a first set of memory cells of a memory device. The operations ofmay be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations ofmay be performed by a reception componentas described with reference to.

610 610 610 530 5 FIG. At, the method may include performing, at the controller, respective decoding operations on the set of encoded data units to obtain a corresponding set of data units and respective error correction information for the set of encoded data units. The operations ofmay be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations ofmay be performed by a decoding componentas described with reference to.

615 615 615 540 5 FIG. At, the method may include generating a parity unit associated with encoded representations of the set of data units based at least in part on performing the respective decoding operations. The operations ofmay be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations ofmay be performed by a parity generation componentas described with reference to.

620 620 620 545 5 FIG. At, the method may include transmitting the parity unit to the memory device. The operations ofmay be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations ofmay be performed by a transmission componentas described with reference to.

625 625 625 550 5 FIG. At, the method may include transmitting a command to the memory device to write a second subset of the set of data units and the parity unit to a second set of memory cells of the memory device. The operations ofmay be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations ofmay be performed by a command transmission componentas described with reference to.

600 Aspect 1: A method, apparatus, or non-transitory computer-readable medium including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving, at a controller, a set of encoded data units from a first set of memory cells of a memory device, performing, at the controller, respective decoding operations on the set of encoded data units to obtain a corresponding set of data units and respective error correction information for the set of encoded data units; generating a parity unit associated with encoded representations of the set of data units based at least in part on performing the respective decoding operations, transmitting the parity unit to the memory device; and transmitting a command to the memory device to write a second subset of the set of data units and the parity unit to a second set of memory cells of the memory device. Aspect 2: The method, apparatus, or non-transitory computer-readable medium of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for encoding a second subset of the set of data units based at least in part on the respective error correction information for the second subset of the set of data units to obtain one or more reencoded data units and transmitting the one or more reencoded data units to the memory device, where the command is further to write the one or more reencoded data units to the second set of memory cells of the memory device, where the first subset of the data units is exclusive of the second subset of the set of data units. Aspect 3: The method, apparatus, or non-transitory computer-readable medium of aspect 1 through 2, where transmitting the one or more reencoded data units and the parity unit includes operations, features, circuitry, logic, means, or instructions, or any combination thereof for suppressing transmitting the second subset of the set of data units to the memory device. Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 3, where the command includes a latch address associated with a subset of a set of latches of the memory device, and the subset of the set of latches corresponds to the first subset of the set of data units. Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for storing, based at least in part on performing the respective decoding operations, the set of data units in a buffer of the controller, where generating the parity unit is based at least in part on the storing. Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for receiving, at the controller, a second set of encoded data units from a third set of memory cells of the memory device; performing, at the controller, respective decoding operations on the second set of encoded data units to obtain a corresponding second set of data units; generating a second parity unit associated with the second set of data units based at least in part on performing the respective decoding operations: transmitting the parity unit to the memory device; and transmitting a second command to the memory device to write the second set of encoded data units and the panty unit to a fourth set of memory cells of the memory device. Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 6, where a first data unit of the set of data units is associated with a first plane of the first set of memory cells and a second data unit of the set of data units is associated with a second plane of the first set of memory cells different than the first plane. Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 7, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for transmitting, to the memory device and as part of a memory management operation to transfer the set of encoded data units from the first set of memory cells to the second set of memory cells, a second command to retrieve the set of encoded data units, where receiving the set of encoded data units is based at least in part on transmitting the second command. Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for determining that the second set of memory cells is associated with a word line of a set of word lines of the memory device, where transmitting the parity unit is based at least in part on the determining. Aspect 10: The method, apparatus, or non-transitory computer-readable medium of aspect 9, where the set of word lines includes word lines of the memory device not satisfying a performance threshold. Aspect 11: The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 10, where each encoded data unit of the set of encoded data units includes respective parity information associated with a first type of error correction and the parity unit is associated with a second type of error correction different than the first type. Aspect 12. The method, apparatus, or non-transitory computer-readable medium of any of aspects 1 through 11, where each memory cell of the first set of memory cells stores one bit of data, two bits of data, three bits of data, or four bits of data, and each memory cell of the second set of memory cells stores four bits of data. In some examples, an apparatus as described herein may perform a method or methods, such as the method. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof for performing the following aspects of the present disclosure:

It should be noted that the described techniques include possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between the components. Components are considered in electronic communication with (or in conductive contact with or connected with or coupled with) one another if there is any conductive path between the components that can, at any time, support the flow of signals between the components. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected with or coupled with) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between the components or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a time, for example, using one or more intermediate components such as switches or transistors.

The term “coupling” refers to a condition of moving from an open-circuit relationship between components in which signals are not presently capable of being communicated between the components over a conductive path to a closed-circuit relationship between components in which signals are capable of being communicated between components over the conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components over a conductive path that previously did not permit signals to flow.

The term “isolated” refers to a relationship between components in which signals are not presently capable of flowing between the components. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch that is positioned between the components are isolated from each other if the switch is open. If a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously permitted signals to flow.

The terms “if,” “when,” “based on,” or “based at least in part on” may be used interchangeably. In some examples, if the terms “if,” “when,” “based on,” or “based at least in part on” are used to describe a conditional action, a conditional process, or connection between portions of a process, the terms may be interchangeable.

The term “in response to” may refer to one condition or action occurring at least partially, if not fully, as a result of a previous condition or action. For example, a first condition or action may be performed and second condition or action may at least partially occur as a result of the previous condition or action occurring (whether directly after or after one or more other intermediate conditions or actions occurring after the first condition or action).

Additionally, the terms “directly in response to” or “in direct response to” may refer to one condition or action occurring as a direct result of a previous condition or action. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring independent of whether other conditions or actions occur. In some examples, a first condition or action may be performed and second condition or action may occur directly as a result of the previous condition or action occurring, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action or a limited quantity of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed “based on,” “based at least in part on,” or “in response to” some other step, action, event, or condition may additionally, or alternatively (e.g., in an alternative example), be performed “in direct response to” or “directly in response to” such other condition or action unless otherwise specified.

The devices discussed herein, including a memory array, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate, or sub-regions of the substrate, may be controlled through doping using various chemical species including, but not limited to, phosphorous, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion-implantation, or by any other doping means.

A switching component or a transistor discussed herein may represent a field-effect transistor (FET) and comprise a three terminal device including a source, drain, and gate. The terminals may be connected to other electronic elements through conductive materials. e.g., metals. The source and drain may be conductive and may comprise a heavily-doped, e.g., degenerate, semiconductor region. The source and drain may be separated by a lightly-doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be “on” or “activated” if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor may be “off” or “deactivated” if a voltage less than the transistor's threshold voltage is applied to the transistor gate.

The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that may be implemented or that are within the scope of the claims. The term “exemplary” used herein means “serving as an example, instance, or illustration” and not “preferred” or “advantageous over other examples.” The detailed description includes specific details to provide an understanding of the described techniques. These techniques, however, may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a hyphen and a second label that distinguishes among the similar components. If just the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over, as one or more instructions or code, a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of” or “one or more of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

The description herein is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.