Fault-attack analysis device and method

This application claims priority of TW Patent Application No. 111150794 filed on Dec. 30, 2022, the entirety of which is incorporated by reference herein.

The invention generally relates to fault-attack analysis technology, and more particularly, to a fault-attack analysis technology in which binary field addition is applied to encoding and decoding.

In fault-attack analysis methods, a fault may be added into the encryption and decryption system, and then differential correlation between multiple right calculations and wrong calculations will be analyzed. Then, according to the features of the encryption and decryption algorithms that are used, an equation for differential correlation is derived.

Therefore, in order to reduce the ability of an attacker to obtain data that has been encrypted and decrypted by the encryption and decryption system by performing a fault-attack, a fault-attack analysis device which can prevent the fault-attack effectively and easily is worthy of discussion.

A fault-attack analysis device and method are provided to overcome the problems mentioned above.

An embodiment of the invention provides a fault-attack analysis device. The fault-attack analysis device includes a controller, an encryption and decryption circuit, a first encoder, a first decoder, a second encoder, a second decoder, a comparison circuit. The controller may generate a control signal. The encryption and decryption circuit is coupled to the controller, and performs a normal round calculation and a redundant round calculation based on the control signal. The first encoder is coupled to the encryption and decryption circuit and performs a first encoding operation on the first output result corresponding to the normal round calculation from the encryption and decryption circuit to generate a first encoding result. The first decoder is coupled to the encryption and decryption circuit, and performs a first decoding operation on the first encoding result to generate a first decoding result. The second encoder is coupled to the encryption and decryption circuit, and performs a second encoding operation on the second output result corresponding to the redundant round calculation from the encryption and decryption circuit to generate a second encoding result. The second decoder is coupled to the encryption and decryption circuit, and performs a second decoding operation on the second encoding result to generate a second decoding result, wherein the second encoding operation and the second decoding operation are based on binary field addition. The comparison circuit is coupled to the first decoder and the second decoder, and compares the first decoding result and the second decoding result to perform a fault-attack analysis.

In an embodiment, the fault-attack analysis device further includes a first storage circuit and a second storage circuit. The first storage circuit is coupled to the first encoder and the first decoder, and stores calculation result of each normal round of the normal round calculation. The second storage circuit is coupled to the second encoder and the second decoder, and stores calculation result of each redundant round of the redundant round calculation.

In an embodiment, the encryption and decryption circuit further includes a first encryption and decryption circuit. The first encryption and decryption circuit is coupled to the first encoder, the first decoder, the second encoder, and the second decoder. The first encryption and decryption circuit performs the normal round calculation based on the control signal to generate the first output result, and performs the redundant round calculation based on the control signal to generate the second output result.

In an embodiment, the encryption and decryption circuit further includes a first encryption and decryption circuit and a second encryption and decryption circuit. The first encryption and decryption circuit is coupled to the first encoder and the first decoder, and performs the normal round calculation based on the control signal to generate the first output result. The second encryption and decryption circuit is coupled to the second encoder and the second decoder, and performs the redundant round calculation based on the control signal to generate the second output result.

In an embodiment, the first encoding operation and the first decoding operation are different from the second encoding operation and the second decoding operation.

In an embodiment, in the first encoding operation, no encoding operation is performed and in the first decoding operation, no decoding operation is performed.

In an embodiment, the encryption and decryption circuit may use an Advanced Encryption Standard (AES) algorithm to perform the normal round calculation and the redundant round calculation. The second encoder may divide each output data of the second output result into a plurality of blocks, the second encoder may configure the blocks corresponding to each output data to different groups to generate a plurality of first variables, and the second encoder may perform the second encoding operation on the first variables to generate the second encoding result. The number of first variables is the same as the number of output data. The second decoder may perform the second decoding operation on the second encoding result to generate a plurality of second variables. The decoder may divide the second variables into a plurality of blocks. The second decoder may configure the blocks corresponding to each second variable to different groups to generate the second decoding result. The number of second variables is the same as the number of first variables.

In an embodiment, the second encoder comprises a plurality of first Exclusive-OR gates and the second decoder comprises a plurality of second Exclusive-OR gates, wherein the number of first Exclusive-OR gates is the same as the number of second Exclusive-OR gates.

An embodiment of the invention provides a fault-attack analysis method. The fault-attack analysis method is applied to a fault-attack analysis device. The fault-attack analysis method comprises the following steps. The controller of the fault-attack analysis device may generate a control signal. The encryption and decryption circuit of the fault-attack analysis device may perform a normal round calculation and a redundant round calculation based on the control signal. The first encoder of the fault-attack analysis device may perform a first encoding operation on the first output result corresponding to the normal round calculation from the encryption and decryption circuit to generate a first encoding result. The first decoder of the fault-attack analysis device may perform a first decoding operation on the first encoding result to generate a first decoding result. The second encoder of the fault-attack analysis device may perform a second encoding operation on the second output result corresponding to the redundant round calculation from the encryption and decryption circuit to generate a second encoding result. The second decoder of the fault-attack analysis device may perform a second decoding operation on the second encoding result to generate a second decoding result. The second encoding operation and the second decoding operation are based on binary field addition. The comparison circuit of the fault-attack analysis device may compare the first decoding result and the second decoding result to perform a fault-attack analysis.

Other aspects and features of the invention will become apparent to those with ordinary skill in the art upon review of the following descriptions of specific embodiments of a fault-attack analysis device and method.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

1 FIG. 1 FIG. 1 FIG. 1 FIG. 100 100 110 120 130 140 151 152 160 171 172 180 190 100 is a block diagram of a d fault-attack analysis deviceaccording to an embodiment of the invention. As shown in, the fault-attack analysis devicemay comprise a bus circuit (or bus interface), a controller, an input/output buffer, an encryption and decryption circuit, a first encoder, a first decoder, a first storage circuit, a second encoder, a second decoder, a second storage circuitand comparison circuit. It should be noted thatpresents a simplified block diagram in which only the elements relevant to the invention are shown. However, the invention should not be limited to what is shown in. The fault-attack analysis devicemay also comprise other elements.

100 According to the embodiments of the invention, the fault-attack analysis devicemay be applied to integrated circuit or microcontroller (MCU), but the invention should not be limited thereto.

110 100 1000 120 120 1000 110 130 140 130 110 140 130 1000 According to the embodiments of the invention, the bus circuitmay obtain the command from the external circuit of the fault-attack analysis devicethrough the bus, transmit the command to the controller, and then transmit the response from the controllerto the bus. In addition, the bus circuitmay transmit the data which needs to be encrypted or decrypted to the input/output buffer. Then, the data which needs to be encrypted or decrypted may be transmitted to the encryption and decryption circuitthrough the input/output buffer. The bus circuitmay receive the data which has been encrypted or decrypted by the encryption and decryption circuitfrom the input/output buffer, and transmit the data which has been encrypted or decrypted to the bus.

120 140 100 140 130 140 140 130 According to the embodiments of the invention, the controllermay transmit the control signal CTRL to the encryption and decryption circuitbased on the command from the bus circuitto encrypt or decrypt data. The encryption and decryption circuitmay perform an encryption operation or a decryption operation on the data from the input/output bufferbased on the control signal CTRL. When the encryption and decryption circuitperforms an encryption operation or a decryption operation on the data, the encryption and decryption circuitmay perform a normal round calculation and a redundant round calculation on the data from the input/output buffer.

140 140 140 1 FIG. According to embodiments of the invention, the encryption and decryption circuitmay perform the normal round calculation and the redundant round calculation based on an encryption and decryption algorithm (e.g., Advanced Encryption Standard (AES)). In the normal round calculation and the redundant round calculation, the encryption and decryption circuitmay perform multiple rounds of an encryption and decryption algorithm. In the embodiment of, the encryption and decryption circuitperforms a normal round calculation first, and then it performs the redundant round calculation. In the normal round calculation and the redundant round calculation, the calculation result of the prior round may be used as the input data in the next round. The details are illustrated below.

160 180 160 180 According to embodiments of the invention, the first storage circuitand the second storage circuitmay be memories or registers. The first storage circuitmay store the calculation result (or calculation state) of each normal round of the normal round calculation, and the second storage circuitmay store the calculation result (or calculation state) of each redundant round of the redundant round calculation.

140 130 151 160 152 160 140 152 190 In first round of normal round calculation, the encryption and decryption circuitmay perform the encryption and decryption algorithm (e.g., AES algorithm) on the initial data from the input/output bufferto generate a first normal round calculation result. Then, the first encodermay perform an encoding operation on the first normal round calculation result, and store the encoded first normal round calculation result in the first storage circuit. Then, the first decodermay perform the decoding operation on the first normal round calculation result stored in the first storage circuit, and transmit the decoded first normal round calculation result to the encryption and decryption circuitto be the input data of the second round of normal round calculation. Accordingly, when the last round of the normal round calculation has been performed, the first decodermay transmit the decoded last normal round calculation result to the comparison circuit.

140 130 171 180 172 180 140 172 190 Similar to normal round calculation, in first round of redundant round calculation, the encryption and decryption circuitmay perform the encryption and decryption algorithm (e.g., AES algorithm) on the initial data from the input/output bufferto generate a first redundant round calculation result. Then, the second encodermay perform an encoding operation on the first redundant round calculation result, and store the encoded first redundant round calculation result in the second storage circuit. Then, the second decodermay perform the decoding operation on the first redundant round calculation result stored in the second storage circuit, and transmit the decoded first redundant round calculation result to the encryption and decryption circuitto be the input data of the second round of redundant round calculation. Accordingly, when the last round of redundant round calculation has been performed, the second decodermay transmit the decoded last redundant round calculation result to the comparison circuit.

190 152 172 190 When the comparison circuitreceives the decoded last normal round calculation result from the first decoderand the decoded last redundant round calculation result from the second decoder, the comparison circuitmay compare the decoded last normal round calculation result to the decoded last redundant round calculation result to determine whether the decoded last normal round calculation result and the decoded last redundant round calculation result are the same.

190 120 120 140 120 130 140 1000 When the decoded last normal round calculation result and the decoded last redundant round calculation result are the same, the comparison circuitmay transmit a comparison result EQUAL (e.g., the value of comparison result EQUAL is 1) to the controllerto tell the controllerthat no fault occurs in the encryption/decryption calculation of the encryption and decryption circuit(i.e., the encryption/decryption calculation is not attacked). Therefore, the controllermay indicate the input/output bufferto transmit the data encrypted or decrypted by the encryption and decryption circuitto the bus.

190 120 120 140 120 160 180 140 When the decoded last normal round calculation result and the decoded last redundant round calculation result are not the same, the comparison circuitmay transmit a comparison result EQUAL (e.g., the value of comparison result EQUAL is 0) to the controllerto tell the controllerthat the fault occurs in the encryption/decryption calculation of the encryption and decryption circuit(i.e., the encryption/decryption calculation may be attacked). The controllermay cancel the encrypted or decrypted data stored in the first storage deviceand the second storage device, and indicate the encryption and decryption circuitto perform the normal round calculation and the redundant round calculation again.

2 FIG. 2 FIG. 2 FIG. 2 FIG. 200 200 210 220 230 240 250 251 252 260 271 272 280 290 200 is a block diagram of a d fault-attack analysis deviceaccording to another embodiment of the invention. As shown in, the fault-attack analysis devicemay comprise a bus circuit (or bus interface), a controller, an input/output buffer, a first encryption and decryption circuit, a second encryption and decryption circuit, a first encoder, a first decoder, a first storage circuit, a second encoder, a second decoder, a second storage circuitand a comparison circuit. It should be noted thatpresents a simplified block diagram in which only the elements relevant to the invention are shown. However, the invention should not be limited to what is shown in. The fault-attack analysis devicemay also comprise other elements.

100 200 240 250 240 251 252 250 271 272 240 230 250 230 Comparing to the fault-attack analysis device, the fault-attack analysis deviceis configured the first encryption and decryption circuitand the second encryption and decryption circuit. The first encryption and decryption circuitmay be coupled to the first encoderand first decoder. The second encryption and decryption circuitmay be coupled to the first encoderand first decoder. The first encryption and decryption circuitmay be configured to perform a normal round calculation on the data from the input/output buffer. The second encryption and decryption circuitmay be configured to perform a redundant round calculation on the data from the input/output buffer. That is, the normal round calculation and the redundant round calculation can be performed at the same time.

200 100 The operations of other elements of the fault-attack analysis deviceare similar to the fault-attack analysis device, details will not be illustrated again.

151 251 171 271 152 252 172 272 151 152 151 152 140 171 172 3 FIG. According to the embodiments of the invention, the first encoder(or first encoder) and second encoder(or second encoder) may perform different encoding operations, and the first decoder(or first decoder) and second decoder(or second decoder) may perform different encoding operations. In an embodiment, the first encoderand the first decodermay not perform any encoding or decoding operations. That is, in the embodiment, in normal round calculation, the first encoderand the first decodermay not perform an encoding operation or a decoding operation on the calculation result output by the encryption and decryption circuit. According to an embodiment of the invention, the encoding operation and decoding operation performed by the second encoderand the second decodermay be the binary field addition-based encoding operation and decoding operation.is used as an example for illustration below.

3 FIG. 3 FIG. is a schematic diagram illustrating binary field addition-based encoding operation and decoding operation according to an embodiment of the invention. As shown in, after the encoder obtains 4 bytes output data A[7:0], B[7:0], C[7:0] and D[7:0] from the encryption and decryption circuit (i.e., each output data is 1 byte), the encoder may equally divide each output data A[7:0], B[7:0], C[7:0] and D[7:0] into 2-bits block (i.e., output data A[7:0] is divided into A[1:0], A[3:2], A[5:4] and A[7:6], output data B[7:0] is divided into B[1:0], B[3:2], B[5:4] and B[7:6], output data C[7:0] is divided into C[1:0], C[3:2], C[5:4] and C[7:6], and output data D[7:0] is divided into D[1:0], D[3:2], D[5:4] and D[7:6]). Then, the encoder may configure the blocks of each output data A[7:0], B[7:0], C[7:0] and D[7:0] to different groups to generate first variables X0, X1, X2 and X3. The first variables X0, X1, X2 and X3 may be shown below:

Then, the encoder may select three variables from the first variables X0, X1, X2 and X3 to perform a binary field addition calculation (i.e., Exclusive-OR calculation) to generate encoding results O0, O1, O2 and O3. The encoder may comprise four Exclusive-OR gates to respectively perform binary field addition calculations (i.e., Exclusive-OR calculations) on different selection results to generate encoding results O0, O1, O2 and O3. The encoding results O0, O1, O2 and O3 are shown below:

Then, the decoder may obtain the encoding results O0, O1, O2 and O3 from the storage circuit, and select three encoding results from the encoding results O0, O1, O2 and O3 to perform the binary field addition calculation (i.e., Exclusive-OR calculation) to generate second variables Y0, Y1, Y2 and Y3. The decoder may comprise four Exclusive-OR gates to respectively perform binary field addition calculations (i.e., Exclusive-OR calculation) on different selection results to generate second variables Y0, Y1, Y2 and Y3. The operations of encoder and decoder may be corresponded each other to make the second variables Y0, Y1, Y2 and Y3 be corresponded to the first variables X0, X1, X2 and X3 respectively. The second variables Y0, Y1, Y2 and Y3 are shown below

The decoder may substitute the encoding results O0, O1, O2 and O3 into the second variables Y0, Y1, Y2 and Y3 as follow:

Therefore, the decoder may generate the decoding results A, B, C and D according to the second variables Y0, Y1, Y2 and Y3. The decoding results A, B, C and D are shown below:

4 FIG. 4 FIG. is a schematic diagram illustrating fault according to an embodiment of the invention. As shown in, it is assumed the encoding result O1 is attacked, the second variables Y0, Y1, Y2 and Y3 may be affected by the attack. When the second variables Y0, Y1, Y2 and Y3 which are affected by the attack are decoded, the decoding results A[1:0], A[3:2], A[5:4], B[1:0], B[3:2], B[5:4], C[1:0], C[3:2], C[5:4] D[1:0], D[3:2] and D[5:4] may affected by the attack. That is, when 1 byte decoding results of 4 bytes decoding results are attacked, 24 bits decoding result will be affected. Therefore, in the invention, the binary field addition calculation (i.e., Exclusive-OR calculation) is applied to perform an encoding operation and a decoding operation, the 16-bit security requirement (i.e., when 1 byte is attacked, at least 16 bits are affected) of the current technology can be met to prevent the single fault attack of the attacker.

5 FIG. 5 FIG. 100 200 510 is a flow chart illustrating a fault-attack analysis method according to an embodiment of the invention. The fault-attack analysis method can be applied to the fault-attack analysis deviceand the fault-attack analysis device. As shown in, in step S, a controller of the fault-attack analysis device may generate a control signal.

520 In step S, an encryption and decryption circuit of the fault-attack analysis device may perform a normal round calculation and a redundant round calculation based on the control signal. In the fault-attack analysis method, the encryption and decryption circuit may use an Advanced Encryption Standard (AES) algorithm to perform the normal round calculation and the redundant round calculation.

530 In step S, a first encoder of the fault-attack analysis device may perform a first encoding operation on the first output result corresponding to the normal round calculation from the encryption and decryption circuit to generate a first encoding result.

540 In step S, a first decoder of the fault-attack analysis device may perform a first decoding operation on the first encoding result to generate a first decoding result.

550 In step S, a second encoder of the fault-attack analysis device may perform a second encoding operation on the second output result corresponding to the redundant round calculation from the encryption and decryption circuit to generate a second encoding result.

560 In step S, a second decoder of the fault-attack analysis device may perform a second decoding operation on the second encoding result to generate a second decoding result. In the fault-attack analysis method, the second encoding operation and the second decoding operation may be based on binary field addition.

570 In step S, a comparison circuit of the fault-attack analysis device may compare the first decoding result (i.e., the decoded last normal round calculation result) and the second decoding result (i.e., the decoded last redundant round calculation result) to perform the fault-attack analysis.

According to an embodiment of the invention, in the fault-attack analysis method, a first storage circuit of the fault-attack analysis device may store the calculation result of each normal round of the normal round calculation, and a second storage circuit of the fault-attack analysis device may store the calculation result of each redundant round of the redundant round calculation.

According to an embodiment of the invention, in the fault-attack analysis method, a first encryption and decryption circuit of the encryption and decryption circuit (i.e., the encryption and decryption circuit may comprise only one encryption and decryption circuit) may perform the normal round calculation based on the control signal to generate the first output result, and perform the redundant round calculation based on the control signal to generate the second output result.

According to an embodiment of the invention, in the fault-attack analysis method, a first encryption and decryption circuit of the encryption and decryption circuit may perform the normal round calculation based on the control signal to generate the first output result, and a second encryption and decryption circuit of the encryption and decryption circuit may perform the redundant round calculation based on the control signal to generate the second output result.

According to an embodiment of the invention, in the fault-attack analysis method, the second encoder may divide each output data of the second output result into a plurality of blocks, the second encoder may configure the blocks corresponding to each output data to different groups to generate a plurality of first variables, and the second encoder may perform the second encoding operation on the first variables to generate the second encoding result. The number of first variables is the same as the number of output data.

According to an embodiment of the invention, in the fault-attack analysis method, the second decoder may perform the second decoding operation on the second encoding result to generate a plurality of second variables, the decoder may divide the second variables into a plurality of blocks, and the second decoder may configure the blocks corresponding to each second variable to different groups to generate the second decoding result. The number of second variables is the same as the number of first variables.

According to the fault-attack analysis method provided in the invention, the design for the encoder or decoder of the fault-attack analysis device may use fewer elements (e.g., Exclusive-OR gate) to meet the security requirement. Therefore, the cost for the fault-attack analysis device will be saved. In addition, according to the fault-attack analysis method provided in the invention, the binary field addition is applied to the encoding operation and the decoding operation to reduce the encoding delay and decoding delay.

Use of ordinal terms such as “first”, “second”, “third”, etc., in the disclosure and claims is for description. It does not by itself connote any order or relationship.

The steps of the method described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (e.g., including executable instructions and related data) and other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a “processor”) such that the processor can read information (e.g., code) from and write information to the storage medium. A sample storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in user equipment. Alternatively, the processor and the storage medium may reside as discrete components in user equipment. Moreover, in some aspects any suitable computer-program product may comprise a computer-readable medium comprising codes relating to one or more of the aspects of the disclosure. In some aspects a computer program product may comprise packaging materials.

The above paragraphs describe many aspects. Obviously, the teaching of the invention can be accomplished by many methods, and any specific configurations or functions in the disclosed embodiments only present a representative condition. Those who are skilled in this technology will understand that all of the disclosed aspects in the invention can be applied independently or be incorporated.

While the invention has been described by way of example and in terms of preferred embodiment, it should be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.