Light emitting device voltage setting method determining whether a black floating phenomenon has been observed

The present application claims priority to and the benefit of Korean Patent Application No. 10-2024-0078193, filed on Jun. 17, 2024, and Korean Patent Application No. 10-2024-0110241, filed on Aug. 19, 2024, in the Korean Intellectual Property Office, the entire disclosures of each of which are incorporated herein by reference.

Aspects of some embodiments of the present disclosure generally relate to an electronic device and a voltage setting method thereof.

With the development of information technologies, the importance of a display device which is a connection medium between a user and information increases. Accordingly, display devices such as a liquid crystal display device and an organic light emitting display device are increasingly used.

Such a display device displays an image while changing frames at high speed, thereby providing higher immersion to a user. Further, it is necessary to control heat generated in the display device by lowering power consumption.

The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art.

Aspects of some embodiments include an electronic device and a voltage setting method thereof, in which display quality can be relatively improved and power consumption can be relatively reduced.

According to some embodiments of the present disclosure, there is provided a voltage setting method of an electronic device, in which a plurality of sub-pixels are in a display device, and an anode initialization voltage applied to the plurality of sub-pixels is set, the voltage setting method including: setting a data voltage for displaying an image having a black grayscale to an a-th level in the plurality of sub-pixels; applying the anode initialization voltage having a first level; determining whether a black floating phenomenon has been observed; decreasing the anode initialization voltage by a second level when the black floating phenomenon is observed; applying the set anode initialization voltage; and writing a level of the set anode initialization voltage to the display device when it is determined that the black floating phenomenon has not been observed.

According to some embodiments, the set anode initialization voltage may be applied, and it may be again determined that the black floating phenomenon has been observed.

According to some embodiments, the voltage setting method may further include determining whether the anode initialization voltage has exceeded a predetermined minimum value.

According to some embodiments, the determining of whether the anode initialization voltage has exceeded the predetermined minimum value may be performed after the decreasing of the anode initialization voltage by the second level.

According to some embodiments, the applying of the set anode initialization voltage may be performed when it is determined that the anode initialization voltage has exceeded the predetermined minimum value.

According to some embodiments, the voltage setting method may further include setting the anode initialization voltage to a third level when it is determined that the anode initialization voltage has not exceeded the predetermined minimum value.

According to some embodiments, the voltage setting method may further include: applying the anode initialization voltage having the third level; and determining whether the black floating phenomenon has been observed as the anode initialization voltage having the third level is applied.

According to some embodiments, the voltage setting method may further include: when the black floating phenomenon is observed as the anode initialization voltage having the third level is applied, increasing a level of the data voltage for displaying the image having the black grayscale by a b-th level; and determining whether the black floating phenomenon has been observed as the data voltage increased by the b-th level is applied.

According to some embodiments, based on a determination that the black floating phenomenon has been observed as the data voltage increased by the b-th level is applied, the level of the data voltage for displaying the image having the black grayscale may be increased by the b-th level.

According to some embodiments, the voltage setting method may further include writing the level of the set data voltage for displaying the image having the black grayscale to the display device when it is determined that the black floating phenomenon has not been observed as the data voltage increased by the b-th level is applied.

According to some embodiments, in the writing of the level of the set data voltage for displaying the image having the black grayscale to the display device, the level of the anode initialization voltage may be written as the third level to the display device.

According to some embodiments, the voltage setting method may further include: when the black floating phenomenon is not observed as the anode initialization voltage having the third level is applied, decreasing the level of the data voltage for displaying the image having the black grayscale by a c-th level; and determining whether the black floating phenomenon has been observed as the data voltage decreased by the c-th level is applied.

According to some embodiments, based on a determination that the black floating phenomenon has not been observed as the data voltage decreased by the c-th level is applied, the level of the data voltage for displaying the image having the black grayscale may be decreased by the c-th level.

According to some embodiments, the voltage setting method may include: increasing the level of the data voltage for displaying the image having the black grayscale by the c-th level when it is determined that the black floating phenomenon has not been observed as the data voltage increased by the c-th level is applied; and writing the level of the data voltage for displaying the image having the black grayscale to the display device.

According to some embodiments, in the writing of the level of the data voltage for displaying the image having the black grayscale to the display device, the level of the anode initialization voltage may be written as the third level to the display device.

According to some embodiments, at least one of the plurality of sub-pixels may include: a sub-pixel circuit configured to generate a driving current; and a light emitting element connected to the sub-pixel circuit, the light emitting element having the driving current flowing therethrough. According to some embodiments, the sub-pixel circuit may include an initialization transistor configured to switch an electrical connection between the light emitting element and a power line to which the anode initialization voltage is applied.

According to some embodiments, the power line to which the anode initialization voltage is applied may be a fourth power line. According to some embodiments, the light emitting element may include: a first electrode connected to the initialization transistor; a second electrode connected to a second power line to which a second power voltage is applied; and a light emitting layer located between the first electrode and the second electrode. According to some embodiments, a voltage difference between the first level and the second power voltage may be lower than a threshold voltage of the light emitting element.

According to some embodiments, the display device may further include: a display panel having the plurality of sub-pixels located therein; a power supply circuit configured to supply the anode initialization voltage to the display panel; and a timing controller configured to control the power supply circuit. According to some embodiments, in the writing of the level of the set anode initialization voltage to the display device, the level of the anode initialization voltage may be written to a memory of the timing controller.

According to some embodiments, the level of the data voltage for displaying the image having the black grayscale may be further stored in the memory of the timing controller.

According to some embodiments of the present disclosure, an electronic device includes: a display panel having a plurality of sub-pixels located therein, the display panel, wherein an anode initialization voltage is applied to the plurality of sub-pixels; a data driving circuit configured to supply a data voltage to the plurality of sub-pixels; a power supply circuit configured to supply the anode initialization voltage to the display panel; and a timing controller configured to control the data driving circuit with reference to a memory, and control the anode initialization voltage output from the power supply circuit to have a predetermined level, wherein the predetermined level is set by: setting the data voltage for displaying an image having a black grayscale to an a-th level in the plurality of sub-pixels; applying the anode initialization voltage having a first level to the display panel; determining whether a black floating phenomenon has been observed; decreasing the anode initialization voltage by a first level when it is determined that the black floating phenomenon has been observed; applying the set anode initialization voltage; and writing a level of the set anode initialization voltage to the display device when it is determined that the black floating phenomenon has not been observed.

Hereinafter, aspects of some embodiments are described in more detail with reference to the accompanying drawings so that those skilled in the art may easily practice the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the disclosed embodiments described in the present specification.

A part irrelevant to the description will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be designated by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

In addition, the size and thickness of each component illustrated in the drawings are arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. Thicknesses of several portions and regions are exaggerated for clear expressions.

In description, the expression “equal” may mean “substantially equal.” That is, this may mean equality to a degree to which those skilled in the art can understand the equality. Other expressions may be expressions in which “substantially” is omitted.

It will be understood that, although the terms “first”, “second,” “a-th,” “b-th,” “c-th,” and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a “first” element discussed below could also be termed a “second” element without departing from the teachings of the present disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The terms “under,” “beneath,” “on,” “above,” and the like are used to describe a relationship between components illustrated in a drawing. The terms are relative and are described with reference to a direction indicated in the drawing.

Unless defined otherwise, it is to be understood that all the terms (including technical and scientific terms) used in the specification has the same meaning as those that are understood by those who skilled in the art. Further, the terms defined by the dictionary generally used should not be ideally or excessively formally defined unless clearly defined specifically.

It will be further understood that the terms “includes” and/or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence and/or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

1 FIG. is a system diagram of an electronic device DS according to some embodiments of the present disclosure.

1 FIG. 100 Referring to, the electronic device DS according to some embodiments of the present disclosure may include a display deviceand a host HOST.

100 110 120 130 140 150 160 The display deviceaccording to some embodiments of the present disclosure may include a display panel, a data driving circuit, a scan driving circuit, an emission driving circuit, a power supply circuit, a timing controller, and the like.

110 110 1 1 1 110 The display panelmay include a substrate SUB. A plurality of sub-pixels SP may be located in the display panel. The sub-pixels SP may be connected to a plurality of data lines DLto DLn (n is an integer of 2 or more), a plurality of scan lines SLto SLm (m is an integer of 2 or more), and a plurality of emission control lines EMLto EMLm. At least one power line configured to apply a power voltage to the plurality of sub-pixels SP may be located in the display panel.

110 The display panelmay include a display area DA in which the plurality of sub-pixels SP are located and a non-display area NDA located in a peripheral area of the display area DA (e.g., an edge of the display area DA).

110 110 110 The display panelmay be formed flat, but embodiments of the present disclosure are not limited thereto. For example, the display panelmay include curved portions formed at left and right ends thereof. A curved surface may have a constant curvature or have a changed curvature. Besides, the display panelmay be formed flexible to be curvable, warpable, bendable, foldable, and rollable.

1 110 2 1 110 2 2 2 110 The plurality of data lines DLto DLn may extend in one direction in the display panel. The one direction may be, for example, a second direction DR. The plurality of data lines DLto DLn may be located in the display panelwhile extending in the second direction DR(e.g., entirely in the second direction DR). The second direction DRmay be, for example, a direction crossing from an upper side to a lower side of the display panel, but embodiments of the present disclosure are not limited thereto.

1 110 1 1 110 1 1 2 1 110 The plurality of scan lines SLto SLm may extend in one direction in the display panel. The one direction may be, for example, a first direction DR. The plurality of scan lines SLto SLm may be located in the display panelwhile extending in the first direction (e.g., entirely in the first direction DR). The first direction DRmay be a direction different from the second direction DR, but embodiments of the present disclosure are not limited thereto. The first direction DRmay be, for example, a direction crossing from a left side to a right side of the display panel.

120 1 120 2 1 The data driving circuitmay be configured to supply a data voltage to the plurality of data lines DLto DLn. The data driving circuitmay generate a data voltage, based on second image data DATAand a data driving circuit control signal DCS, and output the generated data voltage to the plurality of data lines DLto DLn in synchronization with a timing. The data driving circuit control signal DCS may include, for example, a Source Start Pulse (SSP) signal, a Source Shift Clock (SCC) signal, a Source Output Enable (SOE) signal, and the like.

120 110 110 110 The data driving circuitmay be implemented as an integrated circuit (e.g., a Source Driver Integrated Circuit (SDIC) formed separately form the display panel, and be formed together with the display panelto be formed in at least a partial area on the non-display area NDA of the display panel.

130 1 The scan driving circuitmay be configured to output a scan signal to the plurality of scan lines SLto SLm in response to a scan driving circuit control signal SCS. The scan driving circuit control signal SCS may include a start signal indicating a start of a frame, a horizontal synchronization signal for outputting the scan signal in synchronization with a timing, and the like.

140 1 The emission driving circuitmay be configured to output an emission control signal to the plurality of emission control lines EMLto EMLm in response to an emission driving circuit control signal ECS. The emission driving circuit control signal ECS may include a start signal indicating a start of a frame, a horizontal synchronization signal for outputting the emission control signal in synchronization with a timing, and the like.

130 140 110 110 110 The scan driving circuitand/or the emission driving circuitmay be implemented as an integrated circuit (e.g., a Gate Driver Integrated Circuit (GDIC) formed separately form the display panel, and be formed together with the display panelto be formed in at least a partial area on the non-display area NDA of the display panel.

150 150 110 150 130 150 120 150 150 150 The power supply circuitmay be configured to output a constant voltage having a constant voltage level. The power supply circuitmay output a power voltage (e.g., a first power voltage ELVDD, a second power voltage ELVSS, a third power voltage VINT, a fourth power voltage VAINT, or the like) supplied to the display panel. The fourth power voltage VAINT may be referred to as an anode initialization voltage. According to some embodiments, the power supply circuitmay output a voltage (e.g., a gate high voltage, a gate low voltage, or the like) supplied to the scan driving circuit. According to some embodiments, the power supply circuitmay output a voltage (e.g., a gamma voltage, a reference voltage, or the like) supplied to the data driving circuit. The power supply circuitmay include, for example, a regulator (e.g., a Low Dropout (LDO) regulator, or the like). The power supply circuitmay be implemented as, for example, a Power Management Integrated Circuit (PMIC). The power supply circuitmay be configured to output a power voltage to power lines in response to a power supply circuit control signal VCS.

160 120 130 140 150 160 120 130 140 150 160 110 The timing controllermay be configured to control the data driving circuit, the scan driving circuit, the emission driving circuit, the power supply circuit, and the like. The timing controllermay generate and output the control signals DCS, SCS, ECS, and VCS for controlling the data driving circuit, the scan driving circuit, the emission driving circuit, and the power supply circuit, based on a control signal CS (e.g., a synchronization signal, a clock signal, a data enable signal, or the like) input through the host HST. According to some embodiments, the timing controllermay generate the synchronization signal, the data enable signal, and the like therein, based on the control signal CS input through the host HST (e.g., information on a driving frequency (or frame rate) of images displayed on the display panel).

160 1 1 160 1 2 160 120 160 The timing controllermay receive first image data DATAinput from the host HST, and align the input first image data DATAin a pixel row unit. The timing controllermay convert the input first image data DATAin synchronization with an interface (e.g., a set or predetermined interface) (e.g., a Low Voltage Differential Signaling (LVDS), a Display Port (DP), an embedded Display Port (eDP), or the like). The second image data DATAwhich the timing controlleroutputs to the data driving circuitmay be one converted inside the timing controlleraccording to the interface (e.g., the set or predetermined interface).

160 2 1 2 The timing controllermay generate the second image data DATA, based on the input first image data DATAand a sensing value. According to some embodiments, the second image data DATAmay be one obtained by compensating form a change in characteristic value of a sub-pixel included in a pixel (e.g., a change in characteristic value according to degradation of a transistor or a light emitting element in the sub-pixel, or the like).

160 100 160 100 160 According to some embodiments, the timing controllermay be located in a logic type or logic component or logic circuit in the display device. According to some embodiments, the timing controllermay be formed in a processor type in the display device. The timing controllermay include at least one memory MEM. A lookup table LUT may be stored in the memory MEM.

150 4 5 FIGS.and According to some embodiments, data determining a level of the fourth power voltage VAINT provided through the power supply circuitmay be included in the lookup table LUT stored in the memory MEM. The level of the fourth power voltage VAINT may be determined through a method of determining a voltage level, which will be described later with reference to.

4 5 FIGS.and According to some embodiments, data determining a level of a data voltage for displaying images having a black grayscale may be included in the lookup table LUT stored in the memory MEM. The level of the data voltage for display the image having the black grayscale may be determined through the method of determining the voltage level, which will be described later with reference to.

100 100 100 1 100 The host HST may include a set-top box, an Application Processor (AP), and the like. According to some embodiments, the host HST may be a component at the outside of the display device, which is not included in the display device. According to some embodiments, the host HST may be mounted in the display device. The first image data DATAand the control signal CS may be transmitted/received between the host HST and the display devicethrough an interface. The interface may be, for example, a Serial Programming Interface (SPI), an Inter Integrated Circuit (I2C), a Mobile Industry Processor Interface (MIPI), or the like. However, embodiments of the present disclosure are not limited thereto.

100 The electronic device DS according to some embodiments of the present disclosure may include the display deviceand the host HST.

1 FIG. 110 120 160 120 160 100 In, circuits supplying signals, voltages, and the like to the display panelare merely classified according to functions. For example, the data driving circuitand the timing controllermay be formed in one integrated circuit. The data driving circuitand the timing controllermay be ones classified in one integrated circuit according to functions in the display device.

100 The display deviceaccording to some embodiments of the present disclosure may be used as a display screen of not only portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, and an ultra-mobile PC, but also various products such as a television, a notebook computer, a monitor, an advertisement board, and an Internet of things (IoT) device.

2 FIG. 2 FIG. is an equivalent circuit diagram of a sub-pixel SP according to some embodiments of the present disclosure. Althoughillustrates various components in a sub-pixel SP according to some embodiments of the present disclosure, according to some embodiments, the sub-pixel SP may include additional components or fewer components without departing from the spirit and scope of embodiments according to the present disclosure.

2 FIG. Referring to, the sub-pixel SP according to some embodiments of the present disclosure may include a sub-pixel circuit SPC and a light emitting element LE.

The sub-pixel circuit SPC may be connected to an ith scan line SLi (hereinafter, abbreviated as a scan line SLi), an ith emission control line EMLi (hereinafter, abbreviated as an emission control line EMLi), and a jth data line DLj (hereinafter, abbreviated as a data line DLj).

2 FIG. 1 1 2 2 3 3 i i i i i i The scan line SLi may include two or more sub-scan lines. Referring to, the scan line SLi may include an ith first sub-scan line SCL(or abbreviated as a first sub-scan line SCL), an ith second sub-scan line SCL(or abbreviated as a second sub-scan line SCL), and an ith third sub-scan line SCL(or abbreviated as a third sub-scan line SCL).

1 7 The sub-pixel circuit SPC according to some embodiments of the present disclosure may include a plurality of switching elements. For example, the sub-pixel circuit SPC according to some embodiments of the present disclosure may include first to seventh transistors TRto TR. The sub-pixel circuit SPC according to some embodiments of the present disclosure may include at least one storage element. The storage element may be implemented as, for example, a capacitor. For example, the sub-pixel circuit SPC according to some embodiments of the present disclosure may include a storage capacitor Cstg. Hereinafter, for convenience of description, a case where the sub-pixel circuit SPC according to some embodiments of the present disclosure seven transistors and one capacitor is described as an example. However, embodiments of the present disclosure are not limited thereto.

1 1 1 3 2 1 1 1 1 The first transistor TRmay be configured to control a magnitude of a current (e.g., a driving current) supplied to the light emitting element LE. The first transistor TRmay include a gate electrode connected to a first node N, a first electrode connected to a third node N, and a second electrode connected to a second node N. A magnitude of a current (e.g., a drain current) flowing through the first transistor TRmay be determined according to a magnitude of a voltage applied to the first node N. The first electrode of the first transistor TRmay be any one (e.g., a drain electrode) of a source electrode and the drain electrode, and the second electrode may be the other (e.g., the source electrode) of the source electrode and the drain electrode. The first transistor TRmay be referred to as a driving transistor.

2 2 3 2 1 2 3 1 2 i i The second transistor TRmay be configured to write a data voltage Vdata to the sub-pixel circuit SPC. The second transistor TRmay be configured to switch an electrical connection between the data line DLj and the third node N. The second transistor TRmay include a gate electrode connected (e.g., electrically connected) to the first sub-scan line SCL. The second transistor TRmay electrically connect between the data line DLj and the third node Nin response to a first scan signal GW[i] (e.g., the first scan signal GW[i] having a turn-on level) applied to the first sub-scan line SCL. The second transistor TRmay be referred to as a scan transistor.

3 1 2 3 1 3 1 3 1 2 1 3 1 3 i i The third transistor TRmay be configured to switch an electrical connection between the first node Nand the second node N. The third transistor TRmay be configured to compensate for a change in characteristic value (e.g., threshold voltage) of the first transistor TR. The third transistor TRmay include a gate electrode connected to the first sub-scan line SCL. The third transistor TRmay electrically connect between the first node Nand the second node Nin response to the first scan signal GW[i] (e.g., the first scan signal GW[i] having the turn-on level) applied to the first sub-scan line SCL. When the third transistor TRis turned on, the first transistor TRmay be diode-connected. The third transistor TRmay be referred to as a compensation transistor.

4 1 3 4 2 4 1 3 2 4 3 1 4 i i The fourth transistor TRmay be configured to switch an electrical connection between the first node Nand a third power line PL. The fourth transistor TRmay include a gate electrode connected to the second sub-scan line SCL. The fourth transistor TRmay electrically connect between the first node Nand the third power line PLin response to a second scan signal GI[i] (e.g., the second scan signal GI[i] having a turn-on level) applied to the second sub-scan line SCL. When the fourth transistor TR, the third power voltage VINT applied to the third power line PLmay be applied to the first node N. The fourth transistor TRmay be referred to as a first initialization transistor.

5 1 3 5 5 1 3 5 1 3 5 The fifth transistor TRmay be configured to switch an electrical connection between a first power line PLand the third node N. The fifth transistor TRmay include a gate electrode connected to the emission control line EMLi. The fifth transistor TRmay electrically insulate between the first power line PLand the third node Nin response to an emission control signal EM[i] (e.g., the emission control signal EM[i] having a turn-off level) applied to the emission control line EMLi. When the fifth transistor TRis turned on, the first power voltage ELVDD applied to the first power line PLmay be applied to the third node N. The fifth transistor TRmay be referred to as a first emission control transistor.

6 2 4 6 6 2 4 6 2 4 6 The sixth transistor TRmay be configured to switch an electrical connection between the second node Nand a fourth node N. The sixth transistor TRmay include a gate electrode connected to the emission control line EMLi. The sixth transistor TRmay electrically insulate between the second node Nand the fourth node Nin response to the emission control signal EM[i] (e.g., the emission control signal EM[i] having the turn-off level) applied to the emission control line EMLi. When the sixth transistor TRis turned on, the second node Nand the fourth node Nmay be electrically connected to each other. The sixth transistor TRmay be referred to as a second emission control transistor.

7 4 4 7 3 7 4 4 3 7 4 4 7 i i The seventh transistor TRmay be configured to switch an electrical connection between the fourth node Nand a fourth power line PL. The seventh transistor TRmay include a gate electrode connected to the third sub-scan line SCL. The seventh transistor TRmay electrically connect between the fourth node Nand the fourth power line PLin response to a third scan signal GB[i] (e.g., the third scan signal GB[i] having a turn-on level) applied to the third sub-scan line SCL. When the seventh transistor TRis turned on, the fourth power voltage VAINT applied to the fourth power line PLmay be applied to the fourth node N. The seventh transistor TRmay be referred to as a second initialization transistor.

2 FIG. 1 7 1 7 Referring to, it is illustrated that each of the first to seventh transistor TRto TRis a transistor including a P-type semiconductor. However, embodiments according to the present disclosure are not limited thereto. For example, at least one of the first to seventh transistors TRto TRmay be implemented with a transistor including an N-type semiconductor.

2 FIG. 2 3 1 2 3 2 3 i Referring to, it is illustrated that the second transistor TRand the third transistor TRare connected to the same sub-scan line (e.g., the first sub-scan line SCL). However, embodiments according to the present disclosure are not limited thereto. For example, according to some embodiments in which the second transistor TRis implemented as a transistor including a P-type semiconductor and the third transistor TRis implemented as a transistor including an N-type semiconductor, the second transistor TRand the third transistor TRmay be connected to different sub-scan lines.

1 1 1 2 1 1 1 The storage capacitor Cstg may be configured to maintain the magnitude of the voltage applied to the first node N. The storage capacitor Cstg may include one electrode Econnected to the first node Nand the other electrode Econnected to the first power line PL. The storage capacitor Cstg may be configured to maintain a potential difference between the first node Nand the first power line PL.

4 2 1 2 2 The light emitting element LE may include a first electrode connected to the fourth node N, a second electrode connected to a second power line PL, and a light emitting layer located between the first electrode and the second electrode. The first electrode may be any one of an anode electrode and a cathode electrode, and the second electrode may be the other of the anode electrode and the cathode electrode. Hereinafter, for convenience of description, it is assumed and described that the first electrode is the anode electrode and the second electrode is the cathode electrode. The first electrode (e.g., the anode electrode) of the light emitting element LE may be connected (e.g., electrically connected) to the first power line PLthrough the sub-pixel circuit SPC. The second electrode (e.g., the cathode electrode) of the light emitting element LE may be connected to the second power line PL. The second power voltage ELVSS may be applied to the second power line PL.

In the equivalent circuit diagram, the light emitting element LE may include a capacitor component Cle. The capacitor component Cle may be formed by using the anode electrode of the light emitting element as one electrode, using the cathode electrode of the light emitting element as the other electrode, and using, as an insulating layer, the light emitting element located between the anode electrode and the cathode electrode.

7 4 When the seventh transistor TRis turned on, the fourth power voltage VAINT may be applied to the fourth node N. The level of the fourth power voltage VAINT may be equal to a level of the second power voltage ELVDD or be set within a range higher than the level of the second power voltage ELVDD.

Meanwhile, a charge corresponding to a potential difference between the fourth power voltage VAINT and the second power voltage ELVSS may be stored in the capacitor component Cle of the light emitting element LE. When a potential difference between both ends of the capacitor component Cle becomes highest within a range in which the potential difference does not exceed a threshold voltage of the light emitting element LE, the length of a period required when the light emitting element LE emits light may be shortened. Accordingly, this is helpful in rapidly changing frames in image reproduction. In addition, a problem in that an emission time of the light emitting element LE varies as the capacitance of the capacitor component Cle of the light emitting element LE varies according to external temperature is reduced or prevented, so that a problem in that a luminance is changed depending on temperature, a problem in that a color blurring phenomenon occurs, and the like can be relatively reduced.

Also, meanwhile, from the viewpoint of relatively reducing power consumption, it is advantageous that a data voltage Vdata having a level as low as possible is applied within a range in which the light emitting element LE does not emit light when the sub-pixel SP displays an image having a black grayscale (or grayscale 0).

Referring to this, because the fourth power voltage VAINT is continuously input to the sub-pixel circuit SPC not only when the image having the black grayscale is displayed but also when an image having various grayscales is displayed, it may be advantageous to increase the level of the fourth power voltage VAINT as high as possible so as to relatively improve display quality, as compared with a case where the level of a data voltage Vdata for displaying the image having the black grayscale is decreased.

110 1 FIG. 3 5 FIGS.to Accordingly, from the viewpoint of the display panel(see), there is required a method of setting the level of the fourth power voltage VAINT to be as high as possible and setting the level of the data voltage Vdata for displaying the image having the black grayscale to be as low as possible, based on the set fourth power voltage VAINT. In the embodiments of the present disclosure, a method of setting the fourth power voltage VAINT with a high level and the data voltage Vdata for displaying the image having the black grayscale with a low level will be described later with reference to.

3 FIG. 300 310 330 is a tableillustrating data obtained by experimenting while varying a level of a fourth power voltageand a level of a data voltagefor displaying an image having a black grayscale.

300 310 330 In the table, “VAINT” indicates the fourth power voltage, and “Vdata (0 Gray)” indicates the data voltagefor displaying the image having the black grayscale.

310 310 The level of the fourth power voltagemay be, for example, one obtained by considering the level of the second power voltage ELVSS as a ground voltage, and writing a voltage difference from the above-described second power voltage ELVSS as the level of the fourth power voltage.

3 FIG. 3 FIG. 1 FIG. 310 320 330 310 330 110 320 320 340 The experiment shown inwas performed by dividing the level of the fourth power voltageinto five classesand dividing the level of the data voltagefor displaying the image having the black grayscale into eighteen classes. For example, the experiment shown inwas performed by setting the level of the fourth power voltageto any one of 0 V (Volt), 0.15 V, 0.2 V, 0.25 V, and 0.3 V, and increasing the level of the data voltagefor displaying the image having the black grayscale from 4.8 V to 6.5 in a unit of 0.1 V. In addition, a number of samples in which a luminance of the display panel(see) became a luminance (e.g., a set or predetermined luminance) (e.g., 0.001 nit) or less was recorded. The number of samples is 64, which is constant, with respect to each of the classes, and the number of samples in each of the classesis written in a “SUM” item.

300 Experimental results will be described as follows with reference to the table.

330 330 When the level of the fourth power voltage VAINT was 0 V, in 61 samples among the 64 samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.2 V, the luminance of the display panel was the luminance (e.g., the set or predetermined luminance) or less. In addition, in the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.3 V, the luminance of the display panel was the predetermined luminance or less.

330 330 330 330 330 330 When the level of the fourth power voltage VAINT was 0.15 V, in 39 samples among the 64 samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.2 V, the luminance of the display panel was the predetermined luminance or less. In 16 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.3 V, the luminance of the display panel was the predetermined luminance or less. In 5 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.4 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.4 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.5 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.7 V, the luminance of the display panel was the predetermined luminance or less.

330 330 330 330 330 330 330 330 330 330 330 330 330 330 When the level of the fourth power voltage VAINT was 0.2 V, in 23 samples among the 64 samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.2 V, the luminance of the display panel was the predetermined luminance or less. In 18 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.3 V, the luminance of the display panel was the predetermined luminance or less. In 10 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.4 V, the luminance of the display panel was the predetermined luminance or less. In 8 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.5 V, the luminance of the display panel was the predetermined luminance or less. In 3 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.6 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.8 V, the luminance of the display panel was the predetermined luminance or less. When the level of the fourth power voltage VAINT was 0.25 V, in 5 samples among the 64 samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.2 V, the luminance of the display panel was the predetermined luminance or less. In 15 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.3 V, the luminance of the display panel was the predetermined luminance or less. In 17 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.4 V, the luminance of the display panel was the predetermined luminance or less. In 9 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.5 V, the luminance of the display panel was the predetermined luminance or less. In 11 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.6 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.7 V, the luminance of the display panel was the predetermined luminance or less. In 3 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.8 V, the luminance of the display panel was the predetermined luminance or less. In 2 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 6.1 V, the luminance of the display panel was the predetermined luminance or less.

330 330 330 330 330 330 330 330 330 330 When the level of the fourth power voltage VAINT was 0.3 V, in 4 samples among the 64 samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.3 V, the luminance of the display panel was the predetermined luminance or less. In 10 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.4 V, the luminance of the display panel was the predetermined luminance or less. In 20 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.5 V, the luminance of the display panel was the predetermined luminance or less. In 6 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.6 V, the luminance of the display panel was the predetermined luminance or less. In 10 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.7 V, the luminance of the display panel was the predetermined luminance or less. In 8 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.8 V, the luminance of the display panel was the predetermined luminance or less. In 3 samples among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 5.9 V, the luminance of the display panel was the predetermined luminance or less. In one sample among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 6.0 V, the luminance of the display panel was the predetermined luminance or less. In one sample among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 6.2 V, the luminance of the display panel was the predetermined luminance or less. In one sample among the other three samples, it was measured that, when the level of the data voltagefor displaying the image having the black grayscale was 6.3 V, the luminance of the display panel was the predetermined luminance or less.

2 FIG. Meanwhile, when the level of the fourth power voltage VAINT exceeds a predetermined level (e.g., 0.7 V), the level of the fourth power voltage VAINT may become higher than the threshold voltage of the light emitting element LE (see). The image having the black grayscale may not be displayed. Therefore, the level of the fourth power voltage VAINT may be within a range in which the level of the fourth power voltage VAINT is lower than the threshold voltage of the light emitting element LE. For example, the level of the fourth power voltage VAINT may not exceed a maximum of 0.7 V.

Also, meanwhile, the level of the fourth power voltage VAINT may be set within a range in which a display quality (e.g., a set or predetermined display quality) is satisfied. An evaluation standard for the above-described display quality may include evaluations for the problem in that frames are rapidly changed, the problem in that a luminance is changed depending on temperature, the problem in that a color blurring phenomenon occurs, and the like, which are described above. When the level of the fourth power voltage VAINT is excessively low, deterioration of the above-described display quality occurs, and therefore, the fourth power voltage VAINT may be set to a level (e.g., a set or predetermined level) or more. For example, the level of the fourth power voltage VAINT may be set to a minimum of 0.25 V or more.

4 5 FIGS.and 4 5 FIGS.and 400 are flowcharts illustrating a voltage setting methodof the electronic device according to some embodiments of the present disclosure. Althoughillustrate various operations in a voltage setting method, embodiments according to the present disclosure are not limited thereto, and according to various embodiments, the voltage setting method may include additional operations or fewer operations, or the order of operation may vary, unless otherwise state or implied, without departing from the spirit and scope of embodiments according to the present disclosure.

4 5 FIGS.and 2 FIG. In, an anode initialization voltage may correspond to the above-described fourth power voltage VAINT shown in.

400 The voltage setting methodaccording to some embodiments of the present disclosure may include a first case, a second case, and a third case.

The first case is a case where the anode initialization voltage is set within a range in which the anode initialization voltage is higher than a minimum value.

The second case is a case where the anode initialization voltage is set to have the minimum value, and a level of a data voltage for displaying an image having a black grayscale is set while the data voltage is increased.

The third case is a case where the anode initialization voltage is set to have the minimum value, and the level of the data voltage for displaying the image having the black grayscale is set while the data voltage is decreased.

The first case is as follows.

400 410 420 430 440 460 470 450 The voltage setting methodaccording to some embodiments of the present disclosure may include operation Sof setting the data voltage for displaying the image having the black grayscale to an a-th level, operation Sof applying an anode initialization voltage having a first level, operation Sof determining whether a black floating phenomenon has been observed, operation Sof decreasing the anode initialization voltage by a second level, operation Sof determining whether the anode initialization voltage has exceeded a minimum value (e.g., a set or predetermined minimum value), operation Sof applying the set anode initialization voltage, and operation Sof writing a level of the set anode initialization voltage to the display device.

410 300 30 300 3 FIG. In the operation Sof setting the data voltage for displaying the image having the black grayscale to the a-th level, the a-th level may be freely set according to a design of a person skilled in the art. In an example, referring to the above-described tableshown in, when the level of the fourth power voltageis set as 0.3 V, 5.5 V as the level of the data voltagefor displaying the image having the black grayscale, which corresponds to 20 as a most frequent value, may be set to the a-th level. However, embodiments of the present disclosure are not limited thereto.

420 In the operation Sof applying the anode initialization voltage having the first level, the first level may be freely set according to a design of a person skilled in the art. In an example, the first level may be set to 0.7 V as a maximum level of the anode initialization voltage (or the fourth power voltage), but embodiments of the present disclosure are not limited thereto.

430 In the operation Sof determining whether the black floating phenomenon has been observed, the black floating phenomenon represents that a luminance of the display panel exceeds a predetermined luminance when the data voltage for displaying the image having the black grayscale is applied, and the predetermined luminance may be freely set according to a design of a person skilled in the art. In an example, the predetermined luminance may be set to about 0.001 nit, but embodiments of the present disclosure are not limited thereto.

440 In the operation Sof decreasing the anode initialization voltage by the second level, the second level may be freely set according to a design of a person skilled in the art. In an example, the second level may be set to about 0.01 V, but embodiments of the present disclosure are not limited thereto.

460 In the operation Sof determining whether the anode initialization voltage has exceeded the predetermined minimum value, the predetermined minimum value may be freely set according to a design of a person skilled in the art. In an example, the predetermined minimum value may be about 0.25 V, but embodiments of the present disclosure are not limited thereto.

450 160 450 1 FIG. 1 FIG. In the operation Sof writing the level of the set anode initialization voltage to the display device, the level of the set anode initialization voltage may be stored in the form of a lookup table LUT in the memory MEM (see) of the above-described timing controller(see). In the same operation S, the level of the data voltage for displaying the image having the black grayscale may be stored while being set as the a-th level.

430 440 460 470 430 450 In the first case, in the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof decreasing the anode initialization voltage by the second level when the black floating phenomenon is observed. In the operation Sof determining whether the anode initialization voltage has exceeded to the predetermine minimum value, the operation Sof applying the set anode initialization voltage when the anode initialization voltage exceeds the predetermined minimum value. In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof writing the level of the set anode initialization voltage to the display device may be performed when the black floating phenomenon is not observed.

Accordingly, in the first case, the level of the anode initialization voltage can become highest. In addition, the data voltage for displaying the image having the black grayscale, which has a lowest level, in the anode initialization voltage having the corresponding level can be set.

The second case is as follows.

400 410 420 430 440 460 480 510 520 530 540 550 The voltage setting methodaccording to some embodiments of the present disclosure may include operation Sof setting a data voltage for displaying an image having a black grayscale to an a-th level, operation Sof applying an anode initialization voltage having a first level, operation Sof determining whether a black floating phenomenon has been observed, operation Sof decreasing the anode initialization voltage by a second level, operation Sof determining whether the anode initialization voltage has exceeded a predetermined minimum value, operation Sof setting the anode initialization voltage to a third level as the minimum value, operation Sof applying the anode initialization voltage having the third level, operation Sof determining whether the black floating phenomenon has been observed, operation Sof increasing a level of the data voltage for displaying the image having the black grayscale by a b-th level, operation Sof determining whether the black floating phenomenon has been observed, and operation Sof writing the level of the data voltage for displaying the image having the black grayscale to the display device.

460 In the operation Sof determining whether the anode initialization voltage has exceeded the predetermined minimum value, the anode initialization voltage may be set to the third level as the minimum value when the anode initialization voltage does not exceed the predetermined minimum value. The third level may be freely set according to a design of a person skilled in the art. For example, the third level may be the above-described 0.25 V, but embodiments of the present disclosure are not limited thereto.

520 530 In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof increasing the level of the data voltage for displaying the image having the black grayscale by the b-th level may be performed when it is determined that the black floating phenomenon has been observed. The b-th level may be freely set according to a design of a person skilled in the art. For example, the b-th level may be set within a range larger than the range of the above-described second level. The b-th level may be about 0.1 V, but embodiments of the present disclosure are not limited thereto.

540 530 In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof increasing the level of the data voltage for displaying the image having the black grayscale by the b-th level may be performed when it is determined that the black floating phenomenon has been observed.

540 550 550 160 1 FIG. 1 FIG. In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof writing the level of the data voltage for displaying the image having the black grayscale to the display device may be performed when it is determined that the black floating phenomenon has not been observed. In the same operation S, the level of the anode initialization voltage may be stored while being set to the third level. The level of the set data voltage for displaying the image having the black grayscale and the level of the set anode initialization voltage may be stored in the form of a lookup table LUT in the memory MEM (see) of the above-described timing controller(see).

Accordingly, in the second case, the level of the anode initialization voltage can be set to satisfy a predetermined display quality, and the image having the black grayscale can be stably displayed.

The third case is as follows.

400 410 420 430 440 460 480 510 520 560 570 580 590 The voltage setting methodaccording to some embodiments of the present disclosure may include operation Sof setting a data voltage for displaying an image having a black grayscale to an a-th level, operation Sof applying an anode initialization voltage having a first level, operation Sof determining whether a black floating phenomenon has been observed, operation Sof decreasing the anode initialization voltage by a second level, operation Sof determining whether the anode initialization voltage has exceeded a predetermined minimum value, operation Sof setting the anode initialization voltage to a third level as the minimum value, operation Sof applying the anode initialization voltage having the third level, operation Sof determining whether the black floating phenomenon has been observed, operation Sof decreasing a level of the data voltage for displaying the image having the black grayscale by a c-th level, operation Sof determining whether the black floating phenomenon has been observed, operation Sof increasing the level of the data voltage for displaying the image having the black grayscale by the c-th level, and operation Sof writing the level of the set data voltage for displaying the image having the black grayscale to the display device.

520 560 In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof decreasing the level of the data voltage for displaying the image having the black grayscale by the c-th level may be performed when it is determined that the black floating phenomenon has not been observed.

560 In the operation Sof decreasing the level of the data voltage for displaying the image having the black grayscale by the c-th level, the c-th level may be freely set according to a design of a person skilled in the art. In an example, the c-th level may be equal to the b-th level. In an example, the c-th level about 0.1 V. However, embodiments of the present disclosure are not limited thereto.

570 580 In the operation Sof determining whether the black floating phenomenon has been observed, the operation Sof increasing the level of the data voltage for displaying the image having the black grayscale by the c-th level may be performed when it is determined that the black floating phenomenon has been observed. Accordingly, the level of the data voltage for displaying the image having the black grayscale may be set to be lowest within a range in which the black floating phenomenon does not occur.

590 160 590 1 FIG. 1 FIG. In the operation Sof writing the level of the set data voltage for displaying the image having the black grayscale to the display device, the level of the data voltage for displaying the image having the black grayscale may be stored in the form of a lookup table LUT in the memory MEM (see) of the above-described timing controller(see). In the same operation S, the level of the anode initialization voltage may be stored while being set to the third level.

Accordingly, in the third case, the level of the anode initialization voltage can be set to satisfy a predetermined display quality, and the level of the data voltage for displaying the image having the black grayscale is set to be lowest, so that power consumption can be relatively reduced.

In the electronic device and the voltage setting method thereof according to some embodiments of the present disclosure, display quality can be relatively improved and power consumption can be relatively reduced.

Aspects of some embodiments of the present disclosure have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. According to some embodiments, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with particular embodiments may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims, and their equivalents.